ninja: Entering directory `out/gn'
[0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix)
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
-- Testing: 27911 tests, 64 workers --
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (1 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/63169) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bca6f3656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bca6f33505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bca6f36cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0007733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f000778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0007733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f000771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bca6ecc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bca6ecc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bca6eb0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bca6b60166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bca6b5fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f000771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f000771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f000771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bca6b5fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (2 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c37db0856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c37db05505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c37db08cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8042f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8042f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8042f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8042f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c37da9e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c37da9e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c37da82f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c37d732166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c37d731e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8042f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8042f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8042f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c37d731d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (3 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__p2.addr.i3 = alloca <4 x half>, align 8
# |   %__ret.i4 = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i3, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %13, ptr %__ret.i4, align 8
# |   %14 = load <4 x half>, ptr %__ret.i4, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__p1.addr.i2 = alloca <8 x half>, align 16
# |   %__p2.addr.i3 = alloca <8 x half>, align 16
# |   %__ret.i4 = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i1, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i3, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %13, ptr %__ret.i4, align 16
# |   %14 = load <8 x half>, ptr %__ret.i4, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <4 x half>, ptr %__s0, align 8
# |   %4 = load <4 x half>, ptr %__s1, align 8
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <4 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %9 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i, align 8
# |   store <4 x half> %4, ptr %__p1.addr.i, align 8
# |   store <4 x half> %9, ptr %__p2.addr.i, align 8
# |   %10 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %13 = bitcast <8 x i8> %10 to <4 x half>
# |   %14 = bitcast <8 x i8> %11 to <4 x half>
# |   %15 = bitcast <8 x i8> %12 to <4 x half>
# |   %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13)
# |   store <4 x half> %16, ptr %ref.tmp.i, align 8
# |   %17 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %17, ptr %__ret.i, align 8
# |   %18 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %18, ptr %__ret, align 8
# |   %19 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %19, ptr %tmp, align 8
# |   %20 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %20
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <8 x half>, ptr %__s0, align 16
# |   %4 = load <8 x half>, ptr %__s1, align 16
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <8 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3
# |   %9 = load half, ptr %__s2, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4
# |   %10 = load half, ptr %__s2, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5
# |   %11 = load half, ptr %__s2, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6
# |   %12 = load half, ptr %__s2, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %13 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i, align 16
# |   store <8 x half> %4, ptr %__p1.addr.i, align 16
# |   store <8 x half> %13, ptr %__p2.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %15 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %16 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %17 = bitcast <16 x i8> %14 to <8 x half>
# |   %18 = bitcast <16 x i8> %15 to <8 x half>
# |   %19 = bitcast <16 x i8> %16 to <8 x half>
# |   %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17)
# |   store <8 x half> %20, ptr %ref.tmp.i, align 16
# |   %21 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %21, ptr %__ret.i, align 16
# |   %22 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %22, ptr %__ret, align 16
# |   %23 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %23, ptr %tmp, align 16
# |   %24 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half
# | ...
# `---data was truncated (10240/31903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ab2a51556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab2a512505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab2a515cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffacfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffacfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffacfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffacfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab2a4ab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab2a4ab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab2a48ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab2a13f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab2a13ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffacfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffacfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffacfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab2a13ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (4 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f59332756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f593324505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f593327cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d90449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d90449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d90431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5932bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5932bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5932a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f592f51166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f592f50e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d90432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d904330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f592f50d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (5 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d16107b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d161078505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d16107bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7237f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7237f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7237f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7237eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d16101123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d161011086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d160ff5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d160ca5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d160ca4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7237eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7237eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7237eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d160ca4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (6 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c01a84c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c01a849505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c01a84ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb61f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb61f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb61f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb61f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c01a7e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c01a7e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c01a7c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c01a476166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c01a475e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdb61f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb61f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb61f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c01a475d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (7 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfe239756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bfe2394505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bfe2397cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdd7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdd7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdd7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdd7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfe232d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bfe232d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bfe2311f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bfe1fc1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bfe1fc0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbdd7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdd7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdd7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfe1fc0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (8 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3a22e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a3a22e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a3a22e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9626049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96260a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9626049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9626031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3a227c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a3a227c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a3a2260f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a3a1f10166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a3a1f0fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9626032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96260330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96260330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3a1f0fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (9 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmmla_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b3e66b956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b3e66b6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b3e66b9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4a3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4a378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4a3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4a371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3e664f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b3e664f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b3e6633f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b3e62e3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b3e62e2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4a371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4a371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4a371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3e62e2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (10 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/33198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8ec43256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8ec42f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8ec432cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9c4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9c4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9c4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9c4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8ec3c823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8ec3c8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8ec3acf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8ec05c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8ec05be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb9c4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9c4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9c4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8ec05bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (11 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa661a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa661a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa661a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7394f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7394f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7394f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7394eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa6613a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa6613a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa6611ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa65dce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa65dcde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7394eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7394eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7394eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa65dcdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (12 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1
# | ...
# `---data was truncated (10240/26772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055794897856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557948975505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557948978cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff808e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff808ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff808e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff808e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055794890e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055794890e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579488f2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579485a2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579485a1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff808e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff808e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff808e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579485a1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (13 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b46ab0656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b46ab03505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b46ab06cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f315d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f315d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f315d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f315d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b46aa9c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b46aa9c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b46aa80f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b46a730166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b46a72fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f315d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f315d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f315d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b46a72fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (14 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055687e8ba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055687e8b7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055687e8bacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f128a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f128a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f128a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f128a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055687e85023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055687e850086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055687e834f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055687e4e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055687e4e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f128a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f128a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f128a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055687e4e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (15 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584c5ca556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005584c5ca2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005584c5ca5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff00d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff00d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff00d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff00d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584c5c3b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005584c5c3b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005584c5c1ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005584c58cf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005584c58cee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff00d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff00d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff00d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584c58ced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (16 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/62964) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056466e48b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056466e488505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056466e48bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27bb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27bb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27bb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27bb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056466e42123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056466e421086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056466e405f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056466e0b5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056466e0b4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f27bb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27bb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27bb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056466e0b4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (17 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fcee9956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564fcee96505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564fcee99cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0413e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0413e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0413e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0413e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fcee2f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564fcee2f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564fcee13f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564fceac3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564fceac2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0413e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0413e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0413e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fceac2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (18 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.ad
# | ...
# `---data was truncated (10240/16274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e62fcef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e62fcec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e62fcefcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8277449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82774a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8277449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8277431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e62fc8523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e62fc85086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e62fc69f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e62f919166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e62f918e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8277432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82774330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82774330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e62f918d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (19 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fd54cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559fd54c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559fd54cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdcc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdcc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdcc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdcc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fd546123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559fd5461086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559fd5445f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559fd50f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559fd50f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcdcc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdcc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdcc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fd50f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (20 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e5cf9e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e5cf9b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e5cf9ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c1f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c1f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c1f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c1f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e5cf3423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e5cf34086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e5cf18f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e5cbc8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e5cbc7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c1f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c1f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c1f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e5cbc7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (21 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cf231e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564cf231b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564cf231ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa088533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa08858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa088533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa08851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cf22b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564cf22b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564cf2298f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564cf1f48166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564cf1f47e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa08851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa08851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa08851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cf1f47d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (22 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x
# | ...
# `---data was truncated (10240/29379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607f7c8656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005607f7c83505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005607f7c86cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa92ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa92cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa92ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa92ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607f7c1c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005607f7c1c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005607f7c00f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607f78b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607f78afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa92ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa92ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa92ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607f78afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (23 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056144a73156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056144a72e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056144a731cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde57a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde57a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde57a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde57a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056144a6c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056144a6c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056144a6abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056144a35b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056144a35ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde57a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde57a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde57a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056144a35ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (24 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf3556656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bf35563505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bf35566cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f2c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f2c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f2c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f2c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf354fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bf354fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bf354e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bf35190166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bf3518fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2f2c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f2c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f2c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf3518fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (25 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %.splat, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560f1019256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560f1018f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560f10192cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9753133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f975318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9753133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f975311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f1012823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560f10128086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560f1010cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560f0fdbc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560f0fdbbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f975311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f975311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f975311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f0fdbbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (26 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e25cfd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564e25cfa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564e25cfdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7638933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f763898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7638933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f763891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e25c9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564e25c93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564e25c77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564e25927166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564e25926e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f763891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f763891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f763891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e25926d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (27 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i6
# | ...
# `---data was truncated (10240/11946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4623b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a4623b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a4623b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f68533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f6858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f68533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f6851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a46234e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a46234e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a462332f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a461fe2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a461fe1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4f6851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f6851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f6851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a461fe1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (28 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055646b9af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055646b9ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055646b9afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d57c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d57ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d57c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d57c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055646b94523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055646b945086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055646b929f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055646b5d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055646b5d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6d57c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d57c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d57c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055646b5d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (29 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff1336456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ff13361505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ff13364cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f242c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f242c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f242c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f242c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff132fa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ff132fa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ff132def39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ff12f8e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ff12f8de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f242c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f242c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f242c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff12f8dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (30 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055683ba4556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055683ba42505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055683ba45cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f59133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f5918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f59133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f5911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055683b9db23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055683b9db086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055683b9bff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055683b66f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055683b66ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f5911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f5911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f5911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055683b66ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (31 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559b797d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559b797a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559b797dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1947249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19472a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1947249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1947231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559b791323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559b7913086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559b78f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559b75a7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559b75a6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1947232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19472330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19472330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559b75a6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (32 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 4 x 
# | ...
# `---data was truncated (10240/142016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ff6c6c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ff6c69505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ff6c6ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd11501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1150725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd11501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd115003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ff6c0223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ff6c02086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ff6be6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ff6896166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ff6895e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd115004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1150050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1150050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ff6895d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (33 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa4f1fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aa4f1fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aa4f1fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aa2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aa295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aa2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aa28ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa4f19323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aa4f193086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aa4f177f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aa4ee27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aa4ee26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9aa28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aa28ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aa28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa4ee26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (34 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636261e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636261e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636261e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd8ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd8eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd8ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd8ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056362617d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056362617d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563626161f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563625e11166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563625e10e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd8ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd8ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd8ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563625e10d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (35 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de85ffe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de85ffb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de85ffecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe811e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe811ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe811e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe811e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de85f9423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de85f94086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de85f78f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de85c28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de85c27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe811e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe811e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe811e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de85c27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve/recps.c (36 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecps_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecps_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecps_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000557b0afe456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b0afe1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b0afe4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e67a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e67aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e67a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e67a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b0af7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b0af7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b0af5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b0ac0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b0ac0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e67a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e67a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e67a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b0ac0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (37 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c728adf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c728adc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c728adfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3932f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3932f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3932f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3932f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c728a7523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c728a75086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c728a59f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c728709166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c728708e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3932f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3932f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3932f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c728708d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (38 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563965e1956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563965e16505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563965e19cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e1d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e1d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e1d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e1d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563965daf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563965daf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563965d93f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563965a43166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563965a42e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4e1d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e1d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e1d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563965a42d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (39 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cbad5a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cbad57505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cbad5acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a99533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a9958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a99533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a9951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cbacf023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cbacf0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cbacd4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cba984166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cba983e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a9951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a9951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a9951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cba983d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (40 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ee5b2856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561ee5b25505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561ee5b28cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b0da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b0daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b0da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b0da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ee5abe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561ee5abe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561ee5aa2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561ee5752166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561ee5751e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b0da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b0da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b0da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ee5751d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (41 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset
# | ...
# `---data was truncated (10240/287213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b75f4856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b75f45505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b75f48cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38c0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38c04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38c0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38c0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b75ede23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b75ede086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b75ec2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b75b72166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b75b71e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f38c0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38c04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38c04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b75b71d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (42 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e09f59d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e09f59a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e09f59dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19fb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19fb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19fb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19fb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e09f53323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e09f533086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e09f517f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e09f1c7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e09f1c6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f19fb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19fb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19fb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e09f1c6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (43 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd07d4d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd07d4a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd07d4dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26bfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26bfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26bfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26bfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd07ce323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd07ce3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd07cc7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd07977166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd07976e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f26bfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26bfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26bfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd07976d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (44 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1)
# |   ret float %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1)
# |   ret double %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1)
# |   ret float %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1)
# |   ret double %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1)
# |   ret float %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1)
# |   ret double %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1)
# |   ret float %frint64x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1)
# |   ret double %frint64x.i
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32x.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64x.f64(double) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1dba7256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f1dba6f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f1dba72cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d1b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d1b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d1b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d1b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1dba0823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f1dba08086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f1db9ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f1db69c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f1db69be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d1b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d1b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d1b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1db69bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (45 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s16_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, <vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u16_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <v
# | ...
# `---data was truncated (10240/25017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b44506256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b44505f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b445062cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7403733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f740378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7403733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f740371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b444ff823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b444ff8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b444fdcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b444c8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b444c8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f740371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f740371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f740371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b444c8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (46 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> 
# | ...
# `---data was truncated (10240/16951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055889a5ec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055889a5e9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055889a5eccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b9a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b9a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b9a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b9a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055889a58223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055889a582086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055889a566f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055889a216166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055889a215e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b9a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b9a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b9a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055889a215d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (47 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e5353e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564e5353b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564e5353ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0da4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0da46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0da4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0da4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e534d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564e534d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564e534b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564e53168166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564e53167e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0da4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0da46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0da46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e53167d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (48 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e250b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e250b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e250b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a71933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a7198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a71933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a7191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e2504a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e2504a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e2502ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e24cde166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e24cdde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a7191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a7191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a7191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e24cddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (49 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567702e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005567702e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005567702e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba4b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba4b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba4b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba4b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055677027d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055677027d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556770261f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055676ff11166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055676ff10e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fba4b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba4b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba4b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055676ff10d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (50 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloc
# | ...
# `---data was truncated (10240/122004) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f89255056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f89254d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f892550cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2b5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2b56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2b5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2b5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8924e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f8924e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f8924caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f89217a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f892179e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa2b5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2b56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2b56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f892179d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (51 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d46641d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d46641a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d46641dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f374c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f374c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f374c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f374c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4663b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d4663b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d466397f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d466047166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d466046e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f374c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f374c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f374c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d466046d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (52 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fbab4d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562fbab4a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562fbab4dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1ea849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1ea8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1ea849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1ea831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fbaae323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562fbaae3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562fbaac7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562fba777166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562fba776e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd1ea832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1ea8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1ea8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fba776d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (53 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d848da56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559d848d7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559d848dacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6250905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f625095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6250905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62508ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d8487023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559d84870086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559d84854f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559d84504166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559d84503e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62508eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62508ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62508ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d84503d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (54 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056071a9d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056071a9d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056071a9d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae72b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae72b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae72b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae72b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056071a96e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056071a96e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056071a952f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056071a602166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056071a601e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae72b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae72b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae72b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056071a601d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (55 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3)
# |   store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3)
# |   store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x2_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x2_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [2 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4)
# |   store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x2_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x2_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [2 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4)
# |   store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x3_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x3_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [3 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <8 x i8>, ptr %arrayidx4.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5)
# |   store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x3_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x3_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [3 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <16 x i8>, ptr %arrayidx4.i, align 16
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5)
# |   store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x4_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x4_t, align 8
# |   %b.a
# | ...
# `---data was truncated (10240/125901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ecff4956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ecff46505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ecff49cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7eb7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7eb798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7eb7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7eb791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ecfedf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ecfedf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ecfec3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ecfb73166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ecfb72e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7eb791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7eb791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7eb791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ecfb72d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (56 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/424049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562377a1f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562377a1c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562377a1fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd92cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd92cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd92cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd92cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623779b523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005623779b5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562377999f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562377649166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562377648e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd92cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd92cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd92cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562377648d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (57 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056428424d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056428424a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056428424dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc43249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc432a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc43249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc43231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642841e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005642841e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005642841c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564283e77166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564283e76e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc43232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc432330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc432330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564283e76d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (58 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea1121c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea11219505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea1121ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ff8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ff82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ff8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ff8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea111b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea111b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea11196f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea10e46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea10e45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ff8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ff82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ff82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea10e45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (59 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splat
# | ...
# `---data was truncated (10240/24132) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005650d4a1a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005650d4a17505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005650d4a1acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47fa105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47fa15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47fa105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47fa0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650d49b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005650d49b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005650d4994f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005650d4644166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005650d4643e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47fa0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47fa0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47fa0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650d4643d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (60 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <4 x half>, align 8
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6)
# |   store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %9 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %9, ptr %__ret, align 8
# |   %10 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %10, ptr %tmp, align 8
# |   %11 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <16 x i8>, align 16
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   store <16 x i8> %2, ptr %__s2, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <16 x i8>, ptr %__s2, align 16
# |   %7 = load i64, ptr %__s4, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %8, ptr %__ret, align 8
# |   %9 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %9, ptr %tmp, align 8
# |   %10 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <16 x i8>, ptr %__s0, align 16
# |   %5 = load <16 x i8>, ptr %__s1, align 16
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3)
# |   store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16
# |   %9 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <
# | ...
# `---data was truncated (10240/24508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000556581a5256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556581a4f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556581a52cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4662f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4662f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4662f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4662eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565819e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565819e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565819ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055658167c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055658167be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4662eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4662eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4662eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055658167bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (61 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b099aef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b099aec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b099aefcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f8d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f8d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f8d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f8d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b099a8523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b099a85086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b099a69f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b099719166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b099718e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f8d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f8d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f8d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b099718d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (62 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align
# | ...
# `---data was truncated (10240/30281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000056360fa9256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056360fa8f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056360fa92cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf87733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf8778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf87733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf8771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056360fa2823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056360fa28086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056360fa0cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056360f6bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056360f6bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdf8771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf8771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf8771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056360f6bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (63 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0d8c2456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f0d8c21505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f0d8c24cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f518a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f518a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f518a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f518a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0d8bba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0d8bba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0d8b9ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f0d884e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f0d884de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f518a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f518a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f518a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0d884dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (64 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |  
# | ...
# `---data was truncated (10240/22074) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055609ffa956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055609ffa6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055609ffa9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d4bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d4bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d4bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d4bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055609ff3f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055609ff3f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055609ff23f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055609fbd3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055609fbd2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d4bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d4bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d4bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055609fbd2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (65 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota
# | ...
# `---data was truncated (10240/94681) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f268f7b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f268f78505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f268f7bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dbee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dbeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dbee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dbee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f268f1123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f268f11086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f268ef5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f268ba5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f268ba4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0dbee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dbee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dbee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f268ba4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (66 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a4e4df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564a4e4dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564a4e4dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18a0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18a0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18a0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18a0eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a4e47523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564a4e475086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564a4e459f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564a4e109166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564a4e108e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f18a0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18a0eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18a0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a4e108d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (67 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   
# | ...
# `---data was truncated (10240/169917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610306a856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005610306a5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005610306a8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e9bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e9bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e9bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e9bc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056103063e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056103063e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561030622f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005610302d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005610302d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1e9bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e9bc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e9bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610302d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (68 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641cc25e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005641cc25b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005641cc25ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f400aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f400aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f400aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f400aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641cc1f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005641cc1f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005641cc1d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005641cbe88166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005641cbe87e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f400aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f400aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f400aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641cbe87d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (69 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# | 
# | ...
# `---data was truncated (10240/100521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055857525556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558575252505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558575255cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3c5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3c52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3c5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3c5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585751eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005585751eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005585751cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558574e7f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558574e7ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd3c5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3c52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3c52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558574e7ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (70 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603e807f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603e807c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603e807fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a87c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a87ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a87c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a87c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603e801523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005603e8015086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005603e7ff9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005603e7ca9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005603e7ca8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a87c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a87c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a87c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603e7ca8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (71 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c5043c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c50439505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c5043ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5759849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57598a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5759849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5759831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c503d223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c503d2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c503b6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c50066166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c50065e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5759832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57598330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57598330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c50065d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (72 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bba8bd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bba8ba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bba8bdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7fff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7fff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7fff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7fff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bba85323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bba853086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bba837f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bba4e7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bba4e6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff7fff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7fff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7fff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bba4e6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (73 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dbe98d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556dbe98a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556dbe98dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef06305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef0635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef06305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef062ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dbe92323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556dbe923086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556dbe907f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556dbe5b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556dbe5b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef062eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef062ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef062ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dbe5b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (74 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621071a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056210719d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005621071a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8350b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8350b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8350b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8350b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210713623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562107136086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056210711af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562106dca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562106dc9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8350b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8350b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8350b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562106dc9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (75 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/150951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adfd9bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055adfd9b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055adfd9bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb63a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb63a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb63a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb63a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adfd95223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055adfd952086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055adfd936f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055adfd5e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055adfd5e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb63a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb63a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb63a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adfd5e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (76 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b7cfe256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b7cfdf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b7cfe2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aa3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aa3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aa3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aa3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b7cf7823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b7cf78086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b7cf5cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b7cc0c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b7cc0be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3aa3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aa3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aa3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b7cc0bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (77 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store
# | ...
# `---data was truncated (10240/79497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ce982b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ce9828505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ce982bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f574c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f574c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f574c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f574c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ce97c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ce97c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ce97a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ce9455166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ce9454e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f574c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f574c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f574c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ce9454d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (78 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c4e8f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c4e8ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c4e8f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87a6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87a6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87a6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87a6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c4e88723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c4e887086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c4e86bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c4e51b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c4e51ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87a6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87a6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87a6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c4e51ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (79 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e59678556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e596782505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e596785cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3307533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f330758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3307533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f330751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e59671b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e59671b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e5966fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e5963af166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e5963aee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f330751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f330751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f330751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5963aed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (80 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eadd73256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eadd72f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eadd732cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe635649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6356a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe635649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe635631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eadd6c823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eadd6c8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eadd6acf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eadd35c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eadd35be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe635632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6356330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6356330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eadd35bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (81 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562341bcd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562341bca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562341bcdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc354249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3542a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc354249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc354231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562341b6323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562341b63086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562341b47f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005623417f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005623417f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc354232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3542330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3542330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623417f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (82 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558312b1156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558312b0e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558312b11cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78bda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78bdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78bda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78bda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558312aa723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558312aa7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558312a8bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055831273b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055831273ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78bda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78bda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78bda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055831273ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (83 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @
# | ...
# `---data was truncated (10240/18570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b451d2356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b451d20505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b451d23cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74d2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74d2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74d2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74d2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b451cb923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b451cb9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b451c9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b45194d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b45194ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f74d2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74d2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74d2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b45194cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (84 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2q_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svld2q_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2q_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | d
# | ...
# `---data was truncated (10240/75038) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f4b685e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4b685b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4b685ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1861049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18610a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1861049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1861031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4b67f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f4b67f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f4b67d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4b6488166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4b6487e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1861032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18610330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18610330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4b6487d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (85 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5a853656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5a8533505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5a8536cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f404e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f404e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f404e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f404e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5a84cc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5a84cc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5a84b0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5a8160166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5a815fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f404e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f404e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f404e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5a815fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (86 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @test_vlenb() #0 {
# | entry:
# |   %0 = call i32 @llvm.read_register.i32(metadata !4)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.read_register.i32(metadata) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"vlenb"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x000055bad08e056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bad08dd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bad08e0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc913d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc913d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc913d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc913d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad087623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bad0876086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bad085af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bad050a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bad0509e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc913d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc913d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc913d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad0509d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (87 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.a
# | ...
# `---data was truncated (10240/63518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e5adbf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e5adbc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e5adbfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f432bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f432bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f432bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f432bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e5ad5523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e5ad55086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e5ad39f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e5a9e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e5a9e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f432bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f432bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f432bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e5a9e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (88 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df6b13656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055df6b133505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055df6b136cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd22b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd22b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd22b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd22aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df6b0cc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055df6b0cc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055df6b0b0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055df6ad60166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055df6ad5fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd22aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd22aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd22aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df6ad5fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (89 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d5866056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d5865d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d58660cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71e2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71e258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71e2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71e251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d585f623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d585f6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d585daf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d5828a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d58289e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f71e251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71e251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71e251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d58289d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (90 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a49d32d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a49d32a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a49d32dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbb8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbb8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbb8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbb8ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a49d2c323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a49d2c3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a49d2a7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a49cf57166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a49cf56e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffbb8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbb8cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbb8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a49cf56d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (91 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622ffae556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005622ffae2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005622ffae5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2a6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2a698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2a6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2a691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622ffa7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005622ffa7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005622ffa5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005622ff70f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005622ff70ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2a691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2a691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2a691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622ff70ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (92 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bfb466a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bfb4667505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bfb466acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa58b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa58b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa58b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa58b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfb460023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bfb4600086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bfb45e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bfb4294166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bfb4293e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa58b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa58b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa58b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfb4293d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (93 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1077e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1077de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1077e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5142133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f514218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5142133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f514211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c10777723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c107777086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c10775bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c10740b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c10740ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f514211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f514211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f514211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c10740ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (94 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecfa0ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ecfa0ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ecfa0aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff682733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff68278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff682733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff68271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecfa04423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ecfa044086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ecfa028f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ecf9cd8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ecf9cd7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff68271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff68271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff68271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecf9cd7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (95 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f3236356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563f32360505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563f32363cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3ff133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3ff18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3ff133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3ff11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f322f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563f322f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563f322ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563f31f8d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563f31f8ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff3ff11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3ff11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3ff11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f31f8cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (96 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmmla_f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 4 x float>, align 16
# |   %z.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 4 x float> %y, ptr %y.addr, align 16
# |   store <vscale x 4 x float> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %y.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564c2992056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c2991d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c29920cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9152249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91522a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9152249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9152231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c298b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c298b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c2989af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c2954a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c29549e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9152232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91522330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91522330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c29549d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (97 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nounwind }
# | attributes #2 = { nounwind memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e16fdf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e16fdc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e16fdfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd44fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd44fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd44fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd44fa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e16f7523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e16f75086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e16f59f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e16c09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e16c08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd44fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd44fa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd44fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e16c08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (98 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16mf8(<vscale x 8 x half> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d986d4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d986d4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d986d4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ebb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ebb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ebb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ebb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d986ce523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d986ce5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d986cc9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d986979166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d986978e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ebb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ebb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ebb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d986978d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (99 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   
# | ...
# `---data was truncated (10240/17236) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2f92c956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2f92c6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2f92c9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7fb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7fb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7fb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7fb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2f925f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2f925f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2f9243f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2f8ef3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2f8ef2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe7fb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7fb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7fb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2f8ef2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (100 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x
# | ...
# `---data was truncated (10240/51854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556b97fa856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b97fa5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b97fa8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe11d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe11d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe11d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe11d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b97f3e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b97f3e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b97f22f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b97bd2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b97bd1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe11d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe11d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe11d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b97bd1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4a923356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4a9230505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4a9233cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb710b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb710b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb710b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb710b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4a91c923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f4a91c9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f4a91adf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4a8e5d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4a8e5ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb710b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb710b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb710b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4a8e5cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (102 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2, <vscale x 16 x i8> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %data.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 0
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 1
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 2
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 3
# |   call void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, <vscale x 16 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2, <vscale x 8 x i16> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %data.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 0
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 1
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 2
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 3
# |   %11 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10, <vscale x 8 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2, <vscale x 4 x i32> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %data.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 0
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 1
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 2
# |   %10 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 3
# |   %11 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10, <vscale x 4 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2, <vscale x 2 x i64> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %da
# | ...
# `---data was truncated (10240/73307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559dc983156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559dc982e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559dc9831cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f0a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f0a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f0a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f0a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dc97c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559dc97c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559dc97abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559dc945b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559dc945ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2f0a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f0a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f0a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dc945ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0c1fb556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0c1fb2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0c1fb5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24d761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24d76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24d761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24d7603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0c1f4b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c0c1f4b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c0c1f2ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c0c1bdf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c0c1bdee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f24d7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24d76050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24d76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0c1bded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (104 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svuzp_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svuzp_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svuzp_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556ddc61b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ddc618505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ddc61bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd742249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd742249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd742231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ddc5b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ddc5b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ddc595f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ddc245166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ddc244e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd742232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7422330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ddc244d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @foo() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @bar() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @baz(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @quux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %call = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %call
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abe079c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055abe0799505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055abe079ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2743649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27436a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2743649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2743631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abe073223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055abe0732086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055abe0716f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055abe03c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055abe03c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2743632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27436330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27436330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abe03c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x float
# | ...
# `---data was truncated (10240/338684) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d40120456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d401201505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d401204cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2842f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2842f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2842f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2842f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d40119a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d40119a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d40117ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d400e2e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d400e2de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2842f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2842f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2842f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d400e2dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractva
# | ...
# `---data was truncated (10240/22708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590a1f9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005590a1f99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005590a1f9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa854533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa85458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa854533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa85451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590a1f3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005590a1f32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005590a1f16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005590a1bc6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005590a1bc5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa85451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa85451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa85451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590a1bc5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9c135756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d9c1354505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d9c1357cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0591333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f059138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0591333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f059131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9c12ed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9c12ed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9c12d1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9c0f81166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9c0f80e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f059131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f059131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f059131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9c0f80d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5e3dfa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5e3df7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5e3dfacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4635049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46350a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4635049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4635031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5e3d9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5e3d90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5e3d74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5e3a24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5e3a23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4635032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46350330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46350330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5e3a23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve/orv.c (110 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055f806fdf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f806fdc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f806fdfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5149333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f514938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5149333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f514931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f806f7523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f806f75086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f806f59f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f806c09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f806c08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f514931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f514931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f514931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f806c08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b91599556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b915992505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b915995cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cd3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cd338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cd3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cd331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b91592b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b91592b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b91590ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9155bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9155bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1cd331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cd331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cd331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9155bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (112 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %a.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %b.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x bfloat> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c3e2d9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c3e2d8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c3e2d90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20a7305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20a735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20a7305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20a72ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3e2d2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3e2d26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3e2d0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c3e29ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c3e29b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f20a72eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20a72ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20a72ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3e29b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e7646756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e76464505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e76467cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f948cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f948cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f948cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f948caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e763fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e763fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e763e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e76091166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e76090e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f948caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f948caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f948caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e76090d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f90e2356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560f90e20505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560f90e23cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb624b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb624b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb624b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb624b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f90db923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560f90db9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560f90d9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560f90a4d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560f90a4ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb624b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb624b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb624b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f90a4cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x
# | ...
# `---data was truncated (10240/164783) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609abdc856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005609abdc5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005609abdc8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a81849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a818a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a81849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a81831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609abd5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005609abd5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005609abd42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005609ab9f2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005609ab9f1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1a81832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a818330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a818330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609ab9f1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (116 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtssel_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtssel_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtssel_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b47bc8856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b47bc85505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b47bc88cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fc5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fc5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fc5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fc5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b47bc1e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b47bc1e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b47bc02f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b47b8b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b47b8b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4fc5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fc5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fc5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b47b8b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df52f5156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055df52f4e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055df52f51cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe297305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe29735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe297305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2972ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df52ee723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055df52ee7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055df52ecbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055df52b7b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055df52b7ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe2972eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2972ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2972ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df52b7ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e03a1356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e03a10505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e03a13cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f332c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f332c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f332c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f332c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e039a923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e039a9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e0398df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e0363d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e0363ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f332c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f332c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f332c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e0363cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaec07856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eaec075505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eaec078cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbc0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbc058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbc0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbc051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaec00e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eaec00e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eaebff2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eaebca2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eaebca1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcbc051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbc051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbc051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaebca1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638e071156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638e070e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638e0711cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaf0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaf0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaf0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaf0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638e06a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638e06a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638e068bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638e033b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638e033ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffaf0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaf0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaf0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638e033ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f2a56756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f2a564505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f2a567cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9a1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9a1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9a1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9a1c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f2a4fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f2a4fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f2a4e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f2a191166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f2a190e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9a1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9a1c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9a1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f2a190d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a78408c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a784089505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a78408ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe040733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe04078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe040733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe04071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a78402223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a784022086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a784006f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a783cb6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a783cb5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe04071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe04071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe04071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a783cb5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6244a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f6244a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f6244a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6320049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63200a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6320049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6320031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f62443923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f624439086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f62441df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f6240cd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f6240cce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6320032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63200330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63200330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6240ccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %
# | ...
# `---data was truncated (10240/66087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589fb98756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589fb984505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589fb987cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bdd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bdd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bdd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bdd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589fb91d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589fb91d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589fb901f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589fb5b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589fb5b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8bdd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bdd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bdd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589fb5b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/100952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b2784c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b27849505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b2784ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5742449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5742449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5742431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b277e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b277e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b277c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b27476166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b27475e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5742432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57424330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b27475d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <
# | ...
# `---data was truncated (10240/14421) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056481239256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056481238f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564812392cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41a0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41a00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41a0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41a0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056481232823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564812328086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056481230cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564811fbc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564811fbbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f41a0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41a00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41a00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564811fbbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f05be156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f05bde505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f05be1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52e7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52e78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52e7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52e7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f05b7723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f05b77086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f05b5bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f0580b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f0580ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f52e7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52e78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52e78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f0580ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc5b9d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc5b9d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc5b9d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f66b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f66b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f66b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f66b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc5b96d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc5b96d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc5b951f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc5b601166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc5b600e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f66b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f66b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f66b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc5b600d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, al
# | ...
# `---data was truncated (10240/169925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abf287956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055abf2876505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055abf2879cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38c8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38c8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38c8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38c8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abf280f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055abf280f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055abf27f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055abf24a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055abf24a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f38c8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38c8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38c8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abf24a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba9d3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fba9d2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fba9d31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa01cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa01cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa01cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa01caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba9cc723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fba9cc7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fba9cabf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fba995b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fba995ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa01caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa01caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa01caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba995ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556699bb656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556699bb3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556699bb6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c21a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c21aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c21a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c21a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556699b4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556699b4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556699b30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005566997e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005566997dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c21a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c21a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c21a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566997dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646b48f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646b48f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646b48f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ab9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ab9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ab9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ab9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646b488d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646b488d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646b4871f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646b4521166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646b4520e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0ab9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ab9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ab9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646b4520d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587336ef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587336ec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587336efcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c19449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c194a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c19449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c19431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055873368523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558733685086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558733669f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558733319166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558733318e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c19432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c194330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c194330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558733318d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a673ca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558a673c7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558a673cacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46a1a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46a1a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46a1a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46a1a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a6736023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558a67360086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558a67344f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558a66ff4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558a66ff3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f46a1a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46a1a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46a1a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a66ff3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/67482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a61fa9356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a61fa90505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a61fa93cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4145533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f414558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4145533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f414551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a61fa2923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a61fa29086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a61fa0df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a61f6bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a61f6bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f414551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f414551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f414551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a61f6bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_
# | ...
# `---data was truncated (10240/11895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055688e7f856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055688e7f5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055688e7f8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5260649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52606a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5260649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5260631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055688e78e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055688e78e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055688e772f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055688e422166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055688e421e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5260632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52606330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52606330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055688e421d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c2d6c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c2d6bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c2d6c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa84a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa84a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa84a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa84a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c2d65823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c2d658086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c2d63cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c2d2ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c2d2ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa84a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa84a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa84a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c2d2ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d51d2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d51d27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d51d2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43d3505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43d355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43d3505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43d34ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d51cc023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d51cc0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d51ca4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d51954166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d51953e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f43d34eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43d34ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43d34ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d51953d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649c90cf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649c90cc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649c90cfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff42a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff42a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff42a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff42a4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649c906523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005649c9065086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005649c9049f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005649c8cf9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005649c8cf8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff42a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff42a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff42a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649c8cf8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (140 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalb_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561913f8c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561913f89505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561913f8ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3eb0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3eb00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3eb0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3eb0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561913f2223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561913f22086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561913f06f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561913bb6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561913bb5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3eb0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3eb00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3eb00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561913bb5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i
# | ...
# `---data was truncated (10240/51303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b3e8d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b3e8d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b3e8d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd778449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd778449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd778431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b3e86e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b3e86e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b3e852f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b3e502166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b3e501e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd778432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7784330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b3e501d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (142 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559b81f2356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559b81f20505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559b81f23cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff39d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff39d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff39d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff39d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b81eb923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559b81eb9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559b81e9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559b81b4d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559b81b4ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff39d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff39d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff39d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b81b4cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (143 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   store <vscale x 4 x i32> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %1, 1
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, <vscale x 4 x i32> %2, 2
# |   %7 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, <vscale x 4 x i32> %3, 3
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate4_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2, <vscale x 2 x i64> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   %x4.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   store <vscale x 2 x i64> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %1, 1
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, <vscale x 2 x i64> %2, 2
# |   %7 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, <vscale x 2 x i64> %3, 3
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vs
# | ...
# `---data was truncated (10240/21212) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055703537656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557035373505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557035376cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49e7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49e72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49e7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49e7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055703530c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055703530c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570352f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557034fa0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557034f9fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f49e7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49e72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49e72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557034f9fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc2614656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fc26143505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fc26146cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48d3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48d38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48d3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48d3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc260dc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fc260dc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fc260c0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fc25d70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fc25d6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f48d3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48d38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48d38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc25d6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (145 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnda.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i)
# |   store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndp.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i)
# |   store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2)
# |   store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x half>
# |   store <4 x half> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__ret.i3 = alloca <8 x half>, align 16
# |   %__p0.addr.i.i = alloca <4 x float>, align 16
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 16
# |   %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   %6 = fptrunc <4 x float> %5 to <4 x half>
# |   store <4 x half> %6, ptr %ref.tmp.i.i, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %7, ptr %__ret.i.i, align 8
# |   %8 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %2, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %8, ptr %__p1.addr.i2, align 8
# |   %9 = load <4 x half>, ptr %__p0.addr.i1, align 8
# |   %10 = load <4 x half>, ptr %__p1.addr.i2, align 8
# |   %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i3, align 16
# |   %11 = load <8 x half>, ptr %__ret.i3, align 16
# |   store <8 x half> %11, ptr %__ret.i, align 16
# |   %12 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fpext <4 x half> %2 to <4 x float>
# |   store <4 x float> %3, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__ret.i2 = alloca <4 x half>, align 8
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x half>, ptr %__ret.i2, align 8
# |   store <4 x half> %4, ptr %__p0.addr.i.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %7 = fpext <4 x half> %6 to <4 x float>
# |   store <4 x float> %7, ptr %ref.tmp.i.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %8, ptr %__ret.i.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i.i, align 16
# |   store <4 x float> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bc386b956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc386b6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc386b9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f458e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f458e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f458e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f458e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc3864f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc3864f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc38633f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc382e3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc382e2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f458e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f458e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f458e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc382e2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = l
# | ...
# `---data was truncated (10240/23247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634eee4156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005634eee3e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005634eee41cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6731f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6731f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6731f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6731eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634eedd723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634eedd7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005634eedbbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005634eea6b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005634eea6ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6731eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6731eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6731eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634eea6ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1
# | ...
# `---data was truncated (10240/154215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be1965056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be1964d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be19650cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03d9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03d955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03d9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03d94ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be195e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be195e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be195caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be1927a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be19279e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03d94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03d94ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03d94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be19279d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (148 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i)
# |   %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i)
# |   %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i)
# |   %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i)
# |   %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i)
# |   %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i)
# |   %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i)
# |   %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i)
# |   %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i)
# |   %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i)
# |   %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f64.i = bitcast <8 x i8> %1 
# | ...
# `---data was truncated (10240/18543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556ceebfb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ceebf8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ceebfbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f93b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f93b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f93b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f93aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ceeb9123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ceeb91086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ceeb75f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556cee825166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556cee824e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f93aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f93aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f93aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cee824d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (149 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.a
# | ...
# `---data was truncated (10240/28771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e4e36b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4e36b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4e36b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1510b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1510b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1510b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1510b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4e364e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4e364e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4e3632f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4e32e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4e32e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1510b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1510b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1510b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4e32e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f26ac2556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f26ac22505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f26ac25cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f6d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f6d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f6d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f6d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f26abbb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f26abbb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f26ab9ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f26a84f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f26a84ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f6d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f6d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f6d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f26a84ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback 
# | ...
# `---data was truncated (10240/15245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb599c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb599c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb599c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7479105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f747915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7479105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74790ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb5995c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb5995c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb59940f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb595f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb595efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f74790eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74790ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74790ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb595efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (152 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559a3fce356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a3fce0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a3fce3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03b3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03b378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03b3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03b371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a3fc7923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a3fc79086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a3fc5df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a3f90d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a3f90ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03b371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03b371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03b371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a3f90cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (153 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 
# | ...
# `---data was truncated (10240/13379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056208a0f256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056208a0ef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056208a0f2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0eb8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0eb8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0eb8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0eb8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056208a08823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056208a088086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056208a06cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562089d1c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562089d1be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0eb8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0eb8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0eb8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562089d1bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd8c16856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd8c165505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd8c168cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd77be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd77bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd77be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd77be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd8c0fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd8c0fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd8c0e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd8bd92166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd8bd91e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd77be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd77be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd77be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd8bd91d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572246fb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005572246f8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005572246fbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7218333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f721838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7218333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f721831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055722469123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557224691086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557224675f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557224325166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557224324e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f721831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f721831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f721831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557224324d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (156 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_s32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_s64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_u32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_u64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561b642e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561b642e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561b642e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc127b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc127b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc127b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc127b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b6427b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561b6427b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561b6425ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561b63f0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561b63f0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc127b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc127b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc127b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b63f0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (157 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.ad
# | ...
# `---data was truncated (10240/17434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d04b23f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d04b23c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d04b23fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91e5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91e5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91e5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91e5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d04b1d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d04b1d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d04b1b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d04ae69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d04ae68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f91e5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91e5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91e5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d04ae68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b785b1f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b785b1c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b785b1fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8785d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8785d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8785d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8785d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b785ab523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b785ab5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b785a99f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b785749166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b785748e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8785d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8785d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8785d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b785748d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bd135c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bd1359505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bd135ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f702c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f702c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f702c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f702c8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bd12f223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bd12f2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bd12d6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bd0f86166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bd0f85e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f702c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f702c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f702c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bd0f85d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (160 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 3)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 7)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a6df79156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a6df78e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a6df791cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1320533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f132058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1320533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f132051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6df72723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a6df727086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a6df70bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a6df3bb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a6df3bae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f132051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f132051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f132051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6df3bad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (161 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561014ce056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561014cdd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561014ce0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f885b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f885b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f885b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f885b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561014c7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561014c76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561014c5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056101490a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561014909e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f885b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f885b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f885b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561014909d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604a306556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005604a3062505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005604a3065cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64aee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64aeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64aee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64aee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604a2ffb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005604a2ffb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604a2fdff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005604a2c8f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005604a2c8ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f64aee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64aee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64aee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604a2c8ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (163 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %4, 0
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %4, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale
# | ...
# `---data was truncated (10240/25462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005636f630356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636f6300505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636f6303cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f08133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f0818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f08133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f0811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636f629923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005636f6299086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005636f627df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005636f5f2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005636f5f2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f0811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f0811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f0811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636f5f2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (164 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x2(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x2(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svscale_single_f64_x2(<vscale x 2 x double> %op1.coerce0, <vscale x 2 x double> %op1.coerce1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %op1.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x4(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x half> %op1.coerce2, <vscale x 8 x half> %op1.coerce3, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %op1.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x4(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x float> %op1.coerce2, <vscale x 4 x float> %op1.coerce3, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %op1.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr 
# | ...
# `---data was truncated (10240/37349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f9cef9f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9cef9c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9cef9fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7922133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f792218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7922133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f792211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9cef3523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f9cef35086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f9cef19f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f9cebc9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f9cebc8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f792211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f792211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f792211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9cebc8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7a8eb356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7a8eb0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7a8eb3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe873d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe873d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe873d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe873d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7a8e4923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7a8e49086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7a8e2df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7a8add166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7a8adce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe873d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe873d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe873d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7a8adcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (166 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005635e5fed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005635e5fea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005635e5fedcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae5da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae5daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae5da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae5da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635e5f8323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005635e5f83086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005635e5f67f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005635e5c17166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005635e5c16e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae5da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae5da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae5da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635e5c16d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (167 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svget2_f16(<vscale x 8 x half> %tuple.coerce0, <vscale x 8 x half> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %tuple.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svget2_f32(<vscale x 4 x float> %tuple.coerce0, <vscale x 4 x float> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %tuple.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | d
# | ...
# `---data was truncated (10240/14679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560bc2a9456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560bc2a91505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560bc2a94cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44ce133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44ce18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44ce133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44ce11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bc2a2a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560bc2a2a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560bc2a0ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560bc26be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560bc26bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f44ce11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44ce11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44ce11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bc26bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (168 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560f67cff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560f67cfc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560f67cffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29ecd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29ecd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29ecd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29ecd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f67c9523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560f67c95086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560f67c79f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560f67929166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560f67928e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f29ecd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29ecd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29ecd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f67928d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (169 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld4_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld4_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.fr
# | ...
# `---data was truncated (10240/27970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055691a44c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055691a449505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055691a44ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a2b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a2b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a2b8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055691a3e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055691a3e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055691a3c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055691a076166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055691a075e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a2b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a2b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a2b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055691a075d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (170 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eda0d9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eda0d99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eda0d9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9f2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9f2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9f2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9f2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eda0d3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eda0d32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eda0d16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eda09c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eda09c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc9f2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9f2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9f2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eda09c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056362be1956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056362be16505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056362be19cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f184f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f184f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f184f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f184f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056362bdaf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056362bdaf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056362bd93f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056362ba43166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056362ba42e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f184f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f184f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f184f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056362ba42d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (172 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559e4bd9656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e4bd93505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e4bd96cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82fbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82fbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82fbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82fbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e4bd2c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e4bd2c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e4bd10f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e4b9c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e4b9bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82fbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82fbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82fbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e4b9bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (173 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 16
# |   %__s0_827 = alloca <4 x i32>, align 16
# |   %__s1_827 = alloca <16 x i8>, align 16
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp2 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_827, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1_827, align 16
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 16
# |   %4 = load <16 x i8>, ptr %__s1_827, align 16
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__
# | ...
# `---data was truncated (10240/29862) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x0000560ebe84a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560ebe847505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560ebe84acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3df7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3df74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3df7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3df7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ebe7e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560ebe7e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560ebe7c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560ebe474166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560ebe473e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3df7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3df74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3df74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ebe473d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (174 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svclamp_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562a9a33756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a9a334505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a9a337cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad8da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad8daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad8da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad8da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a9a2cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a9a2cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a9a2b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a99f61166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a99f60e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fad8da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad8da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad8da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a99f60d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (175 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055968d8c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055968d8c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055968d8c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40cdc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40cdc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40cdc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40cdc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055968d85923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055968d859086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055968d83df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055968d4ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055968d4ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f40cdc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40cdc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40cdc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055968d4ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (176 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call
# | ...
# `---data was truncated (10240/48703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564db355956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564db3556505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564db3559cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1de8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1de88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1de8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1de8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564db34ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564db34ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564db34d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564db3183166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564db3182e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1de8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1de88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1de88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564db3182d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (177 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalt_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055803503856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558035035505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558035038cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe876133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe87618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe876133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe87611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558034fce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558034fce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558034fb2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558034c62166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558034c61e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe87611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe87611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe87611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558034c61d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (178 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate4_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1, <vscale x 16 x i1> %x2, <vscale x 16 x i1> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   %x2.addr = alloca <vscale x 16 x i1>, align 2
# |   %x4.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   store <vscale x 16 x i1> %x2, ptr %x2.addr, align 2
# |   store <vscale x 16 x i1> %x4, ptr %x4.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %x2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x4.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6, <vscale x 16 x i1> %3, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %7
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b49537856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b495375505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b495378cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62c2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62c28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62c2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62c2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b49530e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b49530e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b4952f2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b494fa2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b494fa1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62c2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62c28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62c28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b494fa1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (179 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005563a9d1d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563a9d1a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563a9d1dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa91b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa91b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa91b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa91b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563a9cb323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005563a9cb3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005563a9c97f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005563a9947166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005563a9946e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa91b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa91b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa91b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563a9946d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (180 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055efb470b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055efb4708505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055efb470bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5467649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5467649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5467631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efb46a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055efb46a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055efb4685f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055efb4335166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055efb4334e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5467632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efb4334d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (181 of 27911)
******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu  -target-cpu swift   -target-feature +fullfp16 -ffreestanding   -flax-vector-conversions=none   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7s-apple-darwin"
# | 
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p0.addr.i1, align 8
# |   store <8 x i8> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %8, ptr %__ret.i3, align 8
# |   %9 = load <8 x i8>, ptr %__ret.i3, align 8
# |   %add.i = add <8 x i8> %3, %9
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x i16>, align 8
# |   %__p1.addr.i2 = alloca <4 x i16>, align 8
# |   %__ret.i3 = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %5 = load <4 x i16>, ptr %__p2.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p0.addr.i1, align 8
# |   store <4 x i16> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16>
# |   %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %8, ptr %__ret.i3, align 8
# |   %9 = load <4 x i16>, ptr %__ret.i3, align 8
# |   %add.i = add <4 x i16> %3, %9
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %10 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <2 x i32>, align 8
# |   %__p1.addr.i2 = alloca <2 x i32>, align 8
# |   %__ret.i3 = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x i32>, ptr %__p2.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p0.addr.i1, align 8
# |   store <2 x i32> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32>
# |   %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %8, ptr %__ret.i3, align 8
# |   %9 = load <2 x i32>, ptr %__ret.i3, align 8
# |   %add.i = add <2 x i32> %3, %9
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %10 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, pt
# | ...
# `---data was truncated (10240/2159854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562cfd3bb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cfd3b8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cfd3bbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0fea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0feaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0fea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0fea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cfd35123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cfd351086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cfd335f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cfcfe5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cfcfe4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa0fea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0fea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0fea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cfcfe4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-neon-vst.c (182 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon      -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <4 x i16>
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x3_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0
# |   store [3 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %4 = bitcast <8 x i8> %1 to <4 x i16>
# |   %5 = bitcast <8 x i8> %2 to <4 x i16>
# |   %6 = bitcast <8 x i8> %3 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x4_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0
# |   store [4 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3
# |   %4 = load <8 x i8>, ptr %arrayidx6, align 8
# |   %5 = bitcast <8 x i8> %1 to <4 x i16>
# |   %6 = bitcast <8 x i8> %2 to <4 x i16>
# |   %7 = bitcast <8 x i8> %3 to <4 x i16>
# |   %8 = bitcast <8 x i8> %4 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float32x2x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <2 x float>
# |   %4 = bitcast <8 x i8> %2 to <2 x float>
# |   call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %s
# | ...
# `---data was truncated (10240/108866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bb05d2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bb05d27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bb05d2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc45533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc4558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc45533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc4551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb05cc023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bb05cc0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bb05ca4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bb05954166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bb05953e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc4551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc4551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc4551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb05953d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (183 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
# | ...
# `---data was truncated (10240/37760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055981de1156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055981de0e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055981de11cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff78b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff78b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff78b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff78b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055981dda723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055981dda7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055981dd8bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055981da3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055981da3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff78b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff78b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff78b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055981da3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (184 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ccea89156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccea88e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccea891cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b31333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b3138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b31333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b3131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccea82723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccea827086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccea80bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ccea4bb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ccea4bae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b3131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b3131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b3131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccea4bad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (185 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005582a1f7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005582a1f72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005582a1f75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f965e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f965e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f965e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f965e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582a1f0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582a1f0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582a1eeff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582a1b9f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582a1b9ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f965e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f965e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f965e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582a1b9ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (186 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtsmul_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtsmul_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtsmul_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005606b1ca856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606b1ca5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606b1ca8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f722ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f722cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f722ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f722ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606b1c3e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606b1c3e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606b1c22f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606b18d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606b18d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f722ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f722ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f722ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606b18d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (187 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvtn_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvtn_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_loc
# | ...
# `---data was truncated (10240/17734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e94457c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e944579505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e94457ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac1ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac1ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac1ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac1ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e94451223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e944512086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9444f6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e9441a6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e9441a5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac1ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac1ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac1ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9441a5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (188 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   call void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 2
# |   %9 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 0
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 1
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 2
# |   %9 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, <vscale x 2 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = al
# | ...
# `---data was truncated (10240/58378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556bfc6cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556bfc6c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556bfc6cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f086e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f086e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f086e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f086e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bfc66123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556bfc661086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556bfc645f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556bfc2f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556bfc2f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f086e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f086e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f086e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bfc2f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon/add.c (189 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %add.i = add <16 x i8> %2, %3
# |   store <16 x i8> %add.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %add.i = add <8 x i16> %2, %3
# |   store <8 x i16> %add.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b
# | ...
# `---data was truncated (10240/221881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055bd305c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bd305bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bd305c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc98a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc98aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc98a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc98a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd3055823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bd30558086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bd3053cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bd301ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bd301ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc98a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc98a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc98a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd301ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vsca
# | ...
# `---data was truncated (10240/14360) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c0a6ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c0a6fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c0a6ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f057cd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f057cd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f057cd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f057cced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c0a69523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c0a695086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c0a679f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c0a329166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c0a328e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f057cceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f057ccef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f057ccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c0a328d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (191 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# | 
# | ...
# `---data was truncated (10240/31781) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d564af056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d564aed505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d564af0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a22649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a226a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a22649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a22631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d564a8623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d564a86086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d564a6af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d56471a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d564719e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a22632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a226330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a226330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d564719d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (192 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | 
# | ...
# `---data was truncated (10240/178306) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556f3c85356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f3c850505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f3c853cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faecd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faecd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faecd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faecd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f3c7e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f3c7e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f3c7cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f3c47d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f3c47ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faecd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faecd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faecd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f3c47cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (193 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <
# | ...
# `---data was truncated (10240/50499) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cf1070156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf106fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf10701cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f080cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f080cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f080cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f080cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf1069723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf10697086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf1067bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf1032b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf1032ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f080cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f080cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f080cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf1032ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (194 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a4a914556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a4a9142505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a4a9145cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1904b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1904b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1904b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1904b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4a90db23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a4a90db086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a4a90bff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a4a8d6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a4a8d6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1904b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1904b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1904b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4a8d6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (195 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005594bbeae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005594bbeab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005594bbeaecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb467933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb46798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb467933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb46791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594bbe4423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594bbe44086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005594bbe28f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005594bbad8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005594bbad7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb46791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb46791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb46791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594bbad7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (196 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ab17f1556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab17f12505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab17f15cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa66c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa66ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa66c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa66c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab17eab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab17eab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab17e8ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab17b3f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab17b3ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa66c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa66c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa66c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab17b3ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584f4c2256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005584f4c1f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005584f4c22cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e52533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e5258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e52533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e5251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584f4bb823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005584f4bb8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005584f4b9cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005584f484c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005584f484be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e5251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e5251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e5251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584f484bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (198 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e2a09ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2a09cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2a09cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ceb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ceb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ceb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ceb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2a096423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2a0964086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2a0948f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2a05f8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2a05f7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ceb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ceb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ceb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2a05f7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (199 of 27911)
******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13)
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundlit
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638ed00556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638ed002505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638ed005cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf93733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf9378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf93733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf9371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638ecf9b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638ecf9b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638ecf7ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638ecc2f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638ecc2ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdf9371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf9371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf9371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638ecc2ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (200 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056289750156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005628974fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562897501cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbbcb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbbcb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbbcb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbbcaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056289749723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562897497086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056289747bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056289712b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056289712ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcbbcaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbbcaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbbcaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056289712ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (201 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005573cc7d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005573cc7d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005573cc7d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa25bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa25bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa25bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa25bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573cc76a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005573cc76a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005573cc74ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005573cc3fe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005573cc3fde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa25bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa25bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa25bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573cc3fdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (202 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_72 = alloca <4 x i16>, align 8
# |   %__s0_72 = alloca <4 x i16>, align 8
# |   %__s1_72 = alloca <4 x i16>, align 8
# |   %__s2_72 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_72, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_72, align 8
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_72, align 8
# |   %3 = load <4 x i16>, ptr %__s0_72, align 8
# |   %4 = load <4 x i16>, ptr %__s1_72, align 8
# |   %5 = load <4 x i16>, ptr %__s2_72, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_72, align 8
# |   %11 = load <4 x i16>, ptr %__ret_72, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_62 = alloca <8 x i16>, align 16
# |   %__s0_62 = alloca <8 x i16>, align 16
# |   %__s1_62 = alloca <8 x i16>, align 16
# |   %__s2_62 = alloca <4 x i16>, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_62, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_62, align 16
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_62, align 8
# |   %3 = load <8 x i16>, ptr %__s0_62, align 16
# |   %4 = load <8 x i16>, ptr %__s1_62, align 16
# |   %5 = load <4 x i16>, ptr %__s2_62, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   %mul = mul <8 x i16> %4, %10
# |   %add = add <8 x i16> %3, %mul
# |   store <8 x i16> %add, ptr %__ret_62, align 16
# |   %11 = load <8 x i16>, ptr %__ret_62, align 16
# |   store <8 x i16> %11, ptr %tmp1, align 16
# |   %12 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_70 = alloca <2 x i32>, align 8
# |   %__s0_70 = alloca <2 x i32>, align 8
# |   %__s1_70 = alloca <2 x i32>, align 8
# |   %__s2_70 = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_70, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_70, align 8
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_70, align 8
# |   %3 = load <2 x i32>, ptr %__s0_70, align 8
# |   %4 = load <2 x i32>, ptr %__s1_70, align 8
# |   %5 = load <2 x i32>, ptr %__s2_70, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   %mul = mul <2 x i32> %4, %10
# |   %add = add <2 x i32> %3, %mul
# |   store <2 x i32> %add, ptr %__ret_70, align 8
# |   %11 = load <2 x i32>, ptr %__ret_70, align 8
# |   store <2 x i32> %11, ptr %tmp1, align 8
# |   %12 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_60 = alloca <4 x i32>, align 16
# |   %__s0_60 = alloca <4 x i32>, align 16
# |   %__s1_60 = alloca <4 x i32>, align 16
# |   %__s2_60 = alloca <2 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_60, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1_60, align 16
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_60, align 8
# |   %3 = load <4 x i32>, ptr %__s0_60, align 16
# |   %4 = load <4 x i32>, ptr %__s1_60, align 16
# |   %5 = load <2 x i32>, ptr %__s2_60, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x i32> %lane, ptr %ref.tmp, align 16
# |   %8 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %8, ptr %__ret, align 16
# |   %9 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %9, ptr %tmp, align 16
# |   %10 = load <4 x i32>, ptr %tmp, align 16
# |   %mul = mul <4 x i32> %4, %10
# |   %add = add <4 x i32> %3, %mul
# |   store <4 x i32> %add, ptr %__ret_60, align 16
# |   %11 = load <4 x i32>, ptr %__ret_60, align 16
# |   store <4 x i32> %11, ptr %tmp1, align 16
# |   %12 = load <4 x i32>, ptr %tmp1, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_482 = alloca <4 x i16>, align 8
# |   %__s0_482 = alloca <4 x i16>, align 8
# |   %__s1_482 = alloca <4 x i16>, align 8
# |   %__s2_482 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_482, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_482, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_482, align 16
# |   %3 = load <4 x i16>, ptr %__s0_482, align 8
# |   %4 = load <4 x i16>, ptr %__s1_482, align 8
# |   %5 = load <8 x i16>, ptr %__s2_482, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_482, align 8
# |   %11 = load <4 x i16>, ptr %__ret_482, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_472 = alloca <8 x i16>, align 16
# |   %__s0_472 = alloca <8 x i16>, align 16
# |   %__s1_472 = alloca <8
# | ...
# `---data was truncated (10240/857511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562f9cb7456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f9cb71505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f9cb74cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bffd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bffd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bffd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bffd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f9cb0a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f9cb0a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f9caeef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f9c79e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f9c79de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3bffd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bffd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bffd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f9c79dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (203 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c1ee58256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1ee57f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1ee582cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f50f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f50f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f50f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f50f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1ee51823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1ee518086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1ee4fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1ee1ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1ee1abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f50f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f50f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f50f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1ee1abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (204 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_s16_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, i32 16)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/33461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005639d323e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639d323b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639d323ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d5f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d5f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d5f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d5f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639d31d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639d31d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639d31b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639d2e68166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639d2e67e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d5f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d5f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d5f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639d2e67d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562765a2556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562765a22505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562765a25cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2f2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2f28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2f2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2f2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627659bb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627659bb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056276599ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056276564f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056276564ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2f2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2f28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2f28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056276564ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve/dup.c (206 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_u8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_u16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_n_f16(half noundef %op) #0 {
# | entry:
# |   %op.addr = alloca half, align 2
# |   store half %op, ptr %op.addr, align 2
# |   %0 = load half, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_n_f32(float noundef %op) #0 {
# | entry:
# |   %op.addr = alloca float, align 4
# |   store float %op, ptr %op.addr, align 4
# |   %0 = load float, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_n_f64(double noundef %op) #0 {
# | entry:
# |   %op.addr = alloca double, align 8
# |   store double %op, ptr %op.addr, align 8
# |   %0 = load double, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b8(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 16 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 16 x i1> %.splatinsert, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
# |   ret <vscale x 16 x i1> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b16(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 8 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 8 x i1> %.splatinsert, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b32(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 4 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 4 x i1> %.splatinsert, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b64(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 2 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 2 x i1> %.splatinsert, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_n_bf16(bfloat noundef %op) #0 {
# | entry:
# |   %op.addr = alloca bfloat, align 2
# |   store bfloat %op, ptr %op.addr, align 2
# |   %0 = load bfloat, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8_z(<vscale x 16 x i1> %pg, i8 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i8, align 1
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i8, ptr %op.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16_z(<vscale x 16 x i1> %pg, i16 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i16, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vsca
# | ...
# `---data was truncated (10240/49557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x0000556cd5bf056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556cd5bed505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556cd5bf0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ddd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ddd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ddd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ddd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cd5b8623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556cd5b86086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556cd5b6af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556cd581a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556cd5819e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ddd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ddd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ddd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cd5819d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (207 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_1() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 1)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_2() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 2)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_3() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 3)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_4() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 4)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_5() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 5)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_6() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 6)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_7() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 7)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 8)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_9() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 9)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_10() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_11() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_12() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 12)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_13() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 13)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_14() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 29)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_15() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 30)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_16() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 1)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 2)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055de806bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de806b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de806bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2edb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2edb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2edb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2edb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de8065223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de80652086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de80636f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de802e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de802e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc2edb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2edb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2edb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de802e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (208 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_u8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_s8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ab1702256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab1701f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab17022cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c49333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c4938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c49333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c4931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab16fb823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab16fb8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab16f9cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab16c4c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab16c4be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8c4931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c4931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c4931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab16c4bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (209 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svqdmulh_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svqdmulh_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x4(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zdn.coerce2, <vscale x 16 x i8> %zdn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zdn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x4(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zdn.coerce2, <vscale x 8
# | ...
# `---data was truncated (10240/47111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056531497e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056531497b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056531497ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff7ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff7ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff7ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff7aaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056531491423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565314914086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005653148f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653145a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653145a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff7aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff7aaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff7aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653145a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (210 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d7f239f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d7f239c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d7f239fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9229e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9229ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9229e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9229e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7f233523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7f2335086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d7f2319f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d7f1fc9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d7f1fc8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9229e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9229e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9229e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7f1fc8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (211 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintam_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintm_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintn_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn me
# | ...
# `---data was truncated (10240/17932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055573110c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555731109505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055573110ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f840a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f840a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f840a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f840a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557310a223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005557310a2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555731086f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555730d36166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555730d35e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f840a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f840a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f840a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555730d35d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willre
# | ...
# `---data was truncated (10240/273697) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056372e25d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056372e25a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056372e25dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0bee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0beea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0bee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0bee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056372e1f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056372e1f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056372e1d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056372de87166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056372de86e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa0bee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0bee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0bee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056372de86d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab7071856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab70715505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab70718cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4863333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f486338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4863333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f486331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab706ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab706ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab70692f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab70342166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab70341e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f486331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f486331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f486331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab70341d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c360ad556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c360ad2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c360ad5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80d9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80d96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80d9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80d9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c360a6b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c360a6b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c360a4ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c3606ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c3606fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80d9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80d96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80d96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3606fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (215 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ad8661d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad8661a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad8661dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2bb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2bb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2bb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2bb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad865b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad865b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad86597f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad86247166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad86246e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff2bb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2bb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2bb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad86246d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (216 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmin_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmin_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005633dfb7e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633dfb7b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633dfb7ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4789533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f478958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4789533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f478951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633dfb1423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005633dfb14086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005633dfaf8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005633df7a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005633df7a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f478951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f478951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f478951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633df7a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (217 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 8 x half
# | ...
# `---data was truncated (10240/88476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005559c199256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559c198f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559c1992cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fc7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fc778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fc7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fc771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559c192823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559c1928086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559c190cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559c15bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559c15bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7fc771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fc771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fc771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559c15bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (218 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnf1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnf1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnf1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/22483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e03ade556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e03ade2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e03ade5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe069c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe069c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe069c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe069c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e03ad7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e03ad7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e03ad5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e03aa0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e03aa0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe069c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe069c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe069c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e03aa0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (219 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 3
# |   %14 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 3
# |   call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, <vscale x 8 x i16> %10, <vscale x 8 x i16> %11, <vscale x 8 x i16> %12, <vscale x 8 x i16> %13, <vscale x 8 x i16> %15, <vscale x 8 x i16> %16, <vscale x 8 x i16> %17, <vscale x 8 x i16> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, <vscale x 16 x i8> %zm.coerce2, <vscale x 16 x i8> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align
# | ...
# `---data was truncated (10240/127452) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c46942756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c469424505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c469427cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8690305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f869035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8690305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86902ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4693bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c4693bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c4693a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c469051166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c469050e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f86902eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86902ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86902ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c469050d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (220 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005586a8e4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005586a8e43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005586a8e46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f955ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f955ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f955ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f955ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586a8ddc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005586a8ddc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005586a8dc0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586a8a70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586a8a6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f955ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f955ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f955ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586a8a6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (221 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560604b5456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560604b51505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560604b54cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff94dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff94dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff94dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff94dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560604aea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560604aea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560604acef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056060477e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056060477de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff94dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff94dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff94dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056060477dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (222 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005642d704856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005642d7045505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005642d7048cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c57249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c572a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c57249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c57231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642d6fde23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005642d6fde086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005642d6fc2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005642d6c72166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005642d6c71e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c57232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c572330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c572330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642d6c71d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (223 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055dd725bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dd725b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dd725bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0380049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03800a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0380049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0380031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd7255223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dd72552086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dd72536f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dd721e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dd721e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0380032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03800330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03800330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd721e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (224 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559e54d8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e54d87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e54d8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa86c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa86c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa86c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa86c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e54d2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e54d20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e54d04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e549b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e549b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa86c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa86c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa86c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e549b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (225 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1)
# |   store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1)
# |   store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca double, align 8
# |   %ref.tmp.i = alloca double, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1)
# |   store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8
# |   %2 = load double, ptr %ref.tmp.i, align 8
# |   store double %2, ptr %__ret.i, align 8
# |   %3 = load double, ptr %__ret.i, align 8
# |   ret double %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16>
# |   %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3)
# |   store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32>
# |   %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9)
# |   store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %2, ptr %__ret, align 8
# |   %3 = load <4 x i16>, p
# | ...
# `---data was truncated (10240/770739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005559ff88b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559ff888505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559ff88bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c8f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c8f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c8f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c8f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559ff82123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559ff821086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559ff805f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559ff4b5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559ff4b4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2c8f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c8f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c8f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559ff4b4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (226 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x
# | ...
# `---data was truncated (10240/66009) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056027df4556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056027df42505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056027df45cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cf2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cf2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cf2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cf2e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056027dedb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056027dedb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056027debff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056027db6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056027db6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0cf2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cf2e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cf2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056027db6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (227 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ee5fce156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee5fcde505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee5fce1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37fa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37fa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37fa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37fa403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee5fc7723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee5fc77086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee5fc5bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee5f90b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee5f90ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f37fa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37fa4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37fa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee5f90ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (228 of 27911)
******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @_Z9cond_boolu10__SVBool_tS_(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ult <vscale x 16 x i1> %0, %1
# |   %2 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %vector_select = select <vscale x 16 x i1> %cmp, <vscale x 16 x i1> %2, <vscale x 16 x i1> %3
# |   ret <vscale x 16 x i1> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_i8u10__SVInt8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_u8u11__SVUint8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_i16u11__SVInt16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_u16u12__SVUint16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_i32u11__SVInt32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_u32u12__SVUint32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_i64u11__SVInt64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_u64u12__SVUint64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @_Z8cond_f16u13__SVFloat16_tS_(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x half> %2, <vscale x 8 x half> %3
# |   ret <vscale x 8 x half> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @_Z8cond_f32u13__SVFloat32_tS_(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %3 = load <vs
# | ...
# `---data was truncated (10240/16444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055c54a4bb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c54a4b8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c54a4bbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b6d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b6d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b6d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b6d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c54a45123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c54a451086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c54a435f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c54a0e5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c54a0e4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7b6d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b6d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b6d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c54a0e4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (229 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcompact_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcompact_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f15b35a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f15b357505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f15b35acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6813b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6813b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6813b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6813aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f15b2f023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f15b2f0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f15b2d4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f15af84166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f15af83e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6813aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6813aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6813aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f15af83d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569cd63a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005569cd637505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005569cd63acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05cb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05cb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05cb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05cb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569cd5d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005569cd5d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005569cd5b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005569cd264166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005569cd263e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f05cb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05cb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05cb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569cd263d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (231 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svzip_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svzip_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svzip_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005561cd02156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561cd01e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561cd021cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f364b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f364b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f364b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f364b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561ccfb723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561ccfb7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561ccf9bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005561ccc4b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005561ccc4ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f364b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f364b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f364b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561ccc4ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (232 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056373fa7e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056373fa7b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056373fa7ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9da21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9da2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9da21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9da203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056373fa1423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056373fa14086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056373f9f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056373f6a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056373f6a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe9da204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9da2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9da2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056373f6a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (233 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/33353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056539981c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565399819505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056539981ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed2c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed2c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed2c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed2c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653997b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005653997b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565399796f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565399446166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565399445e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fed2c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed2c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed2c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565399445d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (234 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ba111f256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba111ef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba111f2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44e9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44e98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44e9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44e9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba1118823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba11188086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba1116cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba10e1c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba10e1be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f44e9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44e98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44e98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba10e1bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (235 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16_1(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtmad_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtmad_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef11c9b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ef11c98505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ef11c9bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56ca049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56ca0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56ca049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56ca031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef11c3123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ef11c31086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ef11c15f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ef118c5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ef118c4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f56ca032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56ca0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56ca0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef118c4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (236 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005638507b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638507b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638507b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dbac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dbaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dbac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dbac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056385074e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056385074e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563850732f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638503e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638503e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3dbac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dbac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dbac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638503e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (237 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za16_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za32_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e746b0d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e746b0a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e746b0dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f027e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f027e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f027e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f027e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e746aa323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e746aa3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e746a87f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e746737166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e746736e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f027e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f027e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f027e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e746736d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (238 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 8)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 1)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 16)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 1)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z_1(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 32)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 1)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z_1(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 64)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i32 1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, 
# | ...
# `---data was truncated (10240/14353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eac8dc156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eac8dbe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eac8dc1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92cbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92cbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92cbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92cbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eac8d5723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eac8d57086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eac8d3bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eac89eb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eac89eae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f92cbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92cbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92cbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eac89ead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (239 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_u32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c1de63456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1de631505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1de634cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f4dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f4dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f4dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f4dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1de5ca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1de5ca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1de5aef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1de25e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1de25de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f4dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f4dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f4dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1de25dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (240 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055912ddb356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055912ddb0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055912ddb3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f508ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f508ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f508ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f508ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055912dd4923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055912dd49086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055912dd2df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055912d9dd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055912d9dce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f508ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f508ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f508ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055912d9dcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (241 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 3
# |   %14 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 3
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, <vscale x 8 x half> %10, <vscale x 8 x half> %11, <vscale x 8 x half> %12, <vscale x 8 x half> %13, <vscale x 8 x half> %15, <vscale x 8 x half> %16, <vscale x 8 x half> %17, <vscale x 8 x half> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/34400) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f3c706456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f3c7061505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f3c7064cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadf4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadf46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadf4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadf4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3c6ffa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f3c6ffa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f3c6fdef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f3c6c8e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f3c6c8de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fadf4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadf46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadf46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3c6c8dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (242 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @subscript_float16(<vscale x 8 x half> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @subscript_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @subscript_float64(<vscale x 2 x double> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %1, float 1.000000e+00, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_read_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecext = extractelement <vscale x 4 x float> %1, i64 %0
# |   %add = fadd float %vecext, 1.000000e+00
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %2, float %add, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005571c50e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005571c50e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005571c50e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f418621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41862725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f418621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4186203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571c507a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571c507a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571c505ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571c4d0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571c4d0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4186204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41862050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41862050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571c4d0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (243 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_s64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 7)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_u8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_s8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056085eb4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056085eb43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056085eb46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33e2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33e298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33e2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33e291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056085eadc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056085eadc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056085eac0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056085e770166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056085e76fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f33e291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33e291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33e291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056085e76fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (244 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 270)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.ad
# | ...
# `---data was truncated (10240/12234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005633843d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633843d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633843d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc882f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc882f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc882f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc882f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056338436d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056338436d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563384351f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563384001166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563384000e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc882f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc882f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc882f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563384000d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (245 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055643447956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556434476505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556434479cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa98705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa9875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa98705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa986ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055643440f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055643440f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005564343f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005564340a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005564340a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa986eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa986ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa986ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564340a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/minv.c (246 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055ccedc3056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccedc2d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccedc30cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae1a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae1a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae1a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae1a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccedbc623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccedbc6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccedbaaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cced85a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cced859e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae1a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae1a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae1a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cced859d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (247 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld3_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld3_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svld3_f64(<vscale x
# | ...
# `---data was truncated (10240/26187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562c7234e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c7234b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c7234ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f793d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f793d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f793d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f793d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c722e423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c722e4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c722c8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c71f78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c71f77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f793d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f793d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f793d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c71f77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (248 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b80179e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b80179b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b80179ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb97b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb97b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb97b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb97b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b80173423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b801734086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b801718f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b8013c8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b8013c7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb97b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb97b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb97b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8013c7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (249 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmax_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmax_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b7902fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b7902fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b7902fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0281049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02810a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0281049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0281031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b79029423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b790294086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b790278f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b78ff28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b78ff27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0281032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02810330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02810330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b78ff27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (250 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d7b8f5b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d7b8f58505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d7b8f5bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a24533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a24533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a2451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7b8ef123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7b8ef1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d7b8ed5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d7b8b85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d7b8b84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a2451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a2451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a2451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7b8b84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (251 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005617cf4fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005617cf4f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005617cf4facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fabb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fabb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fabb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fabb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617cf49023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005617cf490086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005617cf474f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005617cf124166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005617cf123e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5fabb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fabb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fabb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617cf123d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621544e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005621544e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005621544e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3244733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f324478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3244733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f324471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056215447c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056215447c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562154460f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562154110166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056215410fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f324471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f324471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f324471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056215410fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (253 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svsel_s16_x2(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   %11 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale 
# | ...
# `---data was truncated (10240/33971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005570c8d5e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005570c8d5b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005570c8d5ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f868ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f868ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f868ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f868ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570c8cf423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570c8cf4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570c8cd8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570c8988166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570c8987e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f868ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f868ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f868ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570c8987d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (254 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmla_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d5c74d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d5c74d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d5c74d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c7f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c7f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c7f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c7f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5c746d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d5c746d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d5c7451f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d5c7101166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d5c7100e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c7f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c7f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c7f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5c7100d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (255 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a12a64256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a12a63f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a12a642cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d46a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d46aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d46a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d46a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a12a5d823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a12a5d8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a12a5bcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a12a26c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a12a26be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d46a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d46a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d46a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a12a26bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (256 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8_1(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 0)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16_1(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 0)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32_1(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64_1(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svext_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 127)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svext_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr 
# | ...
# `---data was truncated (10240/12880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005573bf65556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005573bf652505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005573bf655cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8aede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8aedea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8aede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8aede31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573bf5eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005573bf5eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005573bf5cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005573bf27f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005573bf27ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8aede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8aede330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8aede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573bf27ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (257 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055faa953b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055faa9538505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055faa953bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9141449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91414a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9141449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9141431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faa94d123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055faa94d1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055faa94b5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055faa9165166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055faa9164e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9141432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91414330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91414330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faa9164d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589ba79e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589ba79b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589ba79ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc27c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc27ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc27c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc27c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589ba73423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589ba734086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589ba718f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589ba3c8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589ba3c7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc27c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc27c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc27c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589ba3c7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (259 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %shl = shl <16 x i32> %0, %1
# |   store <16 x i32> %shl, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 imma
# | ...
# `---data was truncated (10240/51475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055cd0fc7e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd0fc7b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd0fc7ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d57d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d57d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d57d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d57ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd0fc1423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd0fc14086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd0fbf8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd0f8a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd0f8a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d57ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d57cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d57cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd0f8a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>
# | ...
# `---data was truncated (10240/153805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f22807c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f228079505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f22807ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e55649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e55649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e55631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f22801223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f228012086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f227ff6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f227ca6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f227ca5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3e55632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e556330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f227ca5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (261 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056034ea4856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056034ea45505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056034ea48cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc43c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc43c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc43c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc43c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056034e9de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056034e9de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056034e9c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056034e672166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056034e671e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc43c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc43c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc43c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056034e671d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (262 of 27911)
******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> <i32 3, i32 2, i32 8, i32 11, i32 7, i32 6, i32 12, i32 15>
# |   ret <8 x float> %shufp
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> <i32 1, i32 0>
# |   ret <2 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 1, i32 2, i32 3>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <4 x double> %b, ptr %b.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <4 x double>, ptr %b.addr, align 32
# |   %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
# |   ret <4 x double> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
# |   ret <8 x float> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <4 x i64>, align 32
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <4 x i64> %b, ptr %b.addr, align 32
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <4 x i64>, ptr %b.addr, align 32
# |   %3 = bitcast <4 x i64> %2 to <8 x i32>
# |   %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
# |   %4 = bitcast <8 x i32> %vperm to <4 x i64>
# |   ret <4 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3
# |   store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__d.i = alloca double, align 8
# |   %.compoundliteral.i = alloca <4 x double>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load double, ptr %1, align 1
# |   store double %2, ptr %__d.i, align 8
# |   %3 = load double, ptr %__d.i, align 8
# |   %vecinit.i = insertelement <4 x double> poison, double %3, i32 0
# |   %4 = load double, ptr %__d.i, align 8
# |   %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1
# |   %5 = load double, ptr %__d.i, align 8
# |   %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2
# |   %6 = load double, ptr %__d.i, align 8
# |   %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3
# |   store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32
# |   %7 = load <4 x double>, ptr %.compoundliteral.i, align 32
# |   ret <4 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <8 x float>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <8 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3
# |   %7 = load float, ptr %__f.i, align 4
# |   %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4
# |   %8 = load float, ptr %__f.i, align 4
# |   %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5
# |   %9 = load float, ptr %__f.i, align 4
# |   %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6
# |   %10 = load float, ptr %__f.i, align 4
# |   %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7
# |   store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32
# |   %11 = load <8 x float>, ptr %.compoundliteral.i, align 32
# |   ret <8 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <4 x float>, align 16
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
# |   ret <8 x float> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <2 x double>, align 16
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
# |   ret <4 x double> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <2 x i64>, ptr
# | ...
# `---data was truncated (10240/21933) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d8ae6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556d8ae6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556d8ae6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49bbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49bbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49bbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49bbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d8ae0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556d8ae03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556d8ade7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556d8aa97166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556d8aa96e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f49bbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49bbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49bbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d8aa96d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (263 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c0653fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0653f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0653fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5aecd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5aecd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5aecd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5aecd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c06539223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c065392086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c065376f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c065026166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c065025e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5aecd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5aecd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5aecd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c065025d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/widen.c (264 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = sext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = sext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = sext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = zext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = zext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = zext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i1 = alloca <8 x i8>, align 8
# |   %__p0_561.addr.i = alloca <16 x i8>, align 16
# |   %__ret_561.i = alloca <8 x i16>, align 16
# |   %__a1_561.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %__s0.i = alloca <8 x i8>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0_561.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i1, align 8
# |   store <8 x i8> %4, ptr %__a1_561.i, align 8
# |   %5 = load <8 x i8>, ptr %__a1_561.i, align 8
# |   store <8 x i8> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = sext <8 x i8> %6 to <8 x i16>
# |   store <8 x i16> %7, ptr %ref.tmp1.i, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16
# |   store <8 x i16> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %9, ptr %tmp.i, align 16
# |   %10 = load <8 x i16>, ptr %tmp.i, align 16
# |   store <8 x i16> %10, ptr %ref.tmp.i, align 16
# |   %11 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %11, ptr %__ret_561.i, align 16
# |   %12 = load <8 x i16>, ptr %__ret_561.i, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i1 = alloca <4 x i16>, align 8
# |   %__p0_567.addr.i = alloca <8 x i16>, align 16
# |   %__ret_567.i = alloca <4 x i32>, align 16
# |   %__a1_567.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0_567.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i1, align 8
# |   store <4 x i16> %4, ptr %__a1_567.i, align 8
# |   %5 = load <4 x i16>, ptr %__a1_567.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = sext <4 x i16> %7 to <4 x i32>
# |   store <4 x i32> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %12, ptr %__ret_567.i, align 16
# |   %13 = load <4 x i32>, ptr %__ret_567.i, align 16
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i1 = alloca <2 x i32>, align 8
# |   %__p0_564.addr.i = alloca <4 x i32>, align 16
# |   %__ret_564.i = alloca <2 x i64>, align 16
# |   %__a1_564.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %__s0.i = alloca <2 x i32>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0_564.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i1, align 8
# |   store <2 x i32> %4, ptr %__a1_564.i, align 8
# |   %5 = load <2 x i32>, ptr %__a1_564.i, align 8
# |   store <2 x i32> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %8 = sext <2 x i32> %7 to <2 x i64>
# |   store <2 x i64> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16
# |   store <2 x i64> %9, ptr %__ret.i, align 16
# |   %10 = load <2 x i64>, ptr %__ret.i, align 16
# |   store <2 x i64> %10, ptr %tmp.i, align 16
# |   %11 = load <2 x i64>, ptr %tmp.i, align 16
# |   store <2 x i64> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <2 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b6f451e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6f451b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6f451ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0bba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0bbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0bba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0bba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6f44b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6f44b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6f4498f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6f4148166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6f4147e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0bba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0bba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0bba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6f4147d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c535f556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c535f2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c535f5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc47c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc47c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc47c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc47c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c5358b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c5358b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c5356ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c5321f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c5321ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc47c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc47c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc47c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c5321ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (266 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i64>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005603dec7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603dec74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603dec77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe79849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe798a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe79849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe79831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603dec0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005603dec0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005603debf1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005603de8a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005603de8a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbe79832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe798330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe798330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603de8a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (267 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055afeba3256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055afeba2f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055afeba32cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bf001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bf00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bf001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bf0003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afeb9c823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055afeb9c8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055afeb9acf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055afeb65c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055afeb65be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3bf0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bf00050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bf00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afeb65bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (268 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsetffr() #0 {
# | entry:
# |   call void @llvm.aarch64.sve.setffr()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.setffr() #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558f4ed8856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f4ed85505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f4ed88cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5156b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5156b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5156b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5156aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f4ed1e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f4ed1e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f4ed02f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f4e9b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f4e9b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5156aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5156aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5156aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f4e9b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/orn.c (269 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svorn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005626912fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005626912fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005626912fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11e1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11e195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11e1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11e18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056269129423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562691294086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562691278f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562690f28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562690f27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f11e18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11e18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11e18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562690f27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (270 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 1
# | ...
# `---data was truncated (10240/48782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055edc975d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055edc975a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055edc975dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4329b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4329b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4329b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4329aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edc96f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055edc96f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055edc96d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055edc9387166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055edc9386e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4329aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4329aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4329aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edc9386d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (271 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_u8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_u16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_u32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_s64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_u64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svreinterpret_f16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svreinterpret_bf16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svreinterpret_f32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x float>
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svreinterpret_f64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 t
# | ...
# `---data was truncated (10240/168193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x000055dffba2656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dffba23505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dffba26cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97c7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97c7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97c7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97c7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dffb9bc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dffb9bc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dffb9a0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dffb650166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dffb64fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f97c7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97c7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97c7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dffb64fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (272 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_f16_f16(
# | ...
# `---data was truncated (10240/27272) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f35604b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f356048505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f35604bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b26933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b2698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b26933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b2691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f355fe123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f355fe1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f355fc5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f355c75166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f355c74e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1b2691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b2691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b2691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f355c74d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (273 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %9 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 0
# |   %11 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 1
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 2
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 3
# |   %14 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 0
# |   %16 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 1
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 2
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 3
# |   %19 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, <vscale x 16 x i8> %10, <vscale x 16 x i8> %11, <vscale x 16 x i8> %12, <vscale x 16 x i8> %13, <vscale x 16 x i8> %15, <vscale x 16 x i8> %16, <vscale x 16 x i8> %17, <vscale x 16 x i8> %18)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %19
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn3.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn4.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %8 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %9 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %8, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   %zn3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %0, align 16
# |   %zn4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %1, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn3, ptr %zn3.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn4, ptr %zn4.addr, align 16
# |   %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 0
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 1
# |   %14 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 2
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 3
# |   %16 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 0
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 1
# |   %19 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 2
# |   %20 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 3
# |   %21 = call { <vscale x 16 x i8>, <vscale x 16 
# | ...
# `---data was truncated (10240/73319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000055952493756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559524934505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559524937cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb302649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3026a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb302649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb302631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595248cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005595248cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005595248b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559524561166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559524560e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb302632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3026330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3026330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559524560d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (274 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_1(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 =
# | ...
# `---data was truncated (10240/15126) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fbd24e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fbd24e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fbd24e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fcb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fcb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fcb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fcb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbd247c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fbd247c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fbd2460f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fbd2110166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fbd210fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1fcb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fcb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fcb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbd210fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (275 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562bd071956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bd0716505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bd0719cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eb2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eb2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eb2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eb2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bd06af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bd06af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bd0693f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bd0343166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bd0342e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2eb2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eb2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eb2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bd0342d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (276 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 {
# | entry:
# |   ret target("aarch64.svcount") zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005567e3d9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005567e3d8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005567e3d90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9078049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90780a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9078049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9078031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567e3d2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005567e3d26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005567e3d0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005567e39ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005567e39b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9078032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90780330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90780330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567e39b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.a
# | ...
# `---data was truncated (10240/174713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c97728b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c977288505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c97728bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb10c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb10c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb10c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb10c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c97722123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c977221086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c977205f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c976eb5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c976eb4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb10c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb10c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb10c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c976eb4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597b72a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005597b72a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005597b72a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c69905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c6995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c69905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c698ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597b723c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005597b723c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005597b7220f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005597b6ed0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005597b6ecfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2c698eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c698ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c698ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597b6ecfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-misc.c (279 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = icmp sge <8 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %2 to <8 x i8>
# |   store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %3 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %3, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %3 = icmp sge <4 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %3 = icmp sge <2 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x i64>
# |   %3 = icmp sge <1 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = icmp sge <16 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <16 x i1> %2 to <16 x i8>
# |   store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %3 = load <16 x i8>, ptr %ref.tmp.i, align 16
# |   store <16 x i8> %3, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x i16>
# |   %3 = icmp sge <8 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x i32>
# |   %3 = icmp sge <4 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x i64>
# |   %3 = icmp sge <2 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x float>
# |   %3 = fcmp oge <2 x float> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x double>
# |   %3 = fcmp oge <1 x double> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fcmp oge <4 x float> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %3 = fcmp oge <2 x double> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, ali
# | ...
# `---data was truncated (10240/217310) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055cb04d8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb04d84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb04d87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd015933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd01598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd015933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd01591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb04d1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb04d1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb04d01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb049b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb049b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd01591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd01591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd01591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb049b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (280 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 7)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x
# | ...
# `---data was truncated (10240/11356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a65c98056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a65c97d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a65c980cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fc8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fc895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fc8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fc88ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a65c91623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a65c916086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a65c8faf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a65c5aa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a65c5a9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2fc88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fc88ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fc88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a65c5a9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056212016d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056212016a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056212016dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd2f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd2f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd2f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd2f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056212010323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562120103086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005621200e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056211fd97166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056211fd96e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd2f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd2f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd2f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056211fd96d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (282 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2  -target-feature +sme  -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u8_1(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s8_2(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u16_3(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s16_1(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u32_2(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s32_3(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u64_0(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s64_1(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f16_2(<vscale x 8 x half> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_bf16_3(<vscale x 8 x bfloat> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f32_0(<vscale x 4 x float> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f64_1(<vscale x 2 x double> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, <vscale x 2 x double> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %
# | ...
# `---data was truncated (10240/13584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d8c657356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8c6570505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8c6573cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f736f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f736f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f736f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f736f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8c650923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8c6509086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8c64edf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8c619d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8c619ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f736f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f736f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f736f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8c619cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (283 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svzero_zt() #0 {
# | entry:
# |   call void @llvm.aarch64.sme.zero.zt(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b06835656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b068353505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b068356cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f351c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f351c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f351c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f351c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0682ec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0682ec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0682d0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b067f80166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b067f7fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f351c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f351c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f351c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b067f7fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (284 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 1
# |   %6 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | ...
# `---data was truncated (10240/24605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a4b31df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a4b31dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a4b31dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f43d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f43d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f43d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f43d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4b317523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a4b3175086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a4b3159f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a4b2e09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a4b2e08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f43d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f43d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f43d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4b2e08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (285 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055aae896a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aae8967505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aae896acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcc2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcc24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcc2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcc2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aae890023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aae8900086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aae88e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aae8594166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aae8593e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdcc2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcc24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcc24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aae8593d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (286 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005609f267a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005609f2677505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005609f267acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fedea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fede31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609f261023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005609f2610086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005609f25f4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005609f22a4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005609f22a3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3fede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fede330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609f22a3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f5de9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f5de94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f5de97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb56461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5646725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb56461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb564603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f5de2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f5de2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f5de11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f5dac1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f5dac0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb564604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5646050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5646050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f5dac0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (288 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/53158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a5551fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a5551fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a5551fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f912a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f912a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f912a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f912a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a55519423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a555194086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a555178f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a554e28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a554e27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f912a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f912a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f912a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a554e27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (289 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrun_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005601005a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056010059f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601005a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6653733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f665378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6653733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f665371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056010053823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560100538086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056010051cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601001cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601001cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f665371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f665371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f665371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601001cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d42e5a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d42e57505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d42e5acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2c691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d42df023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d42df0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d42dd4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d42a84166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d42a83e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2c691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d42a83d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (291 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559a78d8856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a78d85505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a78d88cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83b3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83b3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83b3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83b3c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a78d1e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a78d1e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a78d02f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a789b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a789b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f83b3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83b3c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83b3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a789b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (292 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000558c9238f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c9238c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c9238fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d69333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d6938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d69333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d6931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c9232523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c92325086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c92309f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c91fb9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c91fb8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d6931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d6931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d6931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c91fb8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (293 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561e5bcdc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e5bcd9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e5bcdccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03dd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03dd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03dd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03dd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e5bc7223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e5bc72086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e5bc56f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e5b906166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e5b905e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03dd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03dd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03dd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e5b905d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (294 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b34c8a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b34c8a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b34c8a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07da533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07da58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07da533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07da51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b34c83c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b34c83c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b34c820f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b34c4d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b34c4cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f07da51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07da51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07da51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b34c4cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629f043d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005629f043a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005629f043dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3524649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35246a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3524649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3524631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629f03d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005629f03d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005629f03b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005629f0067166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005629f0066e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3524632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35246330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35246330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629f0066d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (296 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e9f4dbb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e9f4db8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e9f4dbbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31ca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31ca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31ca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31ca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9f4d5123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e9f4d51086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9f4d35f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e9f49e5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e9f49e4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f31ca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31ca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31ca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9f49e4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (297 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f3271956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f32716505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f32719cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0063f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0063f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0063f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0063f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f326af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f326af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f32693f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f32343166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f32342e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0063f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0063f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0063f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f32342d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (298 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/68255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555efcbc356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555efcbc0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555efcbc3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe58ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe58eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe58ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe58ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555efcb5923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555efcb59086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555efcb3df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555efc7ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555efc7ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe58ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe58ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe58ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555efc7ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (299 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d818cfe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d818cfb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d818cfecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f443a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f443a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f443a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f443a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d818c9423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d818c94086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d818c78f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d818928166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d818927e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f443a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f443a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f443a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d818927d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (300 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559d2ecde56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559d2ecdb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559d2ecdecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f636e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f636e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f636e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f636e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d2ec7423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559d2ec74086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559d2ec58f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559d2e908166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559d2e907e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f636e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f636e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f636e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d2e907d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (301 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ace5afc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ace5af9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ace5afccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd18ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd18ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd18ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd18ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ace5a9223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ace5a92086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ace5a76f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ace5726166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ace5725e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd18ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd18ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd18ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ace5725d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (302 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 0
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 1
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ebff76956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ebff766505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ebff769cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5133249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51332a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5133249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5133231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebff6ff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ebff6ff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ebff6e3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ebff393166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ebff392e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5133232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51332330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51332330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebff392d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (303 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055deddd6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055deddd65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055deddd68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fd7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fd7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fd7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fd7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055deddcfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055deddcfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055deddce2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dedd992166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dedd991e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4fd7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fd7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fd7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dedd991d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (304 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562844cbf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562844cbc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562844cbfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe80d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe80d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe80d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe80d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562844c5523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562844c55086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562844c39f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005628448e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005628448e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe80d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe80d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe80d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628448e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (305 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5f777e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5f777b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5f777ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a33c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a33ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a33c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a33c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5f771423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5f7714086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5f76f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5f73a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5f73a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a33c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a33c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a33c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5f73a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (306 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a77de7c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a77de79505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a77de7ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4382705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f438275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4382705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43826ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a77de1223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a77de12086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a77ddf6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a77daa6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a77daa5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f43826eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43826ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43826ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a77daa5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (307 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrev_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrev_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrev_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b8(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b16(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b32(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b64(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svrev_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559b1848656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559b18483505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559b18486cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91c281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91c28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91c281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91c2803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b1841c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559b1841c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559b18400f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559b180b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559b180afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f91c2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91c28050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91c28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b180afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (308 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x2(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svclamp_single_s16_x2(<vscale x 8 x i16> %op1.coerce0, <vscale x 8 x i16> %op1.coerce1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %op1.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svclamp_single_s32_x2(<vscale x 4 x i32> %op1.coerce0, <vscale x 4 x i32> %op1.coerce1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %op1.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svclamp_single_s64_x2(<vscale x 2 x i64> %op1.coerce0, <vscale x 2 x i64> %op1.coerce1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %op1.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x4(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op1.coerce2, <vscale x 16 x i8> %op1.coerce3, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %op1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/62547) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cd9bd1956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd9bd16505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd9bd19cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3b9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3b958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3b9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3b951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd9bcaf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd9bcaf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd9bc93f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd9b943166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd9b942e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3b951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3b951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3b951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd9b942d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (309 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64, i64,
# | ...
# `---data was truncated (10240/120460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561612fbb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561612fb8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561612fbbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2591333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f259138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2591333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f259131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561612f5123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561612f51086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561612f35f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561612be5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561612be4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f259131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f259131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f259131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561612be4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (310 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmaxnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svmaxnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svmaxnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ced87f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ced87f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ced87f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4486249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44862a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4486249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4486231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ced878c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ced878c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ced8770f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ced8420166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ced841fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4486232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44862330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44862330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ced841fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (311 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000555cc907456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555cc9071505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555cc9074cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb08e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb08e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb08e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb08e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cc900a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555cc900a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555cc8feef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555cc8c9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555cc8c9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb08e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb08e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb08e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cc8c9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (312 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d3b98de56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d3b98db505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d3b98decab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ed681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ed68725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ed681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ed6803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3b987423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d3b9874086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d3b9858f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d3b9508166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d3b9507e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ed6804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ed68050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ed68050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3b9507d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i
# | ...
# `---data was truncated (10240/215478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604b24f456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005604b24f1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005604b24f4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c60a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c60aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c60a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c60a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604b248a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005604b248a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604b246ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005604b211e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005604b211de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c60a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c60a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c60a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604b211dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (314 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtblq_f16(<vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtblq_f32(<vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtblq_f64(<vscale x 2 x double> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtblq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta
# | ...
# `---data was truncated (10240/10820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005610214d956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005610214d6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005610214d9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f782de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f782dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f782de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f782de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056102146f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056102146f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561021453f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561021103166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561021102e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f782de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f782de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f782de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561021102d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (315 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cf3b1d656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf3b1d3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf3b1d6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a51d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a51d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a51d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a51d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf3b16c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf3b16c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf3b150f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf3ae00166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf3adffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3a51d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a51d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a51d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf3adffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (316 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d6c82ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d6c82ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d6c82aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb10e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb10e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb10e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb10e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6c824423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d6c8244086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d6c8228f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d6c7ed8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d6c7ed7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb10e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb10e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb10e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6c7ed7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (317 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale x 16 x 
# | ...
# `---data was truncated (10240/156463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056347051c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563470519505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056347051ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46a7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46a758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46a7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46a751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634704b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634704b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563470496f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563470146166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563470145e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f46a751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46a751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46a751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563470145d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (318 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560b4540b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b45408505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b4540bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0a7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0a715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0a7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0a70ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b453a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b453a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b45385f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b45035166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b45034e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd0a70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0a70ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0a70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b45034d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (319 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005562d3b2d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562d3b2a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562d3b2dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa636f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa636f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa636f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa636f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562d3ac323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562d3ac3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562d3aa7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562d3757166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562d3756e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa636f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa636f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa636f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562d3756d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (320 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef3_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef3_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef3_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef3_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d593f2f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d593f2c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d593f2fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02ce133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02ce18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02ce133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02ce11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d593ec523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d593ec5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d593ea9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d593b59166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d593b58e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f02ce11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02ce11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02ce11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d593b58d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (321 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564f789c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f789c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f789c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffae801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffae80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffae801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffae8003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f7895c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f7895c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f78940f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f785f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f785efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffae8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffae80050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffae80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f785efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (322 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# | 
# | ...
# `---data was truncated (10240/23662) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562d6acdc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d6acd9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d6acdccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b8a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b8a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b8a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b8a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d6ac7223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d6ac72086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d6ac56f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d6a906166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d6a905e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b8a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b8a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b8a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d6a905d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (323 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005614539a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005614539a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005614539a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f299dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f299dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f299dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f299dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056145393f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056145393f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561453923f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005614535d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005614535d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f299dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f299dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f299dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614535d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (324 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb8e26556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb8e262505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb8e265cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33c3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33c338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33c3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33c331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb8e1fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb8e1fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb8e1dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb8de8f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb8de8ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f33c331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33c331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33c331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb8de8ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (325 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055887e54e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055887e54b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055887e54ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1df2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1df2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1df2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1df2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055887e4e423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055887e4e4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055887e4c8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055887e178166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055887e177e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1df2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1df2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1df2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055887e177d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (326 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac2c14456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac2c141505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac2c144cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0595533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f059558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0595533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f059551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac2c0da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac2c0da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac2c0bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac2bd6e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac2bd6de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f059551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f059551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f059551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac2bd6dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (327 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load 
# | ...
# `---data was truncated (10240/31171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000555e967a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555e9679d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555e967a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3506449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3506449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3506431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e9673623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555e96736086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555e9671af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555e963ca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555e963c9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3506432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e963c9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (328 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 8 x half> %0, %1
# |   ret <vscale x 8 x half> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @add_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 4 x float> %0, %1
# |   ret <vscale x 4 x float> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @add_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 2 x double> %0, %1
# |   ret <vscale x 2 x double> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %add = add <vscale x 4 x i32> %1, %0
# |   store <vscale x 4 x i32> %add, ptr %a.addr, align 16
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_inplace_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %add = add <vscale x 2 x i64> %1, %0
# |   store <vscale x 2 x i64> %add, ptr %a.addr, align 16
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <
# | ...
# `---data was truncated (10240/107144) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056048376c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560483769505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056048376ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d7a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d7a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d7a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d7a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056048370223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560483702086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604836e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560483396166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560483395e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d7a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d7a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d7a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560483395d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (329 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_s8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_s16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_s32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_s64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_u8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_u16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_u32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_u64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdupq_lane_f16(<vscale x 8 x half> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdupq_lane_f32(<vscale x 4 x float> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdupq_lane_f64(<vscale x 2 x double> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 {
# | entry:
# |   %x0.addr = alloca i8, align 1
# |   %x1.addr = alloca i8, align 1
# |   %x2.addr = alloca i8, align 1
# |   %x3.addr = alloca i8, align 1
# |   %x4.addr = alloca i8, align 1
# |   %x5.addr = alloca i8, align 1
# |   %x6.addr = alloca i8, align 1
# |   %x7.addr = alloca i8, align 1
# |   %x8.addr = alloca i8, align 1
# |   %x9.addr = alloca i8, align 1
# |   %x10.addr = alloca i8, align 1
# |   %x11.addr = alloca i8, align 1
# |   %x12.addr = alloca i8, align 1
# |   %x13.addr = alloca i8, align 1
# |   %x14.addr = alloca i8, align 1
# |   %x15.addr = alloca i8, align 1
# |   store i8 %x0, ptr %x0.addr, align 1
# |   store i8 %x1, ptr %x1.addr, align 1
# |   store i8 %x2, ptr %x2.addr, align 1
# |   store i8 %x3, ptr %x3.addr, align 1
# |   store i8 %x4, ptr %x4.addr, align 1
# |   store i8 %x5, ptr %x5.addr, align 1
# |   store i8 %x6, ptr %x6.addr, align 1
# |   store i8 %x7, ptr %x7.addr, align 1
# |   store i8 %x8, ptr %x8.addr, align 1
# |   store i8 %x9, ptr %x9.addr, align 1
# |   store i8 %x10, ptr %x10.addr, align 1
# |   store i8 %x11, ptr %x11.addr, align 1
# |   store i8 %x12, ptr %x12.addr, align 1
# |   store i8 %x13, ptr %x13.addr, align 1
# |   store i8 %x14, ptr %x14.addr, align 1
# |   store i8 %x15, ptr %x15.addr, align 1
# |   %0 = load i8, ptr %x0.addr, align 1
# |   %1 = load i8, ptr %x1.addr, align 1
# |   %2 = load i8, ptr %x2.addr, align 1
# |   %3 = load i8, ptr %x3.addr, align 1
# |   %4 = load i8, ptr %x4.addr, align 1
# |   %5 = load i8, ptr %x5.addr, align 1
# |   %6 = load i8, ptr %x6.addr, align 1
# |   %7 = load i8, ptr %x7.addr, align 1
# |   %8 = load i8, ptr %x8.addr, align 1
# |   %9 = load i8, ptr %x9.addr, align 1
# |   %10 = load i8, ptr %x10.addr, align 1
# |   %11 = load i8, ptr %x11.addr, align 1
# |   %12 = load i8, ptr %x12.addr, align 1
# |   %13 = load i8, ptr
# | ...
# `---data was truncated (10240/42600) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559e6f21556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e6f212505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e6f215cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd433249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4332a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd433249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd433231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e6f1ab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e6f1ab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e6f18ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e6ee3f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e6ee3ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd433232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4332330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4332330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e6ee3ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (330 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/176543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557624ec956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557624ec6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557624ec9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8c0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8c04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8c0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8c0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557624e5f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557624e5f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557624e43f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557624af3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557624af2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd8c0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8c04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8c04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557624af2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (331 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x half> %ma
# | ...
# `---data was truncated (10240/619127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654a177756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005654a1774505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005654a1777cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76fcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76fcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76fcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76fcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654a170d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005654a170d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005654a16f1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005654a13a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005654a13a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f76fcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76fcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76fcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654a13a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (332 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.
# | ...
# `---data was truncated (10240/164791) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555820fa956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555820fa6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555820fa9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69dc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69dc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69dc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69dc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555820f3f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555820f3f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555820f23f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555820bd3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555820bd2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f69dc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69dc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69dc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555820bd2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adbbeb656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055adbbeb3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055adbbeb6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f0eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f0eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f0eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f0eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adbbe4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055adbbe4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055adbbe30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055adbbae0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055adbbadfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f0eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f0eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f0eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adbbadfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (334 of 27911)
******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x half> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x float> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x double> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x bfloat> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000559367ff056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559367fed505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559367ff0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd71049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd710a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd71049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd71031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559367f8623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559367f86086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559367f6af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559367c1a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559367c19e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd71032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd710330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd710330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559367c19d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (335 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fb8886d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb8886a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb8886dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ecb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ecb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ecb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ecb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb8880323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb88803086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb887e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb88497166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb88496e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ecb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ecb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ecb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb88496d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (336 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32f16(<vscale x 4 x float> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055993131156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055993130e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559931311cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cc4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cc4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cc4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cc4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599312a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599312a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055993128bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559930f3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559930f3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6cc4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cc4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cc4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559930f3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (337 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005612c8f9356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005612c8f90505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005612c8f93cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a2b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a2b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a2b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612c8f2923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005612c8f29086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005612c8f0df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005612c8bbd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005612c8bbce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a2b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a2b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a2b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612c8bbcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (338 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   ret <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/58597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d7aa94256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d7aa93f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d7aa942cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f872e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f872e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f872e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f872e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7aa8d823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7aa8d8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d7aa8bcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d7aa56c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d7aa56be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f872e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f872e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f872e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7aa56bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (339 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 3, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 4, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564a68c4c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564a68c49505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564a68c4ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1a9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1a958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1a9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1a951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a68be223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564a68be2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564a68bc6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564a68876166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564a68875e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd1a951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1a951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1a951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a68875d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (340 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvt_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvt_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_u32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_s32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, p
# | ...
# `---data was truncated (10240/39207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055800f93456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055800f931505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055800f934cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faeb5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faeb5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faeb5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faeb5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055800f8ca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055800f8ca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055800f8aef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055800f55e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055800f55de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faeb5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faeb5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faeb5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055800f55dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (341 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b35509d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b35509a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b35509dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0baa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0baa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0baa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0baa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b35503323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b355033086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b355017f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b354cc7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b354cc6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb0baa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0baa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0baa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b354cc6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (342 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ac6edf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ac6edc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ac6edfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0941a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0941a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0941a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0941a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ac6e7523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ac6e75086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ac6e59f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ac6b09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ac6b08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0941a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0941a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0941a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ac6b08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (343 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_s32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_u32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svadd_vector_single2_s64(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x
# | ...
# `---data was truncated (10240/34761) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ee9c58a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee9c587505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee9c58acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc454933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc45498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc454933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc45491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee9c52023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee9c520086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee9c504f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee9c1b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee9c1b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc45491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc45491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc45491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee9c1b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (344 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648f36ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005648f36fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005648f36ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c30849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c308a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c30849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c30831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648f369523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005648f3695086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005648f3679f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005648f3329166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005648f3328e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c30832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c308330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c308330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648f3328d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cb9cf556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560cb9cf2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560cb9cf5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f2a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f2a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f2a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f2a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cb9c8b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560cb9c8b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560cb9c6ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560cb991f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560cb991ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f2a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f2a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f2a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cb991ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (346 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16(<vscale x 8 x half> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005645879ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645879aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645879adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92b4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056458794323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564587943086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564587927f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645875d7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645875d6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f92b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92b4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645875d6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (347 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e2b1ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e2b1aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e2b1adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd924905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd92495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd924905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9248ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e2b14323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e2b143086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e2b127f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e2add7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e2add6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd9248eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9248ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9248ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e2add6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce83c8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce83c84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce83c87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1096933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f109698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1096933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f109691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce83c1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce83c1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce83c01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce838b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce838b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f109691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f109691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f109691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce838b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5ce12f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f5ce12c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f5ce12fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f813c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f813c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f813c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f813c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5ce0c523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5ce0c5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5ce0a9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5cdd59166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5cdd58e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f813c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f813c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f813c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5cdd58d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/load.c (350 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %0, align 2
# |   store <8 x half> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %2, ptr %__ret, align 16
# |   %3 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %3, ptr %tmp, align 16
# |   %4 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %0, align 4
# |   store <4 x float> %1, ptr %ref.tmp, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %2, ptr %__ret, align 16
# |   %3 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %3, ptr %tmp, align 16
# |   %4 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <2 x double>, ptr %0, align 8
# |   store <2 x double> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %2, ptr %__ret, align 16
# |   %3 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %3, ptr %tmp, align 16
# |   %4 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   store <2 x i64> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %2, ptr %__ret, align 16
# |   %3 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %3, ptr %tmp, align 16
# |   %4 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store ptr %a
# | ...
# `---data was truncated (10240/415795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x0000557828ce956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557828ce6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557828ce9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ee2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ee20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ee2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ee2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557828c7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557828c7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557828c63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557828913166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557828912e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3ee2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ee20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ee20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557828912d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (351 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a5f0e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a5f0e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a5f0e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ca2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ca258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ca2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ca251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a5f07c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a5f07c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a5f060f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a5ed10166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a5ed0fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ca251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ca251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ca251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a5ed0fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (352 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %and = and <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @or_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %or = or <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @xor_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vsca
# | ...
# `---data was truncated (10240/18831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056365367456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563653671505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563653674cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d04333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d0438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d04333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d0431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056365360a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056365360a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005636535eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056365329e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056365329de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d0431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d0431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d0431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056365329dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (353 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056341bf5256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056341bf4f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056341bf52cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd925f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd925f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd925f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd925eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056341bee823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056341bee8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056341beccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056341bb7c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056341bb7be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd925eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd925eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd925eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056341bb7bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (354 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db7ef3d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055db7ef3a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055db7ef3dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb494d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb494d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb494d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb494d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db7eed323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055db7eed3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055db7eeb7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055db7eb67166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055db7eb66e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb494d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb494d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb494d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db7eb66d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (355 of 27911)
******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | %struct.S = type { ptr, ptr }
# | %struct.T = type { [2 x ptr] }
# | %struct.SS = type { ptr }
# | 
# | @__hip_cuid_ = addrspace(1) global i8 0
# | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4
# |   %1 = load i32, ptr %0, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 {
# | entry:
# |   %x.addr = alloca ptr addrspace(2), align 8, addrspace(5)
# |   %y.addr = alloca ptr addrspace(1), align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr
# |   store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8
# |   store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8
# |   %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0
# |   %1 = load i32, ptr addrspace(2) %arrayidx, align 4
# |   %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8
# |   %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0
# |   store i32 %1, ptr addrspace(1) %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind
# | define dso_local void @_Z4funcPi(ptr noundef %x) #1 {
# | entry:
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr %x, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 {
# | entry:
# |   %s = alloca %struct.S, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %s.ascast = addrspacecast ptr addrspace(5) %s to ptr
# |   %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1
# |   %3 = load ptr, ptr %y, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %4, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 {
# | entry:
# |   %s = alloca ptr, align 8, addrspace(5)
# |   %s.addr = alloca ptr, align 8, addrspace(5)
# |   %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr
# |   store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8
# |   %s1 = load ptr, ptr addrspace(5) %s, align 8
# |   store ptr %s1, ptr %s.addr.ascast, align 8
# |   %0 = load ptr, ptr %s.addr.ascast, align 8
# |   %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %3 = load ptr, ptr %s.addr.ascast, align 8
# |   %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1
# |   %4 = load ptr, ptr %y, align 8
# |   %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0
# |   %5 = load float, ptr %arrayidx2, align 4
# |   %add = fadd contract float %5, 1.000000e+00
# |   store float %add, ptr %arrayidx2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 {
# | entry:
# |   %t = alloca %struct.T, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %t.ascast = addrspacecast ptr addrspace(5) %t to ptr
# |   %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0
# |   %1 = load ptr, ptr %arrayidx, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0
# |   %2 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %2, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1
# |   %3 = load ptr, ptr %arrayidx3, align 8
# |   %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx4, align 4
# |   %add5 = fadd contract float %4, 2.000000e+00
# |   store float %add5, ptr %arrayidx4, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 {
# | entry:
# |   %a = alloca %struct.SS, align 8, addrspace(5)
# |   %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0
# |   store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8
# |   %a.ascast = addrspacecast ptr addrspace(5) %a to ptr
# |   %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0
# |   %0 = load ptr, ptr %x, align 8
# |   %1 = load float, ptr %0, align 4
# |   %add = fadd contract float %1, 3.000000e+00
# |   store float %add, ptr %0, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !2 = !{!"clang version 24.0.0"}
# | !3 = !{}
# | !4 = !{i64 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x0000561f309a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f309a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f309a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1490c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1490ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1490c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1490c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f3093923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f30939086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f3091df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f305cd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f305cce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1490c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1490c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1490c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f305ccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (356 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |  
# | ...
# `---data was truncated (10240/16804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563699ae256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563699adf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563699ae2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8102d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8102d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8102d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8102d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563699a7823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563699a78086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563699a5cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056369970c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056369970be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8102d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8102d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8102d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056369970bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (357 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562655f0e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562655f0b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562655f0ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd782733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd78278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd782733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd78271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562655ea423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562655ea4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562655e88f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562655b38166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562655b37e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd78271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd78271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd78271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562655b37d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (358 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c85f46a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c85f467505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c85f46acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f638bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f638bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f638bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f638bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c85f40023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c85f400086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c85f3e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c85f094166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c85f093e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f638bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f638bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f638bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c85f093d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (359 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557f71e4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f71e40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f71e43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03dc305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03dc35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03dc305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03dc2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f71dd923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f71dd9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f71dbdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f71a6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f71a6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03dc2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03dc2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03dc2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f71a6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (360 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055acc1dd256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055acc1dcf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055acc1dd2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5729505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f572955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5729505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57294ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acc1d6823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055acc1d68086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055acc1d4cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055acc19fc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055acc19fbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f57294eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57294ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57294ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acc19fbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (361 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbo
# | ...
# `---data was truncated (10240/21216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056027661d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056027661a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056027661dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9edb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9edb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9edb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9edb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602765b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005602765b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560276597f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560276247166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560276246e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb9edb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9edb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9edb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560276246d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (362 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055881efd056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055881efcd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055881efd0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc10705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc1075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc10705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc106ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055881ef6623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055881ef66086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055881ef4af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055881ebfa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055881ebf9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc106eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc106ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc106ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055881ebf9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (363 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/427567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055801d00356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055801d000505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055801d003cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efeb3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efeb30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efeb3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efeb3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055801cf9923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055801cf99086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055801cf7df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055801cc2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055801cc2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efeb3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efeb30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efeb30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055801cc2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (364 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ddefe4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ddefe43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ddefe46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c6c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c6c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c6c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c6c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddefddc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ddefddc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ddefdc0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ddefa70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ddefa6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c6c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c6c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c6c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddefa6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (365 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfalse_b() #0 {
# | entry:
# |   ret <vscale x 16 x i1> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055650b1c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055650b1bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055650b1c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc247849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2478a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc247849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc247831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055650b15823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055650b158086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055650b13cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055650adec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055650adebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc247832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2478330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2478330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055650adebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (366 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1rq_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1rq_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1rq_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1rq_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563f273f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563f273f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563f273f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc775733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc77578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc775733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc77571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f2738923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563f27389086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563f2736df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563f2701d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563f2701ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc77571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc77571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc77571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f2701cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (367 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpa_f16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpa_f32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svexpa_f64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564ec830356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ec8300505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ec8303cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa482533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa48258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa482533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa48251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ec829923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ec8299086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ec827df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ec7f2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ec7f2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa48251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa48251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa48251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ec7f2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/poly128.c (368 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   ret i128 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__s1 = alloca i128, align 16
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   store i128 %4, ptr %__s1, align 16
# |   %5 = load ptr, ptr %ptr.addr, align 8
# |   %add.ptr = getelementptr inbounds i128, ptr %5, i64 1
# |   %6 = load i128, ptr %__s1, align 16
# |   store i128 %6, ptr %add.ptr, align 16
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca i128, align 16
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load i64, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3)
# |   %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128
# |   store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16
# |   %4 = load i128, ptr %ref.tmp.i, align 16
# |   store i128 %4, ptr %__ret.i, align 16
# |   %5 = load i128, ptr %__ret.i, align 16
# |   ret i128 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
# | entry:
# |   %__p0.addr.i3 = alloca <2 x i64>, align 16
# |   %__ret.i4 = alloca <1 x i64>, align 8
# |   %__p0.addr.i1 = alloca <2 x i64>, align 16
# |   %__ret.i2 = alloca <1 x i64>, align 8
# |   %__p0.addr.i.i = alloca i64, align 8
# |   %__p1.addr.i.i = alloca i64, align 8
# |   %__ret.i.i = alloca i128, align 16
# |   %ref.tmp.i.i = alloca i128, align 16
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %ref.tmp1.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %2, ptr %__p0.addr.i3, align 16
# |   %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i4, align 8
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load i64, ptr %ref.tmp.i, align 8
# |   %7 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   store <2 x i64> %7, ptr %__p0.addr.i1, align 16
# |   %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8
# |   %10 = load <1 x i64>, ptr %__ret.i2, align 8
# |   store <1 x i64> %10, ptr %ref.tmp1.i, align 8
# |   %11 = load i64, ptr %ref.tmp1.i, align 8
# |   store i64 %6, ptr %__p0.addr.i.i, align 8
# |   store i64 %11, ptr %__p1.addr.i.i, align 8
# |   %12 = load i64, ptr %__p0.addr.i.i, align 8
# |   %13 = load i64, ptr %__p1.addr.i.i, align 8
# |   %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13)
# |   %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128
# |   store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16
# |   %14 = load i128, ptr %ref.tmp.i.i, align 16
# |   store i128 %14, ptr %__ret.i.i, align 16
# |   %15 = load i128, ptr %__ret.i.i, align 16
# |   store i128 %15, ptr %__ret.i, align 16
# |   %16 = load i128, ptr %__ret.i, align 16
# |   ret i128 %16
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.ad
# | ...
# `---data was truncated (10240/19795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558d6569856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d65695505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d65698cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f335c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f335c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f335c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f335c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d6562e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d6562e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d65612f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d652c2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d652c1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f335c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f335c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f335c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d652c1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056450566d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056450566a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056450566dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc8b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc8b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc8b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc8b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056450560323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564505603086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645055e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564505297166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564505296e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc8b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc8b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc8b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564505296d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (370 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %cmp = icmp eq <8 x i8> %2, %3
# |   %sext = sext <8 x i1> %cmp to <8 x i8>
# |   store <8 x i8> %sext, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i32>
# |   store <16 x i32> %sext, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <8 x i64> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i64>
# |   store <8 x i64> %sext, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x 
# | ...
# `---data was truncated (10240/78785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055dabc13f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dabc13c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dabc13fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2068449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20684a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2068449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2068431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dabc0d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dabc0d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dabc0b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dabbd69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dabbd68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2068432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20684330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20684330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dabbd68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (371 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 
# | ...
# `---data was truncated (10240/22063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055642d4c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055642d4c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055642d4c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9980c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9980c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9980c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9980c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055642d45c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055642d45c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055642d440f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055642d0f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055642d0efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9980c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9980c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9980c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055642d0efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (372 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601e1b7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005601e1b74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601e1b77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f510a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f510a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f510a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f510a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601e1b0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005601e1b0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005601e1af1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601e17a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601e17a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f510a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f510a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f510a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601e17a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (373 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1ro_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1ro_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1ro_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1ro_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564236f6756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564236f64505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564236f67cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2553105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f255315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2553105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25530ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564236efd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564236efd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564236ee1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564236b91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564236b90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f25530eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25530ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25530ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564236b90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac6e61156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac6e60e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac6e611cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac5c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac5c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac5c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac5c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac6e5a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac6e5a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac6e58bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac6e23b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac6e23ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac5c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac5c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac5c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac6e23ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (375 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_u8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_u16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_u32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_u64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svinsr_n_f16(<vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> %0, half %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half>, half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svinsr_n_f32(<vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> %0, float %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float>, float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svinsr_n_f64(<vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load double, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> %0, double %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double>, double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svinsr_n_bf16(<vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat>, bfloat) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d43ea7056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d43ea6d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d43ea70cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb866f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb866f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb866f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb866f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d43ea0623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d43ea06086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d43e9eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d43e69a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d43e699e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb866f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb866f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb866f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d43e699d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (376 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclamp_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svclamp_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svclamp_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e6ebde956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e6ebde6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e6ebde9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb745b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb745b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb745b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb745b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6ebd7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e6ebd7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e6ebd63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e6eba13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e6eba12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb745b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb745b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb745b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6eba12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (377 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8>, <vscale x 8 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 8 x i16> %3 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %6, <vscale x 8 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | e
# | ...
# `---data was truncated (10240/32866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e2d361c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2d3619505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2d361ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9319733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f931978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9319733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f931971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2d35b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2d35b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2d3596f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2d3246166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2d3245e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f931971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f931971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f931971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2d3245d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (378 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/21295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e0f627556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e0f6272505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e0f6275cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f355f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f355f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f355f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f355f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0f620b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e0f620b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e0f61eff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e0f5e9f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e0f5e9ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f355f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f355f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f355f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0f5e9ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (379 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrte_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrte_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrte_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055f39825a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f398257505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f39825acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55ca449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55ca4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55ca449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55ca431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3981f023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f3981f0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f3981d4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f397e84166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f397e83e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f55ca432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55ca4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55ca4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f397e83d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (380 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5d271556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e5d2712505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e5d2715cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb36c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb36c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb36c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb36c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5d26ab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e5d26ab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e5d268ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e5d233f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e5d233ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb36c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb36c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb36c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5d233ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (381 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vsc
# | ...
# `---data was truncated (10240/69951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562df160256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562df15ff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562df1602cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a70a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a70a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a70a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a70a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562df159823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562df1598086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562df157cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562df122c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562df122be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6a70a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a70a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a70a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562df122bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (382 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64
# | ...
# `---data was truncated (10240/29175) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a40bdc656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a40bdc3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a40bdc6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cd6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cd658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cd6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cd651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a40bd5c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a40bd5c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a40bd40f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a40b9f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a40b9efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7cd651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cd651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cd651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a40b9efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (383 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cd3b0b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd3b0b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd3b0b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd953305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd95335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd953305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9532ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd3b04d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd3b04d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd3b031f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd3ace1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd3ace0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd9532eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9532ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9532ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd3ace0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (384 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1, <vscale x 16 x i8> %val.coerce2, <vscale x 16 x i8> %val.coerce3) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %val.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %val.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %4 = load i32, ptr %base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale
# | ...
# `---data was truncated (10240/150970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562a9542456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a95421505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a95424cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5576e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5576ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5576e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5576e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a953ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a953ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a9539ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a9504e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a9504de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5576e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5576e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5576e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a9504dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (385 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1, <vscale x 8 x bfloat> %zm.coerce2, <vscale x 8 x bfloat> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, <vscale x 8 x bfloat> %zm.coerce2, 2
# |   %7 = insertvalue { <v
# | ...
# `---data was truncated (10240/13687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561b3acf356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561b3acf0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561b3acf3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd511d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd511d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd511d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd511d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b3ac8923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561b3ac89086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561b3ac6df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561b3a91d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561b3a91ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd511d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd511d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd511d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b3a91cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (386 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldff1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldff1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldff1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/64727) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005600a4fe956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005600a4fe6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005600a4fe9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2272933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f227298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2272933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f227291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600a4f7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600a4f7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600a4f63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005600a4c13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005600a4c12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f227291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f227291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f227291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600a4c12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (387 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef4_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef4_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef4_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef4_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ba2e4c156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba2e4be505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba2e4c1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f177f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f177f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f177f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f177f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba2e45723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba2e457086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba2e43bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba2e0eb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba2e0eae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f177f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f177f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f177f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba2e0ead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442b76e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056442b76b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056442b76ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b01849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b018a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b01849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b01831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056442b70423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056442b704086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056442b6e8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056442b398166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056442b397e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1b01832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b018330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b018330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056442b397d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (389 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055a97ff2756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a97ff24505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a97ff27cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe90333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe9038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe90333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe9031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a97febd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a97febd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a97fea1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a97fb51166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a97fb50e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbe9031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe9031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe9031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a97fb50d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (390 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/63749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055c07cd1e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c07cd1b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c07cd1ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc855a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc855aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc855a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc855a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c07ccb423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c07ccb4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c07cc98f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c07c948166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c07c947e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc855a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc855a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc855a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c07c947d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d97ee956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d97ee6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d97ee9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a83905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a8395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a83905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a838ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d97e7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d97e7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d97e63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d97b13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d97b12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a838eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a838ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a838ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d97b12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (392 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 {
# | entry:
# |   %cnt.addr = alloca target("aarch64.svcount"), align 2
# |   store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2
# |   %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1> %0)
# |   ret target("aarch64.svcount") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561261d9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561261d8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561261d90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74d3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74d3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74d3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74d3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561261d2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561261d26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561261d0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005612619ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005612619b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f74d3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74d3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74d3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612619b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (393 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e06a52256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e06a51f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e06a522cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0576649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05766a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0576649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0576631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e06a4b823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e06a4b8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e06a49cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e06a14c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e06a14be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0576632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05766330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05766330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e06a14bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (394 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556b0f7f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b0f7f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b0f7f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2a6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2a695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2a6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2a68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b0f78d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b0f78d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b0f771f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b0f421166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b0f420e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa2a68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2a68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2a68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b0f420d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (395 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651db1b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005651db1b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005651db1b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bbff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bbff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bbff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bbff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651db14a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651db14a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651db12ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005651dadde166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005651daddde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7bbff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bbff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bbff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651dadddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (396 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f3d75c956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f3d75c6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f3d75c9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbc0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbc038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbc0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbc031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3d755f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f3d755f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f3d7543f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f3d71f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f3d71f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffbc031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbc031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbc031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3d71f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (397 of 27911)
******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# |  #0 0x0000559ed96fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ed96fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ed96fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a7b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a7b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a7b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a7b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ed969423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ed9694086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ed9678f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ed9328166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ed9327e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7a7b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a7b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a7b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ed9327d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (398 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d6226056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d6225d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d62260cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b73b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b73b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b73b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b73aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d621f623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d621f6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d621daf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d61e8a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d61e89e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b73aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b73aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b73aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d61e89d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (399 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_cvtl_f32_x2(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half> %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005559a105a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559a1057505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559a105acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec73105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec7315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec73105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec730ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559a0ff023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559a0ff0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559a0fd4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559a0c84166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559a0c83e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec730eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec730ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec730ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559a0c83d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (400 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> zeroi
# | ...
# `---data was truncated (10240/32102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d65f32156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d65f31e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d65f321cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f852dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f852dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f852dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f852dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d65f2b723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d65f2b7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d65f29bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d65ef4b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d65ef4ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f852dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f852dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f852dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d65ef4ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (401 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563c08af256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c08aef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c08af2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde60733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde6078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde60733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde6071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c08a8823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c08a88086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c08a6cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c0871c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c0871be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde6071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde6071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde6071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c0871bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (402 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005594bd36056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005594bd35d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005594bd360cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd7cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd7cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd7cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd7cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594bd2f623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594bd2f6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005594bd2daf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005594bcf8a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005594bcf89e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd7cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd7cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd7cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594bcf89d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (403 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056300af4756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056300af44505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056300af47cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7a1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7a14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7a1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7a1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056300aedd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056300aedd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056300aec1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056300ab71166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056300ab70e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe7a1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7a14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7a14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056300ab70d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/22298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ee506656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ee5063505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ee5066cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4ab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4ab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4ab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4ab231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ee4ffc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ee4ffc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ee4fe0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ee4c90166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ee4c8fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc4ab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4ab2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4ab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ee4c8fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (405 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_m(<vscale x 8 x bfloat> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eca2f0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eca2eff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eca2f02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0397533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f039758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0397533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f039751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eca2e9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eca2e98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eca2e7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eca2b2c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eca2b2be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f039751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f039751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f039751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eca2b2bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (406 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_571 = alloca float, align 4
# |   %__s0_571 = alloca float, align 4
# |   %__s1_571 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_571, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_571, align 8
# |   %2 = load float, ptr %__s0_571, align 4
# |   %3 = load <2 x float>, ptr %__s1_571, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_571, align 4
# |   %8 = load float, ptr %__ret_571, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret_570 = alloca double, align 8
# |   %__s0_570 = alloca double, align 8
# |   %__s1_570 = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_570, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_570, align 8
# |   %2 = load double, ptr %__s0_570, align 8
# |   %3 = load <1 x double>, ptr %__s1_570, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %4, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_570, align 8
# |   %8 = load double, ptr %__ret_570, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_577 = alloca float, align 4
# |   %__s0_577 = alloca float, align 4
# |   %__s1_577 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_577, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_577, align 16
# |   %2 = load float, ptr %__s0_577, align 4
# |   %3 = load <4 x float>, ptr %__s1_577, align 16
# |   store <4 x float> %3, ptr %__s0, align 16
# |   %4 = load <4 x float>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <4 x float> %4, i32 3
# |   store float %vgetq_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_577, align 4
# |   %8 = load float, ptr %__ret_577, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret_575 = alloca double, align 8
# |   %__s0_575 = alloca double, align 8
# |   %__s1_575 = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_575, align 8
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1_575, align 16
# |   %2 = load double, ptr %__s0_575, align 8
# |   %3 = load <2 x double>, ptr %__s1_575, align 16
# |   store <2 x double> %3, ptr %__s0, align 16
# |   %4 = load <2 x double>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <2 x double> %4, i32 1
# |   store double %vgetq_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_575, align 8
# |   %8 = load double, ptr %__ret_575, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca double, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store double %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x double>, ptr %__p0.addr.i, align 8
# |   %3 = load double, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <1 x double> %2 to double
# |   %5 = fmul double %4, %3
# |   store double %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_626 = alloca float, align 4
# |   %__s0_626 = alloca float, align 4
# |   %__s1_626 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_626, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_626, align 8
# |   %2 = load float, ptr %__s0_626, align 4
# |   %3 = load <2 x float>, ptr %__s1_626, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   store float %2, ptr %__p0.addr.i, align 4
# |   store float %7, ptr %__p1.addr.i, align 4
# |   %8 = load float, ptr %__p0.addr.i, align 4
# |   %9 = load float, ptr %__p1.addr.i, align 4
# |   %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9)
# |   store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4
# |   %10 = load float, ptr %ref.tmp.i, align 4
# |   store float %10, ptr %__ret.i, align 4
# |   %11 = load float, ptr %__ret.i, align 4
# |   store float %11, ptr %__ret_626, align 4
# |   %12 = load float, ptr %__ret_626, align 4
# |   store float %12, ptr %tmp1, align 4
# |   %13 = load float, ptr %tmp1, align 4
# |   ret float %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_636 = alloca float, align 4
# |   %__s0_636 = alloca float, align 4
# |   %__s1_636 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_636, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_636, align 16
# |   %2 = load float, ptr %__s0_636, align 4
# |   %3 = load <4 x float>, ptr %__s1_636, align 16
# |   store <4 x float> %3, ptr %
# | ...
# `---data was truncated (10240/74804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b7147fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b7147f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b7147fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9c7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9c70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9c7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9c7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b71479223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b714792086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b714776f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b714426166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b714425e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9c7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9c70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9c70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b714425d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (407 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset, i64 no
# | ...
# `---data was truncated (10240/287205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e43a0356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e43a00505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e43a03cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4ea049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4ea0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4ea049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4ea031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e4399923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e43999086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e4397df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e4362d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e4362ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd4ea032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4ea0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4ea0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e4362cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (408 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 13, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 29, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cd463db56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd463d8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd463dbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe48533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe4858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe48533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe4851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd4637123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd46371086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd46355f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd46005166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd46004e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbe4851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe4851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe4851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd46004d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (409 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585ae0ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005585ae0ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005585ae0edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3fbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3fbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3fbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3fbaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585ae08323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005585ae083086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005585ae067f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005585add17166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005585add16e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc3fbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3fbaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3fbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585add16d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (410 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = c
# | ...
# `---data was truncated (10240/207083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564328d8956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564328d86505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564328d89cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc99533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc9958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc99533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc9951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564328d1f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564328d1f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564328d03f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005643289b3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005643289b2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc9951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc9951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc9951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643289b2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (411 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055739471c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557394719505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055739471ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddc081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddc08725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddc081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddc0803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573946b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005573946b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557394696f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557394346166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557394345e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fddc0804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddc08050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddc08050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557394345d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8783ba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e8783b7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e8783bacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80f8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80f878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80f8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80f871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e87835023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e878350086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e878334f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e877fe4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e877fe3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80f871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80f871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80f871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e877fe3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c88e6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c88e63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c88e66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc69ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc69ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc69ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc69ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c88dfc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c88dfc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c88de0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c88a90166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c88a8fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc69ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc69ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc69ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c88a8fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (414 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr_z(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000564c5321c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c53219505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c5321ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f168fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f168fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f168fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f168fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c531b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c531b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c53196f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c52e46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c52e45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f168fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f168fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f168fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c52e45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/95445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557570b2756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557570b24505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557570b27cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb90a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb90a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb90a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb90a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557570abd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557570abd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557570aa1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557570751166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557570750e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb90a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb90a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb90a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557570750d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643175b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005643175b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005643175b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f883be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f883be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f883be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f883be03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056431754e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056431754e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564317532f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005643171e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005643171e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f883be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f883be050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f883be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643171e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (417 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c7cfbca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c7cfbc7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c7cfbcacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f14305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f1435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f14305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f142ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7cfb6023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c7cfb60086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c7cfb44f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c7cf7f4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c7cf7f3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f142eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f142ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f142ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7cf7f3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (418 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4
# | ...
# `---data was truncated (10240/96257) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f58fbfa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f58fbf7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f58fbfacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff07ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff07eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff07ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff07ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f58fb9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f58fb90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f58fb74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f58f824166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f58f823e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff07ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff07ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff07ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f58f823d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (419 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcompact_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcompact_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561f1a94056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f1a93d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f1a940cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50d2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50d22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50d2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50d2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f1a8d623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f1a8d6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f1a8baf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f1a56a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f1a569e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f50d2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50d22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50d22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f1a569d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (420 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ce89e3956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce89e36505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce89e39cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb454f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb454f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb454f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb454f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce89dcf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce89dcf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce89db3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce89a63166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce89a62e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb454f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb454f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb454f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce89a62d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/len.c (421 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c         | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vscale.i64() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000559df9b6a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559df9b67505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559df9b6acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9253a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9253aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9253a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9253a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559df9b0023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559df9b00086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559df9ae4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559df9794166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559df9793e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9253a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9253a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9253a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559df9793d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (422 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555820aea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555820ae7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555820aeacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff4dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff4dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff4dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff4dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555820a8023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555820a80086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555820a64f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555820714166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555820713e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff4dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff4dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff4dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555820713d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (423 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 2)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_laneq_f16(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half> %0, i32 4)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_laneq_f32(<vscale x 4 x float> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float> %0, i32 1)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_laneq_f64(<vscale x 2 x double> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double> %0, i32 1)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_laneq_bf16(<vscale x 8 x bfloat> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat> %0, i32 3)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 1)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000565479b9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565479b94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565479b97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b5dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b5dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b5dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b5dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565479b2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565479b2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565479b11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005654797c1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005654797c0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5b5dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b5dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b5dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654797c0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d85a91e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d85a91b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d85a91ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c5aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d85a8b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d85a8b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d85a898f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d85a548166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d85a547e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87c5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c5aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d85a547d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (425 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/11769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056095509556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560955092505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560955095cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8952333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f895238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8952333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f895231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056095502b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056095502b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056095500ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560954cbf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560954cbee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f895231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f895231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f895231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560954cbed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (426 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_x(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_m(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562652e6256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562652e5f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562652e62cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6190f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6190f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6190f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6190f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562652df823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562652df8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562652ddcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562652a8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562652a8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6190f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6190f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6190f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562652a8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (427 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 0
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 1
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 3
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555768b2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555768b27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555768b2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8ad733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8ad78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8ad733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8ad71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555768ac023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555768ac0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555768aa4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555768754166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555768753e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff8ad71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8ad71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8ad71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555768753d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (428 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c4965a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c49659d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c4965a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f772aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f772aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f772aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f772aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c49653623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c496536086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c49651af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c4961ca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c4961c9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f772aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f772aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f772aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4961c9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (429 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmmla_f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 2 x double>, align 16
# |   %y.addr = alloca <vscale x 2 x double>, align 16
# |   %z.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x, ptr %x.addr, align 16
# |   store <vscale x 2 x double> %y, ptr %y.addr, align 16
# |   store <vscale x 2 x double> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %y.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %z.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a75172356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a751720505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a751723cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4d201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4d20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4d201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4d2003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7516b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a7516b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a75169df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a75134d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a75134ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4d2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4d20050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4d20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a75134cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (430 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d0f42c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557d0f429505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557d0f42ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff010733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff01078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff010733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff01071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d0f3c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557d0f3c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557d0f3a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557d0f056166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557d0f055e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff01071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff01071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff01071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d0f055d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (431 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d2efec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556d2efe9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556d2efeccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8e0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8e06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8e0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8e0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d2ef8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556d2ef82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556d2ef66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556d2ec16166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556d2ec15e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff8e0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8e06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8e06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d2ec15d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (432 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577ddfdd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005577ddfda505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005577ddfddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fbc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fbc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fbc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fbc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577ddf7323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005577ddf73086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005577ddf57f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005577ddc07166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005577ddc06e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5fbc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fbc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fbc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577ddc06d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (433 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b05953956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b059536505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b059539cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8356905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f835695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8356905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83568ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0594cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0594cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0594b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b059163166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b059162e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f83568eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83568ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83568ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b059162d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (434 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef2_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef4_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005577996a856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005577996a5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005577996a8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd90b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd90b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd90b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd90b2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055779963e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055779963e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557799622f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005577992d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005577992d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd90b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd90b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd90b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577992d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (435 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_s8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_s16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_s32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_s64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_u8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_u16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_u32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_u64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbl_f16(<vscale x 8 x half> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbl_f32(<vscale x 4 x float> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtbl_f64(<vscale x 2 x double> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtbl_bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptra
# | ...
# `---data was truncated (10240/10361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b5ceddb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5cedd8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5ceddbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e11449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e114a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e11449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e11431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5ced7123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5ced71086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5ced55f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5cea05166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5cea04e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1e11432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e114330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e114330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5cea04d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bb279656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bb2793505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bb2796cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55c561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55c56725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55c561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55c5603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bb272c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bb272c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bb2710f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bb23c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bb23bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f55c5604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55c56050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55c56050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bb23bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (437 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d92c51556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d92c512505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d92c515cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6497505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f649755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6497505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64974ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d92c4ab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d92c4ab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d92c48ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d92c13f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d92c13ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f64974eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64974ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64974ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d92c13ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (438 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsplice_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/14328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e79c2a556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e79c2a2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e79c2a5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7629133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f762918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7629133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f762911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e79c23b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e79c23b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e79c21ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e79becf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e79becee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f762911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f762911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f762911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e79beced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (439 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555e598e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555e598e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555e598e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfa7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfa7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfa7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfa7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e5987d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555e5987d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555e59861f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555e59511166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555e59510e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcfa7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfa7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfa7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e59510d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (440 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056550c52356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056550c520505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056550c523cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56adb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56adb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56adb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56adaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056550c4b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056550c4b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056550c49df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056550c14d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056550c14ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f56adaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56adaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56adaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056550c14cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed4d71a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed4d717505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed4d71acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddc0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddc058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddc0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddc051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed4d6b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed4d6b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed4d694f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed4d344166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed4d343e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fddc051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddc051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddc051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed4d343d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (442 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b53ff356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b53ff0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b53ff3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe851533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe85158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe851533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe85151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b53f8923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b53f89086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b53f6df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b53c1d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b53c1ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe85151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe85151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe85151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b53c1cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (443 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %
# | ...
# `---data was truncated (10240/74176) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bd1602156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bd1601e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bd16021cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6b3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6b30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6b3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6b3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd15fb723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bd15fb7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bd15f9bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bd15c4b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bd15c4ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe6b3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6b30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6b30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd15c4ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebfb1ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ebfb1a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ebfb1accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f097a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f097a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f097a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f097a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebfb14223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ebfb142086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ebfb126f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ebfadd6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ebfadd5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f097a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f097a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f097a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebfadd5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c8aea556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c8aea2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c8aea5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c05d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c05d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c05d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c05d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c8ae3b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c8ae3b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c8ae1ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c8aacf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c8aacee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9c05d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c05d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c05d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c8aaced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (446 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579b4a4056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579b4a3d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579b4a40cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33cc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33cc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33cc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33cc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579b49d623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579b49d6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579b49baf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579b466a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579b4669e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f33cc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33cc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33cc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579b4669d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (447 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056142616256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056142615f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561426162cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3a3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3a3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3a3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3a3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614260f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005614260f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005614260dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561425d8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561425d8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa3a3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3a3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3a3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561425d8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (448 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c4fc8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c4fc87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c4fc8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe790649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe790649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe790631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c4fc2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c4fc20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c4fc04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c4f8b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c4f8b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe790632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7906330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c4f8b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (449 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005579d8b6456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579d8b61505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579d8b64cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe055049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0550a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe055049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe055031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579d8afa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579d8afa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579d8adef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579d878e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579d878de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe055032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0550330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0550330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579d878dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac9e97056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac9e96d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac9e970cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3060505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f306055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3060505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30604ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac9e90623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac9e906086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac9e8eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac9e59a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac9e599e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f30604eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30604ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30604ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac9e599d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (451 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   %10 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %10)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/15164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055742f1a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055742f1a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055742f1a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff65f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff65f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff65f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff65f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055742f13923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055742f139086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055742f11df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055742edcd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055742edcce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff65f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff65f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff65f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055742edccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/store.c (452 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   store <4 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <2 x float>
# |   store <2 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   store <1 x double> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %val.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %val, ptr %val.addr, align 8
# |   %0 = load <8 x i8>, ptr %val.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   store <4 x i16> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store <1 x i64> %val, ptr %val.addr, align 8
# |   %0 = load <1 x i64>, ptr %val.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %ptr.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   store <1 x i64> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   store <8 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   %__s1 = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   store <4 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr
# | ...
# `---data was truncated (10240/446007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x00005604c524856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005604c5245505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005604c5248cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f834d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f834d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f834d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f834d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604c51de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005604c51de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604c51c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005604c4e72166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005604c4e71e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f834d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f834d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f834d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604c4e71d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (453 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vsca
# | ...
# `---data was truncated (10240/53696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e32357356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e323570505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e323573cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d38f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d38f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d38f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d38f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e32350923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e323509086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3234edf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e32319d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e32319ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d38f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d38f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d38f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e32319cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (454 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i32>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store 
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559396dee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559396deb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559396deecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e88933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e8898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e88933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e8891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559396d8423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559396d84086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559396d68f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559396a18166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559396a17e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1e8891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e8891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e8891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559396a17d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (455 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <8 x i16> %2, %3
# |   store <8 x i16> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <4 x i32> %2, %3
# |   store <4 x i32> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   s
# | ...
# `---data was truncated (10240/798827) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c60c62a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c60c627505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c60c62acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb65c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb65c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb65c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb65c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c60c5c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c60c5c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c60c5a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c60c254166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c60c253e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb65c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb65c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb65c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c60c253d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (456 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clasta.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055863abb156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055863abae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055863abb1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2056649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20566a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2056649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2056631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055863ab4723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055863ab47086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055863ab2bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055863a7db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055863a7dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2056632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20566330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20566330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055863a7dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (457 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005645e1e3756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645e1e34505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645e1e37cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f905d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f905d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f905d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f905d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645e1dcd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645e1dcd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645e1db1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645e1a61166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645e1a60e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f905d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f905d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f905d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645e1a60d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (458 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 8, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 9, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557bcf7a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557bcf79f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557bcf7a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dae049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dae0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dae049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dae031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bcf73823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557bcf738086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557bcf71cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557bcf3cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557bcf3cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5dae032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dae0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dae0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bcf3cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (459 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055833e46e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055833e46b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055833e46ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f852af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f852af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f852af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f852af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055833e40423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055833e404086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055833e3e8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055833e098166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055833e097e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f852af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f852af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f852af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055833e097d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (460 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bf046e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bf046de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bf046e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcd9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcd9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcd9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcd9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf0467723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bf04677086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bf0465bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bf0430b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bf0430ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdcd9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcd9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcd9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf0430ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (461 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056146dc0456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056146dc01505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056146dc04cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce96049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce960a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce96049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce96031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056146db9a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056146db9a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056146db7ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056146d82e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056146d82de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce96032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce960330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce960330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056146d82dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (462 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562b7ed7c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562b7ed79505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562b7ed7ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4155133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f415518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4155133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f415511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b7ed1223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562b7ed12086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562b7ecf6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562b7e9a6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562b7e9a5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f415511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f415511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f415511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7e9a5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (463 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea7f74956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea7f746505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea7f749cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdca4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdca42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdca4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdca4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea7f6df23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea7f6df086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea7f6c3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea7f373166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea7f372e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdca4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdca42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdca42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea7f372d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (464 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %and = and <8 x i8> %2, %3
# |   store <8 x i8> %and, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %and = and <8 x i64> %0, %1
# |   store <8 x i64> %and, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x
# | ...
# `---data was truncated (10240/35910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056023206c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560232069505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056023206ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056023200223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560232002086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560231fe6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560231c96166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560231c95e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007facc551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560231c95d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsli
# | ...
# `---data was truncated (10240/14908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb3334f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eb3334c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eb3334fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41ded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41ded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41ded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41ded1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb332e523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eb332e5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eb332c9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eb32f79166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eb32f78e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f41ded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41ded1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41ded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb32f78d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (466 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate2_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %1, 1
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcreate2_f32(<vscale x 4 x float> %x0, <vscale x 4 x float> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x float>, align 16
# |   %x1.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x float> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %1, 1
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svcreate2_f64(<vscale x 2 x double> %x0, <vscale x 2 x double> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x double>, align 16
# |   %x1.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x double> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %1, 1
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_mf8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svcreate2_bf16(<vscale x 8 x bfloat> %x0, <vscale x 8 x bfloat> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %x1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x bfloat> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/10734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560d409fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560d409f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560d409fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca51133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca5118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca51133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca5111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d4099223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560d40992086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560d40976f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560d40626166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560d40625e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca5111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca5111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca5111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d40625d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (467 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557706b9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557706b8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557706b90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d56333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d5638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d56333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d5631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557706b2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557706b26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557706b0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005577067ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005577067b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d5631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d5631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d5631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577067b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056525240256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652523ff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565252402cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66f0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66f0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66f0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66f0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056525239823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565252398086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056525237cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056525202c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056525202be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f66f0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66f0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66f0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056525202bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (469 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmsb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056210238156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056210237e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562102381cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6104533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f610458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6104533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f610451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210231723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562102317086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005621022fbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562101fab166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562101faae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f610451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f610451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f610451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562101faad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (470 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556456b356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005556456b0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005556456b3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f497d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f497d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f497d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f497d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055564564923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555645649086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055564562df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005556452dd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005556452dce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f497d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f497d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f497d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556452dcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (471 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/100960) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f4874d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f4874a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f4874dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3540733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f354078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3540733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f354071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f486e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f486e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f486c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f48377166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f48376e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f354071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f354071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f354071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f48376d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (472 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613c0f8256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613c0f7f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613c0f82cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb3b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb3b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb3b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb3b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613c0f1823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613c0f18086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613c0efcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613c0bac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613c0babe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdb3b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb3b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb3b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613c0babd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607a620056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005607a61fd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005607a6200cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dcaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dcaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dcaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dcaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607a619623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005607a6196086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005607a617af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607a5e2a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607a5e29e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6dcaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dcaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dcaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607a5e29d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (474 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560e9122456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e91221505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e91224cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcf181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcf18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcf181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcf1803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e911ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e911ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e9119ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e90e4e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e90e4de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdcf1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcf18050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcf18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e90e4dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (475 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %5, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %5, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %5, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %5, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# | ...
# `---data was truncated (10240/34217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056058a2c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056058a2c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056058a2c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef40849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef408a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef40849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef40831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056058a25923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056058a259086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056058a23df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560589eed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560589eece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef40832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef408330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef408330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560589eecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/68133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7096e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d7096e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d7096e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbebc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbebc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbebc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbebc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d70967b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d70967b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d70965ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d70930f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d70930ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbebc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbebc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbebc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d70930ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (477 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bb383656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563bb3833505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563bb3836cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f409e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f409e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f409e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f409e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bb37cc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563bb37cc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563bb37b0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563bb3460166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563bb345fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f409e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f409e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f409e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bb345fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm64-lanes.c (478 of 27911)
******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %src, ptr %src.addr, align 8
# |   %0 = load <2 x float>, ptr %src.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vdups_lane = extractelement <2 x float> %1, i32 0
# |   store float %vdups_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <1 x double>, ptr %src.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vdupd_lane = extractelement <1 x double> %1, i32 0
# |   store double %vdupd_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b594e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b594de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b594e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9be305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9be35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9be305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9be2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b5947723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b59477086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b5945bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b5910b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b5910ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe9be2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9be2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9be2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b5910ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (479 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vsc
# | ...
# `---data was truncated (10240/72568) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055aa7ed4056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aa7ed3d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aa7ed40cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0052705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f005275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0052705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00526ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa7ecd623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aa7ecd6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aa7ecbaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aa7e96a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aa7e969e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f00526eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00526ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00526ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa7e969d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (480 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005578cbe5e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578cbe5b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578cbe5ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc55c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc55c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc55c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc55c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578cbdf423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578cbdf4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578cbdd8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578cba88166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578cba87e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc55c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc55c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc55c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578cba87d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e35354f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e35354c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e35354fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5017849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5017849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5017831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3534e523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e3534e5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3534c9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e353179166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e353178e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5017832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50178330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e353178d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (482 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c6cdee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c6cdeb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c6cdeecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f917f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f917f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f917f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f917f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c6cd8423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c6cd84086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c6cd68f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c6ca18166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c6ca17e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f917f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f917f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f917f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c6ca17d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (483 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svrshl_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svrshl_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> 
# | ...
# `---data was truncated (10240/93119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a11517b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a115178505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a11517bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b9b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b9b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b9b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b9b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a11511123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a115111086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a1150f5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a114da5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a114da4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5b9b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b9b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b9b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a114da4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bbe09556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555bbe092505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555bbe095cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55e181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55e18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55e181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55e1803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bbe02b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555bbe02b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555bbe00ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555bbdcbf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555bbdcbee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f55e1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55e18050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55e18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bbdcbed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (485 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_ra
# | ...
# `---data was truncated (10240/35066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x0000562b23a7256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562b23a6f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562b23a72cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4605c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4605ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4605c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4605c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b23a0823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562b23a08086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562b239ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562b2369c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562b2369be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4605c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4605c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4605c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b2369bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (486 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556bae6ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556bae6a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556bae6accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3dd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3dd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3dd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3dd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bae64223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556bae642086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556bae626f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556bae2d6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556bae2d5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd3dd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3dd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3dd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bae2d5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bbe09e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559bbe09b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559bbe09ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d24333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d2438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d24333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d2431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bbe03423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559bbe034086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559bbe018f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559bbdcc8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559bbdcc7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d2431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d2431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d2431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bbdcc7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (488 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a0a7b2d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a0a7b2a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a0a7b2dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7562649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75626a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7562649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7562631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0a7ac323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a0a7ac3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a0a7aa7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a0a7757166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a0a7756e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7562632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75626330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75626330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0a7756d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (489 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef2_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef2_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef2_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef2_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a465e1956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a465e16505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a465e19cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff659933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff65998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff659933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff65991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a465daf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a465daf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a465d93f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a465a43166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a465a42e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff65991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff65991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff65991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a465a42d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (490 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564659d3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564659d2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564659d31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe03b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe03b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe03b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe03b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564659cc723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564659cc7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564659cabf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056465995b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056465995ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe03b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe03b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe03b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056465995ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (491 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056422f89f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056422f89c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056422f89fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91abf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91abf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91abf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91abf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056422f83523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056422f835086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056422f819f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056422f4c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056422f4c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f91abf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91abf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91abf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056422f4c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (492 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563fe40956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563fe406505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563fe409cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30e1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30e1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30e1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30e1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563fe39f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005563fe39f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005563fe383f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005563fe033166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005563fe032e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f30e1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30e1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30e1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563fe032d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (493 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c59234756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c592344505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c592347cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb35849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb358a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb35849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb35831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5922dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5922dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5922c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c591f71166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c591f70e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb35832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb358330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb358330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c591f70d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (494 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056261dd4756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056261dd44505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056261dd47cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9621f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9621f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9621f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9621f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056261dcdd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056261dcdd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056261dcc1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056261d971166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056261d970e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9621f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9621f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9621f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056261d970d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (495 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000561e64fe256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e64fdf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e64fe2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1035b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1035b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1035b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1035b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e64f7823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e64f78086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e64f5cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e64c0c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e64c0be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1035b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1035b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1035b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e64c0bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (496 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7af15956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7af156505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7af159cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bcb305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bcb35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bcb305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bcb2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7af0ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7af0ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7af0d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7aed83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7aed82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9bcb2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bcb2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bcb2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7aed82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (497 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i16>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/18010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558d05ad456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d05ad1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d05ad4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d0c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d0c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d0c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d0c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d05a6a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d05a6a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d05a4ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d056fe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d056fde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d0c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d0c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d0c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d056fdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (498 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0c595756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e0c5954505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e0c5957cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5424705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f542475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5424705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54246ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0c58ed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e0c58ed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e0c58d1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e0c5581166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e0c5580e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f54246eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54246ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54246ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0c5580d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (499 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/13593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055887c3fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055887c3fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055887c3fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5550d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5550d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5550d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5550ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055887c39423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055887c394086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055887c378f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055887c028166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055887c027e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5550ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5550cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5550cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055887c027d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560588a556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005560588a2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005560588a5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5db2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5db2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5db2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5db2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055605883b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055605883b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055605881ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005560584cf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005560584cee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5db2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5db2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5db2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560584ced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576942ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576942ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576942aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa356f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa356f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa356f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa356f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055769424423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557694244086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557694228f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557693ed8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557693ed7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa356f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa356f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa356f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557693ed7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = loa
# | ...
# `---data was truncated (10240/23447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b0ad0056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559b0acfd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559b0ad00cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f230c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f230c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f230c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f230c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b0ac9623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559b0ac96086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559b0ac7af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559b0a92a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559b0a929e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f230c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f230c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f230c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b0a929d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (503 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005572e40de56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005572e40db505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005572e40decab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9662f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9662f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9662f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9662f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572e407423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005572e4074086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005572e4058f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005572e3d08166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005572e3d07e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9662f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9662f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9662f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572e3d07d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (504 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eef175556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eef1752505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eef1755cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8419533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f841958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8419533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f841951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eef16eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eef16eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eef16cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eef137f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eef137ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f841951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f841951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f841951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eef137ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (505 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055582a2d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055582a2d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055582a2d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69c4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69c46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69c4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69c4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055582a26a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055582a26a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055582a24ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555829efe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555829efde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f69c4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69c46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69c46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555829efdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640cf68e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640cf68b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640cf68ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb585505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb58555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb585505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5854ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640cf62423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640cf624086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640cf608f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640cf2b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640cf2b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb5854eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5854ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5854ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640cf2b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (507 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bbda7456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558bbda71505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558bbda74cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5488133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f548818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5488133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f548811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bbda0a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558bbda0a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558bbd9eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558bbd69e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558bbd69de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f548811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f548811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f548811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bbd69dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b3cde856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b3cde5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b3cde8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9baa333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9baa38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9baa333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9baa31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b3cd7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b3cd7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b3cd62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b3ca12166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b3ca11e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9baa31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9baa31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9baa31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b3ca11d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (509 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/68073) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d08dfac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d08dfa9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d08dfaccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8d8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8d8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8d8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8d8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d08df4223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d08df42086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d08df26f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d08dbd6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d08dbd5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd8d8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8d8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8d8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d08dbd5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d5a82956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d5a826505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d5a829cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efca9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efca958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efca9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efca951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d5a7bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d5a7bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d5a7a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d5a453166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d5a452e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efca951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efca951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efca951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d5a452d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (511 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b36e3a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b36e3a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b36e3a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bafd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bafd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bafd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bafced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b36e33c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b36e33c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b36e320f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b36dfd0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b36dfcfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0bafceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bafcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bafcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b36dfcfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (512 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>,
# | ...
# `---data was truncated (10240/159327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558e159cf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e159cc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e159cfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbce5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbce518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbce5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbce511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e1596523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e15965086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e15949f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e155f9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e155f8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbce511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbce511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbce511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e155f8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-3v.c (513 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %and.i = and <8 x i16> %2, %3
# |   store <8 x i16> %and.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %and.i = and <2 x i32> %2, %3
# |   store <2 x i32> %and.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %and.i = and <4 x i32> %2, %3
# |   store <4 x i32> %and.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %and.i = and <1 x i64> %2, %3
# |   store <1 x i64> %and.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %and.i = and <2 x i64> %2, %3
# |   store <2 x i64> %and.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, al
# | ...
# `---data was truncated (10240/70553) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570ed2ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005570ed2cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005570ed2cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f917981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91798725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f917981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9179803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570ed26423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570ed264086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570ed248f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570ecef8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570ecef7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9179804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91798050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91798050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570ecef7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (514 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <16 x i8> %4 to <8 x half>
# |   %fmla1 = bitcast <16 x i8> %3 to <8 x half>
# |   %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %fmla2, ptr %ref.tmp, align 16
# |   %7 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %7, ptr %__ret, align 16
# |   %8 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %8, ptr %tmp, align 16
# |   %9 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %10, ptr %__ret, align 8
# |   %11 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %11, ptr %tmp, align 8
# |   %12 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16
# | ...
# `---data was truncated (10240/13273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562469ae656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562469ae3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562469ae6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6605049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66050a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6605049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6605031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562469a7c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562469a7c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562469a60f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562469710166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056246970fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6605032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66050330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66050330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056246970fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (515 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmac
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562efdc3856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562efdc35505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562efdc38cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81c8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81c8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81c8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81c8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562efdbce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562efdbce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562efdbb2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562efd862166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562efd861e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f81c8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81c8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81c8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562efd861d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (516 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056347b90a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056347b907505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056347b90acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f56f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f56f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f56f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f56eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056347b8a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056347b8a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056347b884f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056347b534166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056347b533e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4f56eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f56eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f56eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056347b533d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/perm.c (517 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, 
# | ...
# `---data was truncated (10240/231562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x0000558cae64a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558cae647505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558cae64acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f911d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f911d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f911d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f911d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cae5e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558cae5e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558cae5c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558cae274166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558cae273e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f911d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f911d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f911d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cae273d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (518 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon         -target-feature +v8.3a         -target-feature +fullfp16         -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i)
# |   %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8>
# |   store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %acc.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float>
# |   %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float>
# |   %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i)
# |   %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8>
# |   store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %lhs.addr = alloca <8 x half>, align 16
# |   %rhs.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %lhs, ptr %lhs.addr, align 16
# |   store <8 x half> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %lhs.addr, align 16
# |   %2 = load <8 x half>, ptr %rhs.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i)
# |   %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %lhs.addr = alloca <4 x float>, align 16
# |   %rhs.addr = alloca <4 x float>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <4 x float> %lhs, ptr %lhs.addr, align 16
# |   store <4 x float> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <4 x float>, ptr %lhs.addr, align 16
# |   %2 = load <4 x float>, ptr %rhs.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float>
# |   %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float>
# |   %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i)
# |   %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <2 x double>, align 16
# |   %lhs.addr = alloca <2 x double>, align 16
# |   %rhs.addr = alloca <2 x double>, align 16
# |   store <2 x double> %acc, ptr %acc.addr, align 16
# |   store <2 x double> %lhs, ptr %lhs.addr, align 16
# |   store <2 x double> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <2 x double>, ptr %acc.addr, align 16
# |   %1 = load <2 x double>, ptr %lhs.addr, align 16
# |   %2 = load <2 x double>, ptr %rhs.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double>
# |   %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double>
# |   %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double>
# |   %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i)
# |   %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16
# |   %6 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %6, ptr %__ret.i, align 16
# |   %7 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v
# | ...
# `---data was truncated (10240/166298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# |  #0 0x00005580c0e6f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005580c0e6c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005580c0e6fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89a8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89a88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89a8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89a8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580c0e0523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005580c0e05086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005580c0de9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005580c0a99166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005580c0a98e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f89a8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89a88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89a88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580c0a98d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (519 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso
# | ...
# `---data was truncated (10240/148012) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056383e00756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056383e004505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056383e007cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f089cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f089cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f089cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f089cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056383df9d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056383df9d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056383df81f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056383dc31166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056383dc30e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f089cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f089cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f089cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056383dc30d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (520 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate2_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %1, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d75571a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d755717505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d75571acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b3e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b3e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b3e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b3e0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7556b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7556b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d755694f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d755344166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d755343e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b3e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b3e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b3e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d755343d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm64_vcreate.c (521 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca i64, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store i64 %a1, ptr %a1.addr, align 8
# |   %0 = load i64, ptr %a1.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <2 x float>, ptr %__promote, align 8
# |   store <2 x float> %1, ptr %__ret, align 8
# |   %2 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %2, ptr %tmp, align 8
# |   %3 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b0ef5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559b0ef53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559b0ef56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dc0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dc0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dc0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dc0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b0eeec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559b0eeec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559b0eed0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559b0eb80166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559b0eb7fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4dc0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dc0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dc0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b0eb7fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c4d12756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c4d124505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c4d127cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab6da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab6daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab6da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab6da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c4d0bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c4d0bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c4d0a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c4cd51166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c4cd50e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab6da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab6da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab6da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c4cd50d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (523 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_s8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_s16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_s32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_s64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_u8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_u16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_u32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_u64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svundef_f16() #0 {
# | entry:
# |   ret <vscale x 8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svundef_f32() #0 {
# | entry:
# |   ret <vscale x 4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svundef_f64() #0 {
# | entry:
# |   ret <vscale x 2 x double> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_mf8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svundef_bf16() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> undef
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557bcadd556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557bcadd2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557bcadd5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd56fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd56fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd56fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd56fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bcad6b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557bcad6b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557bcad4ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557bca9ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557bca9fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd56fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd56fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd56fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bca9fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bc5fce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bc5fcb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bc5fcecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f642e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f642e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f642e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f642e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bc5f6423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bc5f64086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bc5f48f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bc5bf8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bc5bf7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f642e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f642e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f642e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bc5bf7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (525 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cd4623356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd46230505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd46233cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f586d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f586d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f586d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f586d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd461c923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd461c9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd461adf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd45e5d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd45e5ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f586d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f586d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f586d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd45e5cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (526 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005559efe5156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559efe4e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559efe51cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4651f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4651f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4651f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4651f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559efde723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559efde7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559efdcbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559efa7b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559efa7ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4651f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4651f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4651f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559efa7ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (527 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1q_gather_u64base_offset_f64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1q_gather_u64base_offset_f32(<vscale x 16 x i1> %pg, <vscale x 2 x
# | ...
# `---data was truncated (10240/58824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556d3b3a756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556d3b3a4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556d3b3a7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbf6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbf618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbf6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbf611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d3b33d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556d3b33d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556d3b321f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556d3afd1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556d3afd0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbbf611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbf611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbf611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d3afd0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (528 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 
# | ...
# `---data was truncated (10240/35980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055d17e7fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d17e7fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d17e7fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7301705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f730175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7301705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73016ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d17e79323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d17e793086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d17e777f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d17e427166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d17e426e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f73016eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73016ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73016ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d17e426d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (529 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055aa94fb856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aa94fb5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aa94fb8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9952933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f995298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9952933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f995291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa94f4e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aa94f4e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aa94f32f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aa94be2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aa94be1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f995291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f995291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f995291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa94be1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (530 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056125348f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056125348c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056125348fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f371c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f371c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f371c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f371c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056125342523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561253425086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561253409f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005612530b9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005612530b8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f371c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f371c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f371c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612530b8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056267255156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056267254e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562672551cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f104fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f104fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f104fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f104fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626724e723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005626724e7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005626724cbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056267217b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056267217ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f104fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f104fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f104fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056267217ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (532 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32mf8(<vscale x 4 x float> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005625b32e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625b32e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625b32e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5315c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5315ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5315c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5315c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625b327b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005625b327b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005625b325ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005625b2f0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005625b2f0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5315c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5315c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5315c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625b2f0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (533 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3b608d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c3b608a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c3b608dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37d0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37d00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37d0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37d0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3b602323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3b6023086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3b6007f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c3b5cb7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c3b5cb6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f37d0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37d00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37d00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3b5cb6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (534 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ba0c67156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba0c66e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba0c671cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6b7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6b758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6b7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6b751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba0c60723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba0c607086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba0c5ebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba0c29b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba0c29ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc6b751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6b751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6b751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba0c29ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (535 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svminnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svminnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svminnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555f5c01756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555f5c014505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555f5c017cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2261333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f226138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2261333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f226131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f5bfad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555f5bfad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555f5bf91f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555f5bc41166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555f5bc40e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f226131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f226131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f226131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f5bc40d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (536 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c436c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556c436c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556c436c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1e3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1e36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1e3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1e3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c4365b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556c4365b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556c4363ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556c432ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556c432eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff1e3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1e36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1e36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c432eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (537 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e00c91256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e00c90f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e00c912cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75ca21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75ca2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75ca21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75ca203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e00c8a823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e00c8a8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e00c88cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e00c53c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e00c53be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f75ca204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75ca2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75ca2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e00c53bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d0bf1b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d0bf18505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d0bf1bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ba8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ba8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ba8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ba8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d0beb123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d0beb1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d0be95f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d0bb45166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d0bb44e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ba8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ba8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ba8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d0bb44d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc7d9c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fc7d9c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fc7d9c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe81d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe81d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe81d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe81d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc7d95c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fc7d95c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fc7d940f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fc7d5f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fc7d5efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe81d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe81d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe81d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc7d5efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (540 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrts_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrts_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrts_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055d3d74c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d3d74c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d3d74c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13aac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13aaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13aac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13aac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3d745d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d3d745d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d3d7441f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d3d70f1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d3d70f0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13aac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13aac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13aac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3d70f0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %v
# | ...
# `---data was truncated (10240/142327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b85df656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b85df3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b85df6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf06f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf06f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf06f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf06f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b85d8c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b85d8c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b85d70f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b85a20166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b85a1fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcf06f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf06f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf06f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b85a1fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (542 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> noundef %a.coerce, <vscale x 8 x half> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x half>, align 16
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca <32 x half>, align 16
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %b.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store <32 x half> %b, ptr %b.addr, align 16
# |   %0 = load <32 x ha
# | ...
# `---data was truncated (10240/161192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055e2df56556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2df562505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2df565cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7049733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f704978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7049733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f704971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2df4fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2df4fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2df4dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2df18f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2df18ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f704971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f704971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f704971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2df18ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2b6f6256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d2b6f5f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d2b6f62cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86eec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86eec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86eec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86eec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2b6ef823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d2b6ef8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d2b6edcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2b6b8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2b6b8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f86eec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86eec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86eec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2b6b8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/getset.c (544 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <1 x i8>, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <1 x i8>, align 1
# |   %tmp = alloca <1 x i8>, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load <1 x i8>, ptr %ref.tmp, align 1
# |   store <1 x i8> %2, ptr %__ret, align 1
# |   %3 = load <1 x i8>, ptr %__ret, align 1
# |   store <1 x i8> %3, ptr %tmp, align 1
# |   %4 = load <1 x i8>, ptr %tmp, align 1
# |   ret <1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_847 = alloca half, align 2
# |   %__s0_847 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp1 = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %tmp2 = alloca half, align 2
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_847, align 8
# |   %1 = load <4 x i16>, ptr %__s0_847, align 8
# |   store <4 x i16> %1, ptr %__s0, align 8
# |   %2 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %2, i32 1
# |   store i16 %vget_lane, ptr %ref.tmp1, align 2
# |   %3 = load i16, ptr %ref.tmp1, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   store i16 %5, ptr %ref.tmp, align 2
# |   %6 = load half, ptr %ref.tmp, align 2
# |   store half %6, ptr %__ret_847, align 2
# |   %7 = load half, ptr %__ret_847, align 2
# |   store half %7, ptr %tmp2, align 2
# |   %8 = load half, ptr %tmp2, align 2
# |   %conv = fpext half %8 to float
# |   ret float %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %1, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %1, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align
# | ...
# `---data was truncated (10240/76998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ab0178356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab01780505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab01783cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8b3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8b318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8b3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8b311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab0171923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab01719086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab016fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab013ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab013ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8b311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8b311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8b311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab013acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (545 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c67a7056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c67a6d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c67a70cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c83049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c830a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c83049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c83031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c67a0623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c67a06086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c679eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c6769a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c67699e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6c83032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c830330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c830330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c67699d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab681d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab681d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab681d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb81d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb81d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb81d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb81d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab6816a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab6816a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab6814ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab67dfe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab67dfde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb81d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb81d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb81d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab67dfdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (547 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000561f19c9f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f19c9c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f19c9fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f310ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f310ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f310ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f310feed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f19c3523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f19c35086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f19c19f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f198c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f198c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f310feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f310feef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f310feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f198c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d5d23856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560d5d235505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560d5d238cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca28c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca28ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca28c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca28c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d5d1ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560d5d1ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560d5d1b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560d5ce62166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560d5ce61e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca28c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca28c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca28c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d5ce61d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (549 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/81756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056258e1c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056258e1c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056258e1c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f20933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f2098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f20933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f2091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056258e15d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056258e15d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056258e141f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056258ddf1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056258ddf0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f2091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f2091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f2091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056258ddf0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (550 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/246606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056360369556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563603692505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563603695cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9123a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9123aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9123a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9123a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056360362b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056360362b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056360360ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005636032bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005636032bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9123a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9123a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9123a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636032bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (551 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsa
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056530da1856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056530da15505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056530da18cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40eb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40eb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40eb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40eb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056530d9ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056530d9ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056530d992f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056530d642166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056530d641e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f40eb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40eb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40eb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056530d641d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (552 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639792aa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639792a7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639792aacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecb5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecb5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecb5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecb5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056397924023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563979240086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563979224f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563978ed4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563978ed3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fecb5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecb5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecb5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563978ed3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bbce1b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556bbce18505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556bbce1bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb218649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2186a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb218649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb218631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bbcdb123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556bbcdb1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556bbcd95f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556bbca45166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556bbca44e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb218632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2186330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2186330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bbca44d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (554 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055d57d03556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d57d032505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d57d035cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff142333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff14238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff142333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff14231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d57cfcb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d57cfcb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d57cfaff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d57cc5f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d57cc5ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff14231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff14231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff14231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d57cc5ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (555 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056151cb4556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056151cb42505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056151cb45cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87da333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87da38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87da333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87da31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056151cadb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056151cadb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056151cabff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056151c76f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056151c76ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87da31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87da31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87da31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056151c76ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (556 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison
# | ...
# `---data was truncated (10240/18569) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056518ab6056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056518ab5d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056518ab60cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe406649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4066a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe406649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe406631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056518aaf623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056518aaf6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056518aadaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056518a78a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056518a789e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe406632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4066330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4066330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056518a789d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (557 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <
# | ...
# `---data was truncated (10240/50724) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560074a4256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560074a3f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560074a42cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bc9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bc9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bc9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bc9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600749d823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600749d8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600749bcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056007466c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056007466be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5bc9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bc9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bc9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056007466bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (558 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560cb83e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560cb83e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560cb83e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f093881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09388725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f093881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0938803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cb837a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560cb837a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560cb835ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560cb800e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560cb800de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0938804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09388050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09388050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cb800dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (559 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd
# | ...
# `---data was truncated (10240/215044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f73e2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f73e29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f73e2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe94b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe94b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe94b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe94aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f73dc223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f73dc2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f73da6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f73a56166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f73a55e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbe94aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe94aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe94aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f73a55d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (560 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005597952cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005597952c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005597952cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85d3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85d3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85d3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85d3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055979526223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559795262086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559795246f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559794ef6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559794ef5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f85d3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85d3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85d3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559794ef5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e6f5d256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e6f5cf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e6f5d2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1196733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f119678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1196733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f119671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e6f56823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e6f568086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e6f54cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e6f1fc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e6f1fbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f119671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f119671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f119671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e6f1fbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm_acle_swp.c (562 of 27911)
******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7m-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret i32 %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eecaa3b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eecaa38505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eecaa3bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b07733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b0778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b07733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b0771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eeca9d123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eeca9d1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eeca9b5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eeca665166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eeca664e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b0771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b0771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b0771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eeca664d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (563 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1
# | ...
# `---data was truncated (10240/37926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005627e5ce056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005627e5cdd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005627e5ce0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d33049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d330a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d33049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d33031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627e5c7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627e5c76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005627e5c5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627e590a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627e5909e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d33032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d330330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d330330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627e5909d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (564 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564eefe7c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564eefe79505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564eefe7ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33a0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33a0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33a0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33a0eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eefe1223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564eefe12086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564eefdf6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564eefaa6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564eefaa5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f33a0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33a0eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33a0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eefaa5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1e9bfe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f1e9bfb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f1e9bfecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd905733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd90578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd905733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd90571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1e9b9423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f1e9b94086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f1e9b78f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f1e9828166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f1e9827e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd90571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd90571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd90571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1e9827d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (566 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svmov_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ec56d4556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ec56d42505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ec56d45cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaf3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaf358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaf3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaf351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec56cdb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ec56cdb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ec56cbff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ec5696f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ec5696ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feaf351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaf351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaf351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec5696ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d942ec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559d942e9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559d942eccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef3e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef3e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef3e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef3e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d9428223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559d94282086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559d94266f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559d93f16166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559d93f15e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef3e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef3e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef3e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d93f15d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055556439156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055556438e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555564391cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7b1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7b1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7b1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7b1aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055556432723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555564327086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055556430bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555563fbb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555563fbae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff7b1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7b1aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7b1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555563fbad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb7752056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eb7751d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eb77520cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f121cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f121cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f121cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f121cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb774b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eb774b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eb7749af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eb7714a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eb77149e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f121cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f121cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f121cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb77149d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fa69df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562fa69dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562fa69dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb952333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb95238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb952333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb95231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fa697523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562fa6975086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562fa6959f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562fa6609166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562fa6608e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb95231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb95231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb95231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fa6608d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (571 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 
# | ...
# `---data was truncated (10240/22890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650fd84056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005650fd83d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005650fd840cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb786f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb786f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb786f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb786f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650fd7d623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005650fd7d6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005650fd7baf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005650fd46a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005650fd469e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb786f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb786f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb786f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650fd469d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561607a6156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561607a5e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561607a61cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc60ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc60ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc60ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc60ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616079f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005616079f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005616079dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056160768b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056160768ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc60ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc60ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc60ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056160768ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f67ac456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f67ac1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f67ac4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2015533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f201558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2015533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f201551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f67a5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f67a5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f67a3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f676ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f676ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f201551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f201551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f201551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f676edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056342081b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563420818505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056342081bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d8d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d8d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d8d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d8d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634207b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634207b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563420795f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563420445166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563420444e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7d8d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d8d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d8d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563420444d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (575 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d2cd87456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d2cd871505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d2cd874cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3d1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3d12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3d1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3d1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2cd80a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d2cd80a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d2cd7eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2cd49e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2cd49de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc3d1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3d12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3d12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2cd49dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba43f0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba43eff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba43f02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3464933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3464933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba43e9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba43e98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba43e7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba43b2c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba43b2be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f346491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba43b2bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (577 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564783d1356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564783d10505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564783d13cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa430649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4306a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa430649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa430631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564783ca923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564783ca9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564783c8df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056478393d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056478393ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa430632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4306330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4306330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056478393cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (578 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055cf3ddbf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf3ddbc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf3ddbfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d8e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d8e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d8e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d8e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf3dd5523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf3dd55086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf3dd39f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf3d9e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf3d9e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d8e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d8e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d8e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf3d9e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e94194156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e94193e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e941941cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccb5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccb56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccb5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccb5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9418d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e9418d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9418bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e94156b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e94156ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fccb5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccb56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccb56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e94156ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a71b2956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a71b26505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a71b29cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4355d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4355d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4355d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4355d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a71abf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a71abf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a71aa3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a71753166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a71752e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4355d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4355d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4355d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a71752d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (581 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1>, ptr, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = getelementptr <vscale x 16 x i8>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_s32offset(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/16554) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005648669ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005648669ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005648669aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe91e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe91e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe91e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe91e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056486694423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564866944086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564866928f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005648665d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005648665d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe91e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe91e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe91e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648665d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc0536256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc0535f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc05362cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2af249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2af2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2af249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2af231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc052f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc052f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc052dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc04f8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc04f8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd2af232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2af2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2af2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc04f8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560790e5e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560790e5b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560790e5ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0ac449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0ac4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0ac449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0ac431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560790df423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560790df4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560790dd8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560790a88166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560790a87e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0ac432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0ac4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0ac4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560790a87d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591b92ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005591b92aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005591b92adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3420533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f342058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3420533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f342051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591b924323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005591b9243086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005591b9227f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005591b8ed7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005591b8ed6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f342051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f342051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f342051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591b8ed6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d5513e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d5513b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d5513ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9798333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f979838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9798333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f979831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d550d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d550d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d550b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d54d68166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d54d67e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f979831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f979831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f979831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d54d67d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (586 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571e201456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005571e2011505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005571e2014cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77eb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77eb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77eb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77eb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571e1faa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571e1faa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571e1f8ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571e1c3e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571e1c3de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f77eb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77eb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77eb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571e1c3dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 im
# | ...
# `---data was truncated (10240/78242) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562efd9f856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562efd9f5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562efd9f8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f91933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f9198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f91933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f9191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562efd98e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562efd98e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562efd972f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562efd622166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562efd621e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f9191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f9191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f9191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562efd621d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7c293a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d7c2937505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d7c293acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efea7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efea738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efea7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efea731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7c28d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7c28d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d7c28b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d7c2564166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d7c2563e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efea731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efea731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efea731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7c2563d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (589 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d1c89656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d1c893505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d1c896cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f165d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f165d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f165d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f165d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d1c82c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d1c82c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d1c810f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d1c4c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d1c4bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f165d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f165d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f165d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d1c4bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (590 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a86bd4a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a86bd47505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a86bd4acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ca0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ca055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ca0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ca04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a86bce023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a86bce0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a86bcc4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a86b974166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a86b973e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ca04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ca04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ca04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a86b973d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055906559c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559065599505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055906559ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f90d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f90d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f90d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f90d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055906553223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559065532086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559065516f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005590651c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005590651c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f90d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f90d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f90d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590651c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (592 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 8, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 9, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005606206a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606206a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606206a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97dbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97dbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97dbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97dbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056062063a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056062063a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056062061ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606202ce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606202cde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f97dbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97dbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97dbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606202cdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (593 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3a1dd056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b3a1dcd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b3a1dd0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee3e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee3e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee3e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee3e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3a1d6623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b3a1d66086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b3a1d4af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b3a19fa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b3a19f9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fee3e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee3e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee3e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3a19f9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (594 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/18925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a93675956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a936756505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a936759cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ae3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ae378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ae3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ae371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9366ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a9366ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a9366d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a936383166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a936382e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ae371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ae371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ae371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a936382d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (595 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559589bc156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559589bbe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559589bc1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ec5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ec56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ec5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ec5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559589b5723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559589b57086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559589b3bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005595897eb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005595897eae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ec5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ec56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ec56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595897ead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/addv.c (596 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svaddv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svaddv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svaddv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | a
# | ...
# `---data was truncated (10240/10826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055d525fa556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d525fa2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d525fa5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8730333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f873038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8730333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f873031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d525f3b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d525f3b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d525f1ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d525bcf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d525bcee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f873031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f873031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f873031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d525bced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (597 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx
# | ...
# `---data was truncated (10240/75125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055671833b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556718338505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055671833bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd4d905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd4d95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd4d905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd4d8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567182d123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005567182d1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005567182b5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556717f65166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556717f64e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd4d8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd4d8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd4d8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556717f64d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (598 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577a340656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005577a3403505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005577a3406cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8623e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8623ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8623e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8623e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577a339c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005577a339c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005577a3380f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005577a3030166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005577a302fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8623e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8623e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8623e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577a302fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (599 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055daf9f4c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055daf9f49505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055daf9f4ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f090f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f090f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f090f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f090f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daf9ee223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055daf9ee2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055daf9ec6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055daf9b76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055daf9b75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f090f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f090f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f090f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daf9b75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560baf9e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560baf9e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560baf9e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f380bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f380bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f380bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f380bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560baf97c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560baf97c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560baf960f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560baf610166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560baf60fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f380bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f380bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f380bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560baf60fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (601 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c220fc556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c220fc2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c220fc5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ebc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ebc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ebc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ebc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c220f5b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c220f5b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c220f3ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c220bef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c220beee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ebc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ebc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ebc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c220beed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (602 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <8 x i8>, al
# | ...
# `---data was truncated (10240/26059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000564bfd7b556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bfd7b2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bfd7b5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa144449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1444a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa144449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa144431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bfd74b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bfd74b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bfd72ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bfd3df166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bfd3dee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa144432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1444330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1444330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bfd3ded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648a68bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005648a68b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005648a68bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8373449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8373449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8373431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648a685223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005648a6852086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005648a6836f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005648a64e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005648a64e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8373432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83734330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648a64e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (604 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b083bfc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b083bf9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b083bfccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdefc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdefc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdefc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdefc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b083b9223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b083b92086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b083b76f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b083826166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b083825e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdefc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdefc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdefc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b083825d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ccd0bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ccd0b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ccd0bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc132d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc132d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc132d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc132d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ccd05223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ccd052086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ccd036f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559cccce6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559cccce5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc132d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc132d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc132d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cccce5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (606 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627c7e0156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005627c7dfe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005627c7e01cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ac5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ac5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ac5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ac5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627c7d9723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627c7d97086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005627c7d7bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627c7a2b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627c7a2ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ac5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ac5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ac5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627c7a2ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1da21e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a1da21b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a1da21ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaf701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaf70725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaf701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaf7003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1da1b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a1da1b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a1da198f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a1d9e48166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a1d9e47e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faaf7004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaf70050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaf70050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1d9e47d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/poly64.c (608 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none  -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %cmp.i = icmp eq <1 x i64> %2, %3
# |   %sext.i = sext <1 x i1> %cmp.i to <1 x i64>
# |   store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %cmp.i = icmp eq <2 x i64> %2, %3
# |   %sext.i = sext <2 x i1> %cmp.i to <2 x i64>
# |   store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %6 = and <1 x i64> %4, %5
# |   %7 = icmp ne <1 x i64> %6, zeroinitializer
# |   %vtst.i = sext <1 x i1> %7 to <1 x i64>
# |   store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8
# |   %8 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %8, ptr %__ret.i, align 8
# |   %9 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %6 = and <2 x i64> %4, %5
# |   %7 = icmp ne <2 x i64> %6, zeroinitializer
# |   %vtst.i = sext <2 x i1> %7 to <2 x i64>
# |   store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16
# |   %8 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %8, ptr %__ret.i, align 16
# |   %9 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_913 = alloca <1 x i64>, align 8
# |   %__s0_913 = alloca <1 x i64>, align 8
# |   %__s2_913 = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp3 = alloca <1 x i64>, align 8
# |   %tmp4 = alloca <1 x i64>, align 8
# |   %tmp5 = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0_913, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_913, align 8
# |   %2 = load <1 x i64>, ptr %__s2_913, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <1 x i64>, ptr %__s0_913, align 8
# |   store <1 x i64> %7, ptr %__s1, align 8
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <1 x i64>, ptr %__s1, align 8
# |   %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0
# |   store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <1 x i64>, ptr %ref.tmp3, align 8
# |   store <1 x i64> %10, ptr %__ret, align 8
# |   %11 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %11, ptr %tmp4, align 8
# |   %12 = load <1 x i64>, ptr %tmp4, align 8
# |   store <1 x i64> %12, ptr %__ret_913, align 8
# |   %13 = load <1 x i64>, ptr %__ret_913, align 8
# |   store <1 x i64> %13, ptr %tmp5, align 8
# |   %14 = load <1 x i64>, ptr %tmp5, align 8
# |   ret <1 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_909 = alloca <2 x i64>, align 16
# |   %__s0_909 = alloca <2 x i64>, align 16
# |   %__s2_909 = alloca <1 x i64>, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_909, align 16
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_909, align 8
# |   %2 = load <1 x i64>, ptr %__s2_909, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <2 x i64>, ptr %__s0_909, align 16
# |   store <2 x i64> %7, ptr %__s1, align 16
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <2 x i64>, ptr %__s1, align 16
# |   %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1
# |   store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <2 x i64>, ptr %ref.tmp3, align 16
# |   store <2 x i64> %10, ptr %__ret, align 16
# |   %11 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %11, ptr %tmp4, align 16
# |   %12 = load <2 x i64>, ptr %tmp4, align 16
# |   store <2 x i64> %12, ptr %__ret_909, align 16
# |   %13 = load <2 x i64>, ptr %__ret_909, align 16
# |   store <2 x i64> %13, ptr %tmp5, align 16
# |   %14 = load <2 x i64>, ptr %tmp5, align 16
# |   ret <2 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret_915 = alloca <2 x i64>, align 16
# |   %__s0_915 = alloca <2 x i64>, align 16
# |   %__s2_915 = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_915, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s2_915, align 16
# |   %2 = load <2 x i64>, ptr %__s2_915, align 16
# |   store <2 x i64> %2, ptr %__s02, align 16
# |   %3 = load <2 x i64>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <2 x i64> %3, i32 1
# |   store i64 %vgetq_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = 
# | ...
# `---data was truncated (10240/22456) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005586884b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005586884b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005586884b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe24d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe24d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe24d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe24d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055868844c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055868844c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558688430f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586880e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586880dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe24d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe24d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe24d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586880dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (609 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0
# | ...
# `---data was truncated (10240/39820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e4c06c156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4c06be505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4c06c1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f131fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f131fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f131fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f131fe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4c065723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4c0657086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4c063bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4c02eb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4c02eae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f131fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f131fe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f131fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4c02ead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (610 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamax_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svamax_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 0
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 1
# |   %10 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %8, <vscale x 4 x float> %9)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svamax_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm.coerce0, <vscale x 2 x double> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %zm.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 1
# |   %7 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 0
# |   %9 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 1
# |   %10 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double> %5, <vscale x 2 x double> %6, <vscale x 2 x double> %8, <vscale x 2 x double> %9)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamin_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8
# | ...
# `---data was truncated (10240/45703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f5e3e8456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f5e3e81505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f5e3e84cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1ec705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1ec75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1ec705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1ec6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5e3e1a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5e3e1a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5e3dfef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5e3aae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5e3aade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff1ec6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1ec6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1ec6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5e3aadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/79853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b0275e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b0275b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b0275ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc40a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc40a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc40a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc40a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b026f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b026f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b026d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b02388166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b02387e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc40a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc40a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc40a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b02387d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (612 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1ae08d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e1ae08a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e1ae08dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa47ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa47ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa47ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa47ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1ae02323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e1ae023086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1ae007f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e1adcb7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e1adcb6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa47ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa47ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa47ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1adcb6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, pt
# | ...
# `---data was truncated (10240/79679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562824faa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562824fa7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562824faacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e13733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e1378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e13733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e1371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562824f4023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562824f40086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562824f24f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562824bd4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562824bd3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3e1371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e1371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e1371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562824bd3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (614 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 
# | ...
# `---data was truncated (10240/98445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646fc41b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646fc418505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646fc41bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7500133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f750018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7500133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f750011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646fc3b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646fc3b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646fc395f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646fc045166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646fc044e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f750011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f750011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f750011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646fc044d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (615 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/77120) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056041037356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560410370505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560410373cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff651e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff651ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff651e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff651e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056041030923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560410309086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604102edf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056040ff9d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056040ff9ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff651e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff651e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff651e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056040ff9cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (616 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2, align 8
# |   %extract = extractelement <1 x double> %5, i32 0
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.fma.f64(double, double, double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <2 x double>, ptr %__s2, align 16
# |   %extract = extractelement <2 x double> %5, i32 1
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret_443 = alloca float, align 4
# |   %__s0_443 = alloca float, align 4
# |   %__s1_443 = alloca float, align 4
# |   %__s2_443 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_443, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1_443, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2_443, align 8
# |   %3 = load float, ptr %__s0_443, align 4
# |   store float %3, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1_443, align 4
# |   %fneg = fneg float %4
# |   store float %fneg, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2_443, align 8
# |   store <2 x float> %5, ptr %__s2, align 8
# |   %6 = load float, ptr %__s0, align 4
# |   %7 = load float, ptr %__s1, align 4
# |   %8 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %8, i32 1
# |   %9 = call float @llvm.fma.f32(float %7, float %extract, float %6)
# |   store float %9, ptr %ref.tmp, align 4
# |   %10 = load float, ptr %ref.tmp, align 4
# |   store float %10, ptr %__ret, align 4
# |   %11 = load float, ptr %__ret, align 4
# |   store float %11, ptr %tmp, align 4
# |   %12 = load float, ptr %tmp, align 4
# |   store float %12, ptr %__ret_443, align 4
# |   %13 = load float, ptr %__ret_443, align 4
# |   store float %13, ptr %tmp1, align 4
# |   %14 = load float, ptr %tmp1, align 4
# |   ret float %14
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.fma.f32(float, float, float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret_449 = alloca <1 x double>, align 8
# |   %__s0_449 = alloca <1 x double>, align 8
# |   %__s1_449 = alloca <1 x double>, align 8
# |   %__s2_449 = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   %tmp3 = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0_449, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_449, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2_449, align 8
# |   %3 = load <1 x double>, ptr %__s0_449, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s1_449, align 8
# |   %fneg = fneg <1 x double> %4
# |   store <1 x double> %fneg, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2_449, align 8
# |   store <1 x double> %5, ptr %__s2, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = load <8 x i8>, ptr %__s1, align 8
# |   %8 = load <8 x i8>, ptr %__s2, align 8
# |   %9 = bitcast <8 x i8> %8 to <1 x double>
# |   %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %7 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %6 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %10, ptr %__ret, align 8
# |   %11 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %11, ptr %tmp, align 8
# |   %12 = load <1 x double>, ptr %tmp, align 8
# |   store <1 x double> %12, ptr %__ret_449, align 8
# |   %13 = load <1 x double>, ptr %__ret_449, align 8
# |   store <1 x double> %13, ptr %tmp3, align 8
# |   %14 = load <1 x double>, ptr %tmp3, align 8
# |   ret <1 x double> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret_460 = alloca <1 x double>, align 8
# |   %__s0_460 = alloca <1 x double>, align 8
# |   %__s1_460 = alloca <1 x double>, align 8
# |   %__s2_460 = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %_
# | ...
# `---data was truncated (10240/12799) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005638ae51e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638ae51b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638ae51ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e60a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e60aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e60a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e60a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638ae4b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638ae4b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638ae498f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638ae148166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638ae147e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e60a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e60a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e60a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638ae147d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (617 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16  -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_812 = alloca <4 x float>, align 16
# |   %__s0_812 = alloca <4 x float>, align 16
# |   %__s1_812 = alloca <8 x bfloat>, align 16
# |   %__s2_812 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <4 x float>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp2 = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0_812, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1_812, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <8 x bfloat> %2, ptr %__s2_812, align 16
# |   %3 = load <4 x float>, ptr %__s0_812, align 16
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 16
# |   %5 = load <4 x float>, ptr %__s2_812, align 16
# |   store <4 x float> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 16
# |   store <4 x float> %8, ptr %__ret, align 16
# |   %9 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %9, ptr %tmp, align 16
# |   %10 = load <4 x float>, ptr %tmp, align 16
# |   store <4 x float> %10, ptr %ref.tmp, align 16
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %15, ptr %__ret.i, align 16
# |   %16 = load <4 x float>, ptr %__ret.i, align 16
# |   store <4 x float> %16, ptr %__ret_812, align 16
# |   %17 = load <4 x float>, ptr %__ret_812, align 16
# |   store <4 x float> %17, ptr %tmp2, align 16
# |   %18 = load <4 x float>, ptr %tmp2, align 16
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>,
# | ...
# `---data was truncated (10240/54685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005591097ab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005591097a8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005591097abcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055910974123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559109741086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559109725f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005591093d5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005591093d4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd9b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591093d4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c43741b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c437418505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c43741bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbd741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbd74725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbd741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbd7403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4373b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c4373b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c437395f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c437045166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c437044e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcbd7404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbd74050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbd74050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c437044d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (619 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/75656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055998f29856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055998f295505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055998f298cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9a3305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9a335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9a3305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9a32ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055998f22e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055998f22e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055998f212f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055998eec2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055998eec1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9a32eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9a32ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9a32ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055998eec1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561badc1756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561badc14505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561badc17cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa77b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa77b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa77b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa77b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561badbad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561badbad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561badb91f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561bad841166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561bad840e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa77b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa77b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa77b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bad840d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (621 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate3_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1, <vscale x 8 x half> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   %x2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x half> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vsc
# | ...
# `---data was truncated (10240/15704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005619f98d956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005619f98d6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005619f98d9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58c2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58c298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58c2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58c291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619f986f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005619f986f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005619f9853f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005619f9503166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005619f9502e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f58c291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58c291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58c291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619f9502d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (622 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 
# | ...
# `---data was truncated (10240/172384) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e7928d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7928d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7928d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb630649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6306a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb630649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb630631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e79286b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e79286b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e79284ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7924ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7924fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb630632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6306330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6306330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7924fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (623 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | declare void @g(<1 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_cst(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %vecext = extractelement <16 x i8> %0, i32 3
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# |  #0 0x0000562733ac956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562733ac6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562733ac9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83b2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83b2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83b2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83b2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562733a5f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562733a5f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562733a43f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627336f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627336f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f83b2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83b2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83b2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627336f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ef196956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558ef1966505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558ef1969cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd324449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd324449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd324431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ef18ff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558ef18ff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558ef18e3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558ef1593166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558ef1592e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd324432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3244330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ef1592d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3a4e0f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c3a4e0c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c3a4e0fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed33f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed33f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed33f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed33f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3a4da523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3a4da5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3a4d89f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c3a4a39166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c3a4a38e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fed33f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed33f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed33f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3a4a38d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (626 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc2333456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fc23331505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fc23334cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f387cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f387cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f387cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f387cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc232ca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fc232ca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fc232aef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fc22f5e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fc22f5de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f387cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f387cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f387cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc22f5dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (627 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056294965456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562949651505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562949654cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa248133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa24818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa248133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa24811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629495ea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005629495ea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005629495cef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056294927e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056294927de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa24811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa24811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa24811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056294927dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056234ad8656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056234ad83505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056234ad86cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab33a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab33a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab33a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab33a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056234ad1c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056234ad1c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056234ad00f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056234a9b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056234a9afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab33a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab33a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab33a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056234a9afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (629 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584e081f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005584e081c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005584e081fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52e671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584e07b523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005584e07b5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005584e0799f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005584e0449166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005584e0448e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f52e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52e671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584e0448d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (630 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a10784c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a107849505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a10784ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd89f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd89f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd89f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd89f0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1077e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a1077e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a1077c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a107476166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a107475e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd89f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd89f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd89f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a107475d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (631 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 7
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x float>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_vnum_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x double>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"
# | ...
# `---data was truncated (10240/10573) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055565174d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055565174a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055565174dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe431b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe431b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe431b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe431b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556516e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005556516e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005556516c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555651377166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555651376e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe431b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe431b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe431b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555651376d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (632 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, al
# | ...
# `---data was truncated (10240/223137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588873d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005588873d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005588873d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3dca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3dcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3dca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3dca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055888736a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055888736a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055888734ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558886ffe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558886ffde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb3dca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3dca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3dca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558886ffdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055565ace956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055565ace6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055565ace9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3177533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f317758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3177533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f317751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055565ac7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055565ac7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055565ac63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055565a913166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055565a912e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f317751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f317751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f317751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055565a912d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (634 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005640b1fef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640b1fec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640b1fefcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68f5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68f578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68f5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68f571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640b1f8523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640b1f85086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640b1f69f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640b1c19166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640b1c18e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f68f571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68f571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68f571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640b1c18d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (635 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/134736) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581fb19456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005581fb191505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005581fb194cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc70e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc70ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc70e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc70e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581fb12a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581fb12a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581fb10ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581fadbe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581fadbde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc70e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc70e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc70e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581fadbdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (636 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr
# | ...
# `---data was truncated (10240/26796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fcf26c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fcf26bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fcf26c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9464449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94644a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9464449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9464431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcf265823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fcf2658086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fcf263cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fcf22ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fcf22ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9464432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94644330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94644330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcf22ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (637 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = and <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = and <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = and <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = and <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb709d156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb709ce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb709d1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1869849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18698a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1869849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1869831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb7096723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb70967086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb7094bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb705fb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb705fae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1869832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18698330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18698330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb705fad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (638 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a75956256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a75955f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a759562cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f025cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f025cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f025cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f025cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7594f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a7594f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a7594dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a75918c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a75918be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f025cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f025cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f025cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a75918bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (639 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/150649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d685e4c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d685e49505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d685e4ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e05c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e05ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e05c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e05c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d685de223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d685de2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d685dc6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d685a76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d685a75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e05c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e05c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e05c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d685a75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (640 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ace68eb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ace68e8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ace68ebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff226649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff226649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff226631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ace688123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ace6881086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ace6865f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ace6515166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ace6514e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff226632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2266330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ace6514d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (641 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa579cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aa579c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aa579cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe675d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe675d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe675d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe675d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa5796123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aa57961086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aa57945f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aa575f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aa575f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe675d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe675d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe675d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa575f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (642 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ee265d256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee265cf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee265d2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4710449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47104a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4710449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4710431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee2656823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee26568086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee2654cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee261fc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee261fbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4710432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47104330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47104330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee261fbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %
# | ...
# `---data was truncated (10240/201226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dee3fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558dee3f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558dee3facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f4ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f4ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f4ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f4ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dee39023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558dee390086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558dee374f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558dee024166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558dee023e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f4ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f4ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f4ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dee023d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc9844d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc9844a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc9844dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31a851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc983e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc983e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc983c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc98077166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc98076e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f31a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31a851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc98076d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b487f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562b487ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562b487f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ca8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ca878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ca8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ca871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b4878723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562b48787086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562b4876bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562b4841b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562b4841ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ca871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ca871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ca871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b4841ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055652108456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556521081505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556521084cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc577105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc57715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc577105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5770ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055652101a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055652101a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556520ffef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556520cae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556520cade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc5770eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5770ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5770ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556520cadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/135345) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e085e856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564e085e5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564e085e8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8d3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8d3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8d3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8d3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e0857e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564e0857e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564e08562f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564e08212166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564e08211e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe8d3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8d3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8d3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e08211d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (648 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svld2_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm
# | ...
# `---data was truncated (10240/24404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560a895b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a895b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a895b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a8954e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a8954e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a89532f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a891e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a891e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87c011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a891e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (649 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6)
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <4 x float> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load <4 x float>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %10, ptr %__ret.i, align 16
# |   %11 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %c.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6)
# |   store <2 x double> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %10, ptr %__ret.i, align 16
# |   %11 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x float>
# |   %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> <i32 1, i32 1>
# |   %fmla = bitcast <8 x i8> %4 to <2 x float>
# |   %fmla1 = bitcast <8 x i8> %3 to <2 x float>
# |   %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1)
# |   store <2 x float> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/80179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c6c3aec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c6c3ae9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c6c3aeccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9447f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9447f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9447f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9447f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6c3a8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c6c3a82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c6c3a66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c6c3716166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c6c3715e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9447f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9447f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9447f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6c3715d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (650 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i
# | ...
# `---data was truncated (10240/23350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055ebed78856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ebed785505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ebed788cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0923c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0923ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0923c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0923c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebed71e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ebed71e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ebed702f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ebed3b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ebed3b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0923c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0923c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0923c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebed3b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (651 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056174910e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056174910b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056174910ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1910733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f191078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1910733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f191071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617490a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005617490a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561749088f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561748d38166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561748d37e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f191071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f191071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f191071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561748d37d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (652 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558ac6b3956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558ac6b36505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558ac6b39cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe275c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe275ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe275c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe275c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ac6acf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558ac6acf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558ac6ab3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558ac6763166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558ac6762e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe275c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe275c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe275c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ac6762d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (653 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svadda_f16(<vscale x 16 x i1> %pg, half noundef %initial, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca half, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store half %initial, ptr %initial.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load half, ptr %initial.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1> %3, half %1, <vscale x 8 x half> %2)
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1>, half, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svadda_f32(<vscale x 16 x i1> %pg, float noundef %initial, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca float, align 4
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store float %initial, ptr %initial.addr, align 4
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load float, ptr %initial.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1> %3, float %1, <vscale x 4 x float> %2)
# |   ret float %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1>, float, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svadda_f64(<vscale x 16 x i1> %pg, double noundef %initial, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca double, align 8
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store double %initial, ptr %initial.addr, align 8
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load double, ptr %initial.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %3, double %1, <vscale x 2 x double> %2)
# |   ret double %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cba681456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cba6811505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cba6814cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9136e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9136ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9136e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9136e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cba67aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cba67aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cba678ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cba643e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cba643de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9136e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9136e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9136e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cba643dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (654 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/424041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056191fbbf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056191fbbc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056191fbbfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25f5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25f538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25f5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25f531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056191fb5523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056191fb55086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056191fb39f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056191f7e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056191f7e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f25f531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25f531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25f531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056191f7e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (655 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x float>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_f64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x double> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %zt, ptr %zt.addr
# | ...
# `---data was truncated (10240/12466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005582aef5456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005582aef51505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005582aef54cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f366b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f366b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f366b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f366b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582aeeea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582aeeea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582aeecef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582aeb7e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582aeb7de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f366b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f366b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f366b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582aeb7dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055658d50856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055658d505505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055658d508cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe6ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe6eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe6ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe6ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055658d49e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055658d49e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055658d482f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055658d132166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055658d131e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbe6ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe6ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe6ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055658d131d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be6920e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be6920b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be6920ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58f8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58f898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58f8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58f891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be691a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be691a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be69188f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be68e38166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be68e37e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f58f891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58f891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58f891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be68e37d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (658 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cb0d7a856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb0d7a5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb0d7a8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc50449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc50449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc50431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb0d73e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb0d73e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb0d722f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb0d3d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb0d3d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc50432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb0d3d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (659 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595d823c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005595d8239505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005595d823ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa107b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa107b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa107b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa107aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595d81d223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005595d81d2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005595d81b6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005595d7e66166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005595d7e65e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa107aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa107aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa107aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595d7e65d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (660 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e487e5956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e487e56505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e487e59cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30d1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30d10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30d1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30d1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e487def23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e487def086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e487dd3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e487a83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e487a82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f30d1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30d10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30d10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e487a82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (661 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsca
# | ...
# `---data was truncated (10240/24214) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b797ce656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b797ce3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b797ce6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc10c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc10ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc10c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc10c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b797c7c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b797c7c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b797c60f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b797910166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b79790fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc10c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc10c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc10c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b79790fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (662 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588af83e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005588af83b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005588af83ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1ed21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1ed2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1ed21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1ed203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588af7d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005588af7d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005588af7b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005588af468166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005588af467e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff1ed204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1ed2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1ed2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588af467d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561af2bba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561af2bb7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561af2bbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f939bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f939bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f939bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f939bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561af2b5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561af2b50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561af2b34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561af27e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561af27e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f939bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f939bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f939bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561af27e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (664 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8e64a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e8e649f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e8e64a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f438dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f438dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f438dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f438dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8e643823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e8e6438086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8e641cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e8e60cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e8e60cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f438dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f438dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f438dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8e60cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6d1bd756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6d1bd4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6d1bd7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4ef01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4ef0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4ef01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4ef003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6d1b6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6d1b6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6d1b51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6d1801166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6d1800e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb4ef004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4ef0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4ef0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6d1800d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (666 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone   -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %add.i = fadd <4 x float> %2, %3
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %sub.i = fsub <2 x float> %2, %3
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <4 x float> %2, %3
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <2 x double> %2, %3
# |   store <2 x double> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <4 x float> %2, %3
# |   store <4 x float> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <2 x double> %2, %3
# |   store <2 x double> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   %v3.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   store <2 x float> %v3, ptr %v3.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   %2 = load <2 x float>, ptr %v3.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x float>, ptr %__p2.addr.i, align 8
# |   %mul.i = fmul <2 x float> %4, %5
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %6 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   %v3.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   store <4 x float> %v3, ptr %v3.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   %2 = load <4 x float>, ptr %v3.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load <4 x float>, ptr %__p2.addr.i, align 16
# |   %mul.i = fmul <4 x float> %4, %5
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/91378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c555bfe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c555bfb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c555bfecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b1e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b1e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b1e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b1e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c555b9423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c555b94086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c555b78f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c555828166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c555827e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b1e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b1e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b1e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c555827d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (667 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvtn_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt1_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt2_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr
# | ...
# `---data was truncated (10240/17058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d32efbd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d32efba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d32efbdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4383533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f438358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4383533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f438351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d32ef5323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d32ef53086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d32ef37f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d32ebe7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d32ebe6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f438351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f438351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f438351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d32ebe6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-neon-endianness.c (668 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-arm-none-eabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 2
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 3
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 1
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# |  #0 0x000055923dd6956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055923dd66505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055923dd69cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37d1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37d1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37d1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37d1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055923dcff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055923dcff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055923dce3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055923d993166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055923d992e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f37d1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37d1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37d1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055923d992d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628f2e4756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005628f2e44505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005628f2e47cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb21d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb21d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb21d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb21d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628f2ddd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005628f2ddd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005628f2dc1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005628f2a71166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005628f2a70e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb21d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb21d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb21d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628f2a70d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055885fbeb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055885fbe8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055885fbebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13ddd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13ddd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13ddd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13ddd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055885fb8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055885fb81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055885fb65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055885f815166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055885f814e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13ddd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13ddd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13ddd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055885f814d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f40cff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f40cfc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f40cffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb92f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb92f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb92f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb92f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f40c9523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f40c95086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f40c79f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f40929166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f40928e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feb92f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb92f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb92f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f40928d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cef70156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cef6fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cef701cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3564333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f356438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3564333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f356431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cef69723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cef697086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cef67bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cef32b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cef32ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f356431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f356431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f356431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cef32ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/78164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cdc70756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558cdc704505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558cdc707cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84fef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84fef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84fef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84fef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cdc69d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558cdc69d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558cdc681f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558cdc331166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558cdc330e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84fef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84fef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84fef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cdc330d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056211131356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562111310505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562111313cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52f7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52f74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52f7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52f7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621112a923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005621112a9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056211128df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562110f3d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562110f3ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f52f7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52f74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52f74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562110f3cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (675 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d9594d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d9594a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d9594dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3908f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3908f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3908f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3908f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d958e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d958e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d958c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d95577166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d95576e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3908f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3908f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3908f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d95576d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b3338256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562b3337f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562b33382cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc299c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc299ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc299c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc299c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b3331823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562b33318086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562b332fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562b32fac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562b32fabe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc299c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc299c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc299c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b32fabd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056535d3c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056535d3c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056535d3c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1f1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1f158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1f1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1f151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056535d35d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056535d35d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056535d341f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056535cff1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056535cff0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc1f151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1f151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1f151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056535cff0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/71955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e13eb856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563e13eb5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563e13eb8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febf8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febf84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febf8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febf8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e13e4e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563e13e4e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563e13e32f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563e13ae2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563e13ae1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007febf8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febf84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febf84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e13ae1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056354e81756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056354e814505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056354e817cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f692ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f692eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f692ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f692ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056354e7ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056354e7ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056354e791f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056354e441166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056354e440e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f692ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f692ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f692ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056354e440d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (680 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f501f8056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f501f7d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f501f80cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0ddb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0ddb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0ddb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0ddb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f501f1623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f501f16086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f501efaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f501baa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f501ba9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0ddb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0ddb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0ddb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f501ba9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/273705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056120b56e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056120b56b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056120b56ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7164733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f716478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7164733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f716471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056120b50423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056120b504086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056120b4e8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056120b198166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056120b197e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f716471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f716471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f716471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056120b197d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (682 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c0e2b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557c0e2b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557c0e2b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03fa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03fa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03fa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03fa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c0e24c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557c0e24c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557c0e230f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557c0dee0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557c0dedfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03fa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03fa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03fa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c0dedfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579a9cc956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579a9cc6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579a9cc9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff36c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff36c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff36c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff36c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579a9c5f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579a9c5f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579a9c43f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579a98f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579a98f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff36c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff36c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff36c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579a98f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (684 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e396d2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e396d27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e396d2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3950f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3950f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3950f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3950f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e396cc023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e396cc0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e396ca4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e396954166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e396953e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3950f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3950f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3950f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e396953d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (685 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpa_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005615e3c1556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615e3c12505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615e3c15cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f604561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60456725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f604561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6045603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615e3bab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615e3bab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615e3b8ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615e383f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615e383ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6045604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60456050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60456050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615e383ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b9a81956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b9a816505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b9a819cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb55de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb55dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb55de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb55de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b9a7af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b9a7af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b9a793f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b9a443166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b9a442e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb55de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb55de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb55de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b9a442d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056384d9cd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056384d9ca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056384d9cdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06a4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06a495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06a4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06a48ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056384d96323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056384d963086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056384d947f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056384d5f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056384d5f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f06a48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06a48ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06a48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056384d5f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %v
# | ...
# `---data was truncated (10240/110062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f19c5d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f19c5d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f19c5d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb37ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb37aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb37ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb37ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f19c56e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f19c56e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f19c552f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f19c202166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f19c201e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb37ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb37ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb37ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f19c201d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbb11c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cbb11c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cbb11c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf3c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf3c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf3c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf3c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbb115923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cbb1159086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cbb113df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cbb0ded166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cbb0dece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faf3c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf3c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf3c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbb0decd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (690 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #4
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64
# | ...
# `---data was truncated (10240/21923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000562b525bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562b525b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562b525bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb80d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb80d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb80d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb80d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b5255223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562b52552086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562b52536f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562b521e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562b521e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb80d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb80d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb80d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b521e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (691 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x00005575e742056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005575e741d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005575e7420cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd893533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd89358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd893533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd89351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575e73b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005575e73b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005575e739af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005575e704a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005575e7049e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd89351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd89351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd89351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575e7049d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (692 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559879b8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559879b84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559879b87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd28cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd28cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd28cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd28cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559879b1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559879b1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559879b01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005598797b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005598797b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd28cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd28cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd28cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598797b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/83088) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633c87ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633c87ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633c87edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafbd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafbd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafbd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafbd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633c878323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005633c8783086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005633c8767f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005633c8417166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005633c8416e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fafbd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafbd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafbd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633c8416d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (694 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svldr_zt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svstr_zt(ptr noundef %base) #2 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) }
# | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559f2ff8c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f2ff89505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f2ff8ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4e8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4e84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4e8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4e8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f2ff2223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f2ff22086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f2ff06f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f2fbb6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f2fbb5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc4e8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4e84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4e84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f2fbb5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/72493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bec031156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bec030e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bec0311cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ebf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bec02a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bec02a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bec028bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bebff3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bebff3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f83ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bebff3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641acda156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005641acd9e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005641acda1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda50849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda50849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda50831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641acd3723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005641acd37086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005641acd1bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005641ac9cb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005641ac9cae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda50832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda508330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641ac9cad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055826f30556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055826f302505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055826f305cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2762733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f276278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2762733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f276271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055826f29b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055826f29b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055826f27ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055826ef2f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055826ef2ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f276271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f276271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f276271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055826ef2ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (698 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ff83c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560ff83c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560ff83c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9e6e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9e6e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9e6e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9e6e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ff835c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560ff835c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560ff8340f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560ff7ff0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560ff7fefe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9e6e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9e6e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9e6e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ff7fefd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056343e43456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056343e431505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056343e434cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc22ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc22ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056343e3ca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056343e3ca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056343e3aef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056343e05e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056343e05de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc22ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056343e05dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (700 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565077b4e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565077b4b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565077b4ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2514333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f251438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2514333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f251431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565077ae423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565077ae4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565077ac8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565077778166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565077777e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f251431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f251431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f251431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565077777d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <
# | ...
# `---data was truncated (10240/117389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627cbe9556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005627cbe92505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005627cbe95cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d77933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d7798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d77933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d7791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627cbe2b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627cbe2b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005627cbe0ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627cbabf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627cbabee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d7791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d7791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d7791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627cbabed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4f65af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a4f65ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a4f65afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23f0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23f038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23f0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23f031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4f654523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a4f6545086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a4f6529f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a4f61d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a4f61d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f23f031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23f031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23f031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4f61d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (703 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx
# | ...
# `---data was truncated (10240/78682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea7d11a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea7d117505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea7d11acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9a9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9a9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9a9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9a9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea7d0b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea7d0b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea7d094f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea7cd44166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea7cd43e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9a9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9a9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9a9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea7cd43d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (704 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/12431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac15c8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac15c84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac15c87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff64521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6452725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff64521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff645203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac15c1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac15c1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac15c01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac158b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac158b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff645204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6452050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6452050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac158b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (705 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055814745256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055814744f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558147452cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4971533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f497158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4971533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f497151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581473e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581473e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581473ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055814707c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055814707be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f497151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f497151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f497151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055814707bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcreate_v_f16m1_f16m2(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %3 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %2, <vscale x 4 x half> %1, i64 4)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m1_f16m4(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %5 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %4, <vscale x 4 x half> %1, i64 4)
# |   %6 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %5, <vscale x 4 x half> %2, i64 8)
# |   %7 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %6, <vscale x 4 x half> %3, i64 12)
# |   ret <vscale x 16 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m1_f16m8(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   %v4.addr = alloca <vscale x 4 x half>, align 2
# |   %v5.addr = alloca <vscale x 4 x half>, align 2
# |   %v6.addr = alloca <vscale x 4 x half>, align 2
# |   %v7.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x half> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x half> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x half> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x half> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x half>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x half>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x half>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x half>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %9 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %8, <vscale x 4 x half> %1, i64 4)
# |   %10 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %9, <vscale x 4 x half> %2, i64 8)
# |   %11 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %10, <vscale x 4 x half> %3, i64 12)
# |   %12 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %11, <vscale x 4 x half> %4, i64 16)
# |   %13 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %12, <vscale x 4 x half> %5, i64 20)
# |   %14 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %13, <vscale x 4 x half> %6, i64 24)
# |   %15 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %14, <vscale x 4 x half> %7, i64 28)
# |   ret <vscale x 32 x half> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m2_f16m4(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %3 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %2, <vscale x 8 x half> %1, i64 8)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m2_f16m8(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   %v2.addr = alloca <vscale x 8 x half>, align 2
# |   %v3.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %5 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %4, <vscale x 8 x half> %1, i64 8)
# |   %6 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %5, <vscale x 8 x half> %2, i64 16)
# |   %7 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %6, <vscale x 8 x half> %3, i64 24)
# |   ret <vscale x 32 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m4_f16m8(<vscale x 16 x half> %v0, <vscale x 16 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x half>, align 2
# |   %v1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> %0, i64 0)
# |   %3 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %2, <vscale x 16 x half> %1, i64 16)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcreate_v_f32m1_f32m2(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 2 x float>, align 4
# |   %v1.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %v0, ptr %v0.addr, align 4
# |   store <vscale x 2 x float> %v1, ptr %v1.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %v0.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %v1.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> %0, i64 0)
# |   %3 = call <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/593252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d70591a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d705917505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d70591acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65d6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65d60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65d6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65d6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7058b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7058b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d705894f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d705544166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d705543e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f65d6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65d60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65d60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d705543d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646e5e0f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646e5e0c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646e5e0fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36a9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36a9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36a9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36a9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646e5da523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646e5da5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646e5d89f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646e5a39166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646e5a38e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f36a9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36a9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36a9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646e5a38d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae19f1e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae19f1b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae19f1ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e4d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e4d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e4d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e4d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae19eb423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae19eb4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae19e98f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae19b48166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae19b47e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e4d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e4d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e4d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae19b47d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/thinlto_backend.ll (709 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# |  #0 0x000055a99889456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a998891505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a998894cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f300f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f300f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f300f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f300f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a99882a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a99882a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a99880ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a9984be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a9984bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f300f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f300f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f300f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9984bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e68d3fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e68d3fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e68d3fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f318ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f318ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f318ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f318ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e68d39423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e68d394086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e68d378f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e68d028166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e68d027e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f318ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f318ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f318ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e68d027d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (711 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577968ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005577968eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005577968eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e47649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e476a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e47649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e47631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055779688423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557796884086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557796868f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557796518166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557796517e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e47632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e476330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e476330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557796517d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f12d43e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f12d43b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f12d43ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f626a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f626a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f626a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f626a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f12d3d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f12d3d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f12d3b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f12d068166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f12d067e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f626a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f626a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f626a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f12d067d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564fb6c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005564fb6c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005564fb6c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe640105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe64015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe640105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6400ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564fb65923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005564fb659086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005564fb63df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005564fb2ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005564fb2ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe6400eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6400ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6400ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564fb2ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/nand.c (714 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnand_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000562789d8856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562789d85505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562789d88cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38e3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38e3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38e3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38e3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562789d1e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562789d1e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562789d02f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627899b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627899b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f38e3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38e3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38e3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627899b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fea56d056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fea56cd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fea56d0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64a0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64a02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64a0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64a0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fea566623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fea5666086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fea564af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fea52fa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fea52f9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f64a0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64a02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64a02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fea52f9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsm
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056238a4b356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056238a4b0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056238a4b3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe02f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe02f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe02f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe02f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056238a44923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056238a449086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056238a42df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056238a0dd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056238a0dce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe02f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe02f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe02f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056238a0dcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578e058656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578e0583505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578e0586cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b8ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b8eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b8ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b8ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578e051c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578e051c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578e0500f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578e01b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578e01afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7b8ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b8ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b8ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578e01afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale
# | ...
# `---data was truncated (10240/79489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f0f61c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f0f619505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f0f61ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2566049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2566049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2566031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f0f5b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f0f5b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f0f596f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f0f246166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f0f245e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2566032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25660330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f0f245d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bab42956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bab426505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bab429cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb52f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb52f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb52f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb52f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bab3bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bab3bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bab3a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bab053166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bab052e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb52f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb52f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb52f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bab052d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (720 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpklo_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e371dc056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e371dbd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e371dc0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6007933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f600798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6007933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f600791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e371d5623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e371d56086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e371d3af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e3719ea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e3719e9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f600791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f600791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f600791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3719e9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv
# | ...
# `---data was truncated (10240/255166) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595d338856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005595d3385505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005595d3388cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedc0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedc018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedc0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedc011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595d331e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005595d331e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005595d3302f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005595d2fb2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005595d2fb1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fedc011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedc011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedc011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595d2fb1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8ef25956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f8ef256505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f8ef259cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb5fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb5fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb5fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb5fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8ef1ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f8ef1ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f8ef1d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f8eee83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f8eee82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb5fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb5fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb5fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8eee82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (723 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056139bf2156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056139bf1e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056139bf21cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39e1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39e1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39e1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39e1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056139beb723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056139beb7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056139be9bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056139bb4b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056139bb4ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f39e1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39e1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39e1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056139bb4ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple,
# | ...
# `---data was truncated (10240/27986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578bd05f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578bd05c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578bd05fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47f6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47f655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47f6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47f64ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578bcff523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578bcff5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578bcfd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578bcc89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578bcc88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47f64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47f64ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47f64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578bcc88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (725 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> <i32 1>
# |   store <1 x double> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/20383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574275d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005574275d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005574275d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d18133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d1818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d18133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d1811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055742756d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055742756d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557427551f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557427201166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557427200e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d1811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d1811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d1811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557427200d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (726 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.
# | ...
# `---data was truncated (10240/78690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650214c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005650214c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005650214c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa470649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4706a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa470649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa470631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056502145d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056502145d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565021441f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005650210f1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005650210f0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa470632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4706330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4706330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650210f0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (727 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558aca08456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558aca081505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558aca084cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ca2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ca2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ca2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ca2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aca01a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558aca01a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558ac9ffef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558ac9cae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558ac9cade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0ca2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ca2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ca2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ac9cadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7a4da156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d7a4d9e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d7a4da1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdf2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdf22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdf2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdf2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7a4d3723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7a4d37086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d7a4d1bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d7a49cb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d7a49cae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcdf2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdf22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdf22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7a49cad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (729 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae8e1a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae8e1a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae8e1a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f368ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f368eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f368ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f368ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae8e13a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae8e13a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae8e11ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae8ddce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae8ddcde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f368ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f368ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f368ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae8ddcdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7943ec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f7943e9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f7943eccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81b3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81b338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81b3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81b331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f79438223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f794382086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f794366f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f794016166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f794015e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f81b331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81b331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81b331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f794015d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (731 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602d0f4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005602d0f43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005602d0f46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f516dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f516dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f516dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f516dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602d0edc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005602d0edc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005602d0ec0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005602d0b70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005602d0b6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f516dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f516dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f516dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602d0b6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591dba8e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005591dba8b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005591dba8ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb640c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb640ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb640c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb640c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591dba2423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005591dba24086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005591dba08f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005591db6b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005591db6b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb640c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb640c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb640c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591db6b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055beb9af956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055beb9af6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055beb9af9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9bf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9bf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9bf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9bf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055beb9a8f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055beb9a8f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055beb9a73f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055beb9723166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055beb9722e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd9bf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9bf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9bf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055beb9722d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/124506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564de4ede56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564de4edb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564de4edecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc55361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5536725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc55361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc553603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564de4e7423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564de4e74086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564de4e58f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564de4b08166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564de4b07e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc553604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5536050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5536050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564de4b07d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (735 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local half @subscript_float16(<vscale x 8 x half> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 4 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %a.coerce, i64 0)
# |   store <16 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 2 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> %a.coerce, i64 0)
# |   store <8 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056184974f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056184974c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056184974fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cb4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cb44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cb4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cb4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618496e523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005618496e5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005618496c9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561849379166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561849378e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1cb4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cb44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cb44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561849378d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d19db6256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d19db5f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d19db62cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7624a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7624a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7624a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7624a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d19daf823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d19daf8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d19dadcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d19d78c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d19d78be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7624a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7624a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7624a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d19d78bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba325356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fba3250505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fba3253cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f134bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f134bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f134bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f134bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba31e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fba31e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fba31cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fba2e7d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fba2e7ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f134bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f134bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f134bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba2e7cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (738 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056389c17456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056389c171505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056389c174cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f545e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f545e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f545e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f545e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056389c10a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056389c10a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056389c0eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056389bd9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056389bd9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f545e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f545e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f545e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056389bd9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (739 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e2d09a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e2d097505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e2d09acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde7a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde7a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde7a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde7a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e2d03023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e2d030086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e2d014f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e2ccc4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e2ccc3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde7a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde7a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde7a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e2ccc3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/33764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9684d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9684d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9684d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc25733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc2578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc25733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc2571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f96846d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f96846d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f968451f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f968101166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f968100e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc2571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc2571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc2571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f968100d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594ca77756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005594ca774505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005594ca777cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72c1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72c14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72c1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72c1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594ca70d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594ca70d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005594ca6f1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005594ca3a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005594ca3a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72c1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72c14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72c14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594ca3a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (742 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648e14f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005648e14f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005648e14f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb91fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb91faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb91fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb91fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648e148923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005648e1489086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005648e146df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005648e111d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005648e111ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb91fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb91fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb91fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648e111cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e88afa956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e88afa6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e88afa9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03a0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03a00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03a0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03a0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e88af3f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e88af3f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e88af23f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e88abd3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e88abd2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03a0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03a00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03a00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e88abd2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e8079f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e8079c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e8079fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f3181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f318725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f3181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f31803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e8073523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e80735086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e80719f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e803c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e803c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f31804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f318050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f318050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e803c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f75fcc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f75fc9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f75fcccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a25449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a254a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a25449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a25431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f75f6223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f75f62086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f75f46f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f75bf6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f75bf5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7a25432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a254330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a254330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f75bf5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (746 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555bcca4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555bcca40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555bcca43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6489933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f648998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6489933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f648991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bcc9d923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555bcc9d9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555bcc9bdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555bcc66d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555bcc66ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f648991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f648991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f648991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bcc66cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (747 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005567b8ed856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005567b8ed5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005567b8ed8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ed1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ed138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ed1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ed131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567b8e6e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005567b8e6e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005567b8e52f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005567b8b02166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005567b8b01e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ed131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ed131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ed131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567b8b01d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (748 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d0edef456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d0edef1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d0edef4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd851a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd851a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd851a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd851a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0ede8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d0ede8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d0ede6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d0edb1e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d0edb1de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd851a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd851a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd851a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0edb1dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (749 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_scatter_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16> %3, <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) #
# | ...
# `---data was truncated (10240/43213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055760884756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557608844505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557608847cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4020f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4020f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4020f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4020f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576087dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576087dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576087c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557608471166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557608470e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4020f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4020f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4020f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557608470d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c31465556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c314652505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c314655cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a65133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a6518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a65133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a6511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3145eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3145eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3145cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c31427f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c31427ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a6511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a6511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a6511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c31427ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (751 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpe_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpe_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpe_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000056502e20956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056502e206505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056502e209cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c42933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c4298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c42933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c4291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056502e19f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056502e19f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056502e183f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056502de33166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056502de32e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c4291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c4291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c4291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056502de32d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (752 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/68141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbfef3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bbfef2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bbfef31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c72733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c7278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c72733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c7271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbfeec723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bbfeec7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bbfeeabf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bbfeb5b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bbfeb5ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2c7271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c7271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c7271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbfeb5ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d277dcb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d277dc8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d277dcbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5020d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5020d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5020d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5020d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d277d6123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d277d61086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d277d45f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2779f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2779f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5020d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5020d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5020d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2779f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (754 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 2, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 3, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005617a1d0456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005617a1d01505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005617a1d04cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87a0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87a038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87a0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87a031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617a1c9a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005617a1c9a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005617a1c7ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005617a192e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005617a192de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87a031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87a031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87a031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617a192dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e35dd5756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e35dd54505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e35dd57cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cf401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cf40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cf401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cf4003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e35dced23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e35dced086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e35dcd1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e35d981166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e35d980e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8cf4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cf40050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cf40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e35d980d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd9a8af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dd9a8ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dd9a8afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e24c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e24ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e24c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e24c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd9a84523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dd9a845086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dd9a829f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dd9a4d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dd9a4d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3e24c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e24c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e24c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd9a4d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (757 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d23418456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d234181505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d234184cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e83533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e8358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e83533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e8351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d23411a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d23411a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d2340fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d233dae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d233dade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e8351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e8351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e8351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d233dadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c443b0956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c443b06505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c443b09cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7003305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f700335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7003305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70032ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c443a9f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c443a9f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c443a83f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c443733166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c443732e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f70032eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70032ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70032ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c443732d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (759 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055884b06256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055884b05f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055884b062cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9604533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f960458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9604533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f960451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055884aff823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055884aff8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055884afdcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055884ac8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055884ac8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f960451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f960451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f960451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055884ac8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558189c7856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558189c75505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558189c78cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb35533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb3558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb35533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb3551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558189c0e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558189c0e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558189bf2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581898a2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581898a1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb3551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb3551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb3551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581898a1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f463b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f463b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f463b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b83649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b836a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b83649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b83631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f4634d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f4634d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f46331f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f45fe1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f45fe0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b83632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b836330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b836330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f45fe0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6eef3856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d6eef35505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d6eef38cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f85e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f85ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f85e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f85e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6eeece23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d6eeece086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d6eeeb2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d6eeb62166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d6eeb61e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f85e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f85e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f85e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6eeb61d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/43507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055971e9be56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055971e9bb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055971e9becab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12de733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12de78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12de733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12de71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055971e95423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055971e954086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055971e938f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055971e5e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055971e5e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f12de71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12de71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12de71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055971e5e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (764 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/46416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055edd7e3456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055edd7e31505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055edd7e34cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8522449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85224a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8522449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8522431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edd7dca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055edd7dca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055edd7daef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055edd7a5e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055edd7a5de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8522432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85224330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85224330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edd7a5dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a84150856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a841505505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a841508cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1efb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1efb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1efb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1efb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a84149e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a84149e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a841482f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a841132166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a841131e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff1efb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1efb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1efb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a841131d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056279cd4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056279cd4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056279cd4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e6fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e6faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e6fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e6fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056279cce523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056279cce5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056279ccc9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056279c979166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056279c978e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3e6fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e6fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e6fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056279c978d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x h
# | ...
# `---data was truncated (10240/69487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e1519f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e1519c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e1519fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5eb0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5eb038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5eb0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5eb031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e1513523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e15135086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e15119f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e14dc9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e14dc8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5eb031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5eb031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5eb031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e14dc8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cdbcea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cdbce7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cdbceacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6af261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6af26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6af261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6af2603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cdbc8023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cdbc80086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cdbc64f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cdb914166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cdb913e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6af2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6af26050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6af26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cdb913d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (769 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fe804be56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fe804bb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fe804becab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e6bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e6bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e6bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e6bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe8045423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fe80454086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fe80438f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fe800e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fe800e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e6bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e6bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e6bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe800e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (770 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/11908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e8ad00e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e8ad00b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e8ad00ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8679c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8679ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8679c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8679c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8acfa423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e8acfa4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8acf88f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e8acc38166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e8acc37e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8679c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8679c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8679c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8acc37d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (771 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056070dce656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056070dce3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056070dce6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f490b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f490b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f490b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f490b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056070dc7c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056070dc7c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056070dc60f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056070d910166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056070d90fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f490b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f490b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f490b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056070d90fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x 
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e92176956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e921766505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e921769cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32a4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32a48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32a4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32a4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9216ff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e9216ff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9216e3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e921393166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e921392e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f32a4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32a48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32a48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e921392d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055703dc8156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055703dc7e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055703dc81cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd56a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd56a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd56a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd56a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055703dc1723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055703dc17086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055703dbfbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055703d8ab166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055703d8aae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd56a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd56a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd56a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055703d8aad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (774 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_bf16(<vscale x 8 x bfloat> %zn_zm.coerce0, <vscale x 8 x bfloat> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16(<vscale x 8 x half> %zn_zm.coerce0, <vscale x 8 x half> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnb_f8_f32(<vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnt_f8_f32(<vscale x 16 x i8> %zd, <vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zd.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store <vscale x 16 x i8> %zd, ptr %zd.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zd.addr, align 16
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   %7 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret <vscale x 16 x i8> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e33dca856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e33dca5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e33dca8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f908b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f908b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f908b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f908b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e33dc3e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e33dc3e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e33dc22f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e33d8d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e33d8d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f908b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f908b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f908b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e33d8d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055807249356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558072490505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558072493cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5892a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5892aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5892a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5892a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055807242923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558072429086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055807240df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005580720bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005580720bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5892a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5892a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5892a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580720bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055984f44756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055984f444505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055984f447cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa2da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa2daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa2da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa2da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055984f3dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055984f3dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055984f3c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055984f071166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055984f070e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa2da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa2da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa2da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055984f070d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e29ff556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e29ff2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e29ff5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3289049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32890a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3289049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3289031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e29f8b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e29f8b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e29f6ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e29c1f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e29c1ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3289032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32890330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32890330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e29c1ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d09eea356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d09eea0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d09eea3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84d3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84d36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84d3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84d3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d09ee3923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d09ee39086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d09ee1df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d09eacd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d09eacce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84d3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84d36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84d36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d09eaccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (779 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ...
# `---data was truncated (10240/14904) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c6b9ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c6b9eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c6b9eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fb3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fb3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fb3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fb3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c6b98423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c6b984086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c6b968f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c6b618166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c6b617e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8fb3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fb3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fb3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c6b617d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (780 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056142f1ba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056142f1b7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056142f1bacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dd4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dd498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dd4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dd491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056142f15023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056142f150086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056142f134f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056142ede4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056142ede3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6dd491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dd491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dd491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056142ede3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (781 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 2
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 2
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue 
# | ...
# `---data was truncated (10240/21007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056218be6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056218be65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056218be68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3658f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3658f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3658f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3658f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056218bdfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056218bdfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056218bde2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056218ba92166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056218ba91e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3658f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3658f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3658f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056218ba91d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c139c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c139c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c139c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a63905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a6395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a63905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a638ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c1395d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c1395d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c13941f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c135f1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c135f0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3a638eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a638ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a638ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c135f0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b75b56b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b75b568505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b75b56bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b50e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b50ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b50e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b50e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b75b50123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b75b501086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b75b4e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b75b195166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b75b194e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3b50e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b50e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b50e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b75b194d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (784 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsel_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/15264) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055c79d4ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c79d4aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c79d4adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7eb1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7eb1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7eb1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7eb1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c79d44323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c79d443086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c79d427f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c79d0d7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c79d0d6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7eb1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7eb1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7eb1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c79d0d6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562417e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562417e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562417e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe81249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe812a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe81249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe81231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055624177a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055624177a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055624175ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055624140e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055624140de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe81232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe812330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe812330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055624140dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (786 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af7dbfe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af7dbfb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af7dbfecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5d7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5d74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5d7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5d7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af7db9423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af7db94086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af7db78f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af7d828166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af7d827e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc5d7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5d74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5d74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af7d827d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b04443f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b04443c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b04443fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4802305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f480235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4802305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48022ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0443d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0443d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0443b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b044069166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b044068e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f48022eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48022ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48022ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b044068d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587657c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587657bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587657c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f470901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47090725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f470901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4709003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055876575823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558765758086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055876573cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005587653ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005587653ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4709004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47090050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47090050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587653ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (789 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055688446456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556884461505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556884464cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd459649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4596a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd459649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd459631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568843fa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005568843fa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005568843def39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055688408e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055688408de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd459632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4596330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4596330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055688408dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a0dc5056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a0dc4d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a0dc50cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f945261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94526725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f945261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9452603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a0dbe623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a0dbe6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a0dbcaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a0d87a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a0d879e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9452604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94526050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94526050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a0d879d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563127fd456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563127fd1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563127fd4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb163f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb163f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb163f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb163f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563127f6a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563127f6a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563127f4ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563127bfe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563127bfde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb163f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb163f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb163f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563127bfdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (792 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556f9f50356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f9f500505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f9f503cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cdac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cdaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cdac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cdac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f9f49923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f9f499086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f9f47df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f9f12d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f9f12ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4cdac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cdac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cdac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f9f12cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b24749f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b24749c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b24749fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1387505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f138755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1387505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13874ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b24743523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b247435086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b247419f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b2470c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b2470c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13874eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13874ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13874ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2470c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (794 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vsqaddb_u8() #0 {
# | entry:
# |   %__p0.addr.i = alloca i8, align 1
# |   %__p1.addr.i = alloca i8, align 1
# |   %__ret.i = alloca i8, align 1
# |   %ref.tmp.i = alloca i8, align 1
# |   store i8 1, ptr %__p0.addr.i, align 1
# |   store i8 -1, ptr %__p1.addr.i, align 1
# |   %0 = load i8, ptr %__p0.addr.i, align 1
# |   %1 = load i8, ptr %__p1.addr.i, align 1
# |   %2 = insertelement <8 x i8> poison, i8 %0, i64 0
# |   %3 = insertelement <8 x i8> poison, i8 %1, i64 0
# |   %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3)
# |   %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0
# |   store i8 %4, ptr %ref.tmp.i, align 1
# |   %5 = load i8, ptr %ref.tmp.i, align 1
# |   store i8 %5, ptr %__ret.i, align 1
# |   %6 = load i8, ptr %__ret.i, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vsqaddh_u16() #0 {
# | entry:
# |   %__p0.addr.i = alloca i16, align 2
# |   %__p1.addr.i = alloca i16, align 2
# |   %__ret.i = alloca i16, align 2
# |   %ref.tmp.i = alloca i16, align 2
# |   store i16 1, ptr %__p0.addr.i, align 2
# |   store i16 -1, ptr %__p1.addr.i, align 2
# |   %0 = load i16, ptr %__p0.addr.i, align 2
# |   %1 = load i16, ptr %__p1.addr.i, align 2
# |   %2 = insertelement <4 x i16> poison, i16 %0, i64 0
# |   %3 = insertelement <4 x i16> poison, i16 %1, i64 0
# |   %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3)
# |   %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0
# |   store i16 %4, ptr %ref.tmp.i, align 2
# |   %5 = load i16, ptr %ref.tmp.i, align 2
# |   store i16 %5, ptr %__ret.i, align 2
# |   %6 = load i16, ptr %__ret.i, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vsqadds_u32() #0 {
# | entry:
# |   %__p0.addr.i = alloca i32, align 4
# |   %__p1.addr.i = alloca i32, align 4
# |   %__ret.i = alloca i32, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   store i32 1, ptr %__p0.addr.i, align 4
# |   store i32 -1, ptr %__p1.addr.i, align 4
# |   %0 = load i32, ptr %__p0.addr.i, align 4
# |   %1 = load i32, ptr %__p1.addr.i, align 4
# |   %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1)
# |   store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4
# |   %2 = load i32, ptr %ref.tmp.i, align 4
# |   store i32 %2, ptr %__ret.i, align 4
# |   %3 = load i32, ptr %__ret.i, align 4
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vsqaddd_u64() #0 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i64, align 8
# |   %ref.tmp.i = alloca i64, align 8
# |   store i64 1, ptr %__p0.addr.i, align 8
# |   store i64 -1, ptr %__p1.addr.i, align 8
# |   %0 = load i64, ptr %__p0.addr.i, align 8
# |   %1 = load i64, ptr %__p1.addr.i, align 8
# |   %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1)
# |   store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8
# |   %2 = load i64, ptr %ref.tmp.i, align 8
# |   store i64 %2, ptr %__ret.i, align 8
# |   %3 = load i64, ptr %__ret.i, align 8
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# |  #0 0x000056349133156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056349132e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563491331cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2762533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f276258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2762533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f276251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634912c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634912c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005634912abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563490f5b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563490f5ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f276251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f276251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f276251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563490f5ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b81db556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b81db2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b81db5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf2fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf2fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf2fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf2fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b81d4b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b81d4b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b81d2ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b819df166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b819dee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcf2fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf2fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf2fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b819ded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66314) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055906865a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559068657505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055906865acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe008e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe008ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe008e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe008e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590685f023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005590685f0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005590685d4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559068284166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559068283e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe008e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe008e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe008e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559068283d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b8365d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b8365a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b8365dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f837e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f837e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f837e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f837e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b835f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b835f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b835d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b83287166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b83286e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f837e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f837e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f837e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b83286d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (798 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e72ad3056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e72ad2d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e72ad30cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fefa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fefaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fefa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fefa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e72acc623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e72acc6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e72acaaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e72a95a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e72a959e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0fefa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fefa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fefa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e72a959d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575f81ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005575f81ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005575f81edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a8c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a8c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a8c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a8c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575f818323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005575f8183086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005575f8167f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005575f7e17166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005575f7e16e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a8c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a8c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a8c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575f7e16d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598f152356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005598f1520505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005598f1523cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1509d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1509d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1509d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1509d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598f14b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005598f14b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005598f149df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005598f114d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005598f114ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1509d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1509d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1509d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598f114cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3f447f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b3f447c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b3f447fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b5e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b5e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b5e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b5e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3f441523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b3f4415086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b3f43f9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b3f40a9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b3f40a8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b5e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b5e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b5e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3f40a8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 
# | ...
# `---data was truncated (10240/14824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5630b256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5630af505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5630b2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa273733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa27378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa273733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa27371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b56304823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b563048086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b56302cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b562cdc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b562cdbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa27371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa27371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa27371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b562cdbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619f8fc556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005619f8fc2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005619f8fc5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1aa6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1aa655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1aa6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1aa64ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619f8f5b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005619f8f5b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005619f8f3ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005619f8bef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005619f8beee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1aa64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1aa64ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1aa64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619f8beed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, 
# | ...
# `---data was truncated (10240/142319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5f3a9656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5f3a93505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5f3a96cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a25d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a25d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a25d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a25ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5f3a2c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5f3a2c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5f3a10f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5f36c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5f36bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1a25ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a25cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a25cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5f36bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri
# | ...
# `---data was truncated (10240/20523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb83c2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eb83c27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eb83c2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8247733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f824778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8247733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f824771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb83bc023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eb83bc0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eb83ba4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eb83854166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eb83853e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f824771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f824771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f824771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb83853d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579ad1e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579ad1de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579ad1e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7f8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7f8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7f8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7f8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579ad17723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579ad177086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579ad15bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579ace0b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579ace0ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc7f8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7f8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7f8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579ace0ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602b7d1556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005602b7d12505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005602b7d15cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4480133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f448018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4480133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f448011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602b7cab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005602b7cab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005602b7c8ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005602b793f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005602b793ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f448011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f448011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f448011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602b793ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ac96a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555ac96a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555ac96a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03c3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03c3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03c3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03c3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ac963923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555ac9639086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555ac961df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555ac92cd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555ac92cce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03c3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03c3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03c3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ac92ccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ec0dee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ec0deb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ec0deecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4587f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4587f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4587f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4587f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ec0d8423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ec0d84086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ec0d68f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ec0a18166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ec0a17e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4587f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4587f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4587f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ec0a17d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055993c18356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055993c180505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055993c183cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b1d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b1d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b1d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b1d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055993c11923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055993c119086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055993c0fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055993bdad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055993bdace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6b1d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b1d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b1d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055993bdacd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (811 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005644a6c6256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005644a6c5f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005644a6c62cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbaf2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbaf20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbaf2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbaf2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644a6bf823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005644a6bf8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005644a6bdcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005644a688c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005644a688be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbaf2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbaf20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbaf20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644a688bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   
# | ...
# `---data was truncated (10240/223129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559294b7156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559294b6e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559294b71cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84a2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84a278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84a2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84a271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559294b0723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559294b07086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559294aebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055929479b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055929479ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84a271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84a271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84a271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055929479ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/nor.c (813 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnor_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000562bbbfdb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bbbfd8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bbbfdbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea3bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea3bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea3bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea3bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bbbf7123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bbbf71086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bbbf55f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bbbc05166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bbbc04e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fea3bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea3bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea3bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bbbc04d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (814 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load
# | ...
# `---data was truncated (10240/410391) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fa68d356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558fa68d0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558fa68d3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a70249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a702a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a70249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a70231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fa686923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558fa6869086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558fa684df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558fa64fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558fa64fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1a70232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a702330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a702330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fa64fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8bc94a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f8bc947505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f8bc94acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8bc8e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f8bc8e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f8bc8c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f8bc574166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f8bc573e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f12b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8bc573d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (816 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <2 x float>, align 8
# |   store <2 x float> %x, ptr %x.addr, align 8
# |   %0 = load <2 x float>, ptr %x.addr, align 8
# |   %1 = bitcast <2 x float> %0 to <8 x i8>
# |   ret <8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <8 x i8> %0 to <2 x float>
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <4 x float>, align 16
# |   store <4 x float> %x, ptr %x.addr, align 16
# |   %0 = load <4 x float>, ptr %x.addr, align 16
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i128, align 16
# |   store i128 %x, ptr %x.addr, align 16
# |   %0 = load i128, ptr %x.addr, align 16
# |   %1 = bitcast i128 %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to i128
# |   ret i128 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x000055db31bef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055db31bec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055db31befcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73adf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db31b8523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055db31b85086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055db31b69f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055db31819166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055db31818e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f73adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db31818d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bff1fe456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bff1fe1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bff1fe4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff74c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff74c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff74c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff74c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bff1f7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bff1f7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bff1f5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bff1c0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bff1c0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff74c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff74c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff74c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bff1c0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (818 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055652dcfc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055652dcf9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055652dcfccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61ff01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61ff0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61ff01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61ff003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055652dc9223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055652dc92086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055652dc76f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055652d926166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055652d925e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61ff004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61ff0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61ff0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055652d925d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (819 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649ad78356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649ad780505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649ad783cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f92533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f9258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f92533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f9251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649ad71923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005649ad719086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005649ad6fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005649ad3ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005649ad3ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f9251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f9251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f9251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649ad3acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (820 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d4936156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d4935e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d49361cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff62249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff622a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff62249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff62231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d492f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d492f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d492dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d48f8b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d48f8ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff62232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff622330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff622330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d48f8ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c4796a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c47967505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c4796acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe50933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe5098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe50933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe5091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c4790023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c47900086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c478e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c47594166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c47593e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe5091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe5091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe5091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c47593d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (822 of 27911)
******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }>
# | %struct.A.base = type <{ ptr, i32 }>
# | 
# | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8
# | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x000055bc030fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc030fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc030fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81fc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81fc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81fc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81fc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc0309323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc03093086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc03077f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc02d27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc02d26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f81fc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81fc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81fc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc02d26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562327bae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562327bab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562327baecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64c4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64c4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64c4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64c4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562327b4423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562327b44086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562327b28f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005623277d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005623277d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f64c4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64c4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64c4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623277d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555952cf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005555952cc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005555952cfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f530ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f530ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f530ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f530ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055559526523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555595265086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555595249f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555594ef9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555594ef8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f530ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f530ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f530ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555594ef8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (825 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnt1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %b
# | ...
# `---data was truncated (10240/22231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ee3dac456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee3dac1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee3dac4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1a5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee3da5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee3da5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee3da3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee3d6ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee3d6ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe1a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1a5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee3d6edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %b
# | ...
# `---data was truncated (10240/38307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bbb85f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558bbb85c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558bbb85fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62a5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62a54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62a5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62a5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bbb7f523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558bbb7f5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558bbb7d9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558bbb489166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558bbb488e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62a5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62a54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62a54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bbb488d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557edbda656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557edbda3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557edbda6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3f0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3f06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3f0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3f0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557edbd3c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557edbd3c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557edbd20f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557edb9d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557edb9cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb3f0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3f06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3f06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557edb9cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# | 
# | ...
# `---data was truncated (10240/211223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620e70f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005620e70f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005620e70f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3be3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3be3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3be3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3be3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620e708d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005620e708d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005620e7071f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005620e6d21166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005620e6d20e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3be3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3be3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3be3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620e6d20d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (829 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/134744) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a9224a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557a92247505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557a9224acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f260e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f260e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f260e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f260e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a921e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557a921e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557a921c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557a91e74166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557a91e73e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f260e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f260e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f260e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a91e73d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (830 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/11849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec686c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ec686c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ec686c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e97849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e97849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e97831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec6865d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ec6865d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ec68641f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ec682f1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ec682f0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3e97832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e978330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec682f0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558be680956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558be6806505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558be6809cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f209ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f209ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f209ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f209ba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558be679f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558be679f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558be6783f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558be6433166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558be6432e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f209ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f209ba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f209ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558be6432d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (832 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5
# | ...
# `---data was truncated (10240/15508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585b26f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005585b26ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005585b26f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b57849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b57849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b57831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585b268723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005585b2687086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005585b266bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005585b231b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005585b231ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6b57832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b578330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585b231ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555b443956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005555b4436505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005555b4439cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca4d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca4d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca4d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca4d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555b43cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005555b43cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005555b43b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005555b4063166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005555b4062e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca4d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca4d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca4d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555b4062d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (834 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> }
# | ...
# `---data was truncated (10240/45653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005607b06b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005607b06b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005607b06b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8922c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8922c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8922c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8922c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607b064e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005607b064e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005607b0632f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607b02e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607b02e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8922c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8922c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8922c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607b02e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056481acfc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056481acf9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056481acfccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34d4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34d4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34d4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34d4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056481ac9223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056481ac92086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056481ac76f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056481a926166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056481a925e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f34d4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34d4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34d4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056481a925d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa9dc4456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa9dc41505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa9dc44cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadadb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadadb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadadb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadadb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa9dbda23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa9dbda086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa9dbbef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa9d86e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa9d86de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fadadb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadadb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadadb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa9d86dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (837 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 4)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 5)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 2)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 3)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svextq_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svextq_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 2)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svextq_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svextq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 6)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr,
# | ...
# `---data was truncated (10240/11061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005593132f056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005593132ed505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005593132f0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff99d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff99d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff99d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff99ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055931328623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559313286086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055931326af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559312f1a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559312f19e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff99ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff99cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff99cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559312f19d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (838 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558b38f6e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b38f6b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b38f6ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67b891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b38f0423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b38f04086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b38ee8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b38b98166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b38b97e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f67b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67b891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b38b97d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (839 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i)
# |   store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i)
# |   store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i)
# |   store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i)
# |   store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i)
# |   store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i)
# |   store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i)
# |   store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i)
# |   store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vrndns_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vrndn.i = call float @llvm.roundeven.f32(float %1)
# |   store float %vrndn.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i)
# |   store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndm.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i)
# |   store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i)
# |   store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a
# | ...
# `---data was truncated (10240/29785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557259c4256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557259c3f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557259c42cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d84449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d844a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d84449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d84431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557259bd823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557259bd8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557259bbcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055725986c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055725986be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d84432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d844330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d844330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055725986bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8faedc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c8faed9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c8faedccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f346ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f346ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8fae7223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c8fae72086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c8fae56f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c8fab06166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c8fab05e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f346ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8fab05d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (841 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %p0.addr = alloca <8 x half>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <8 x half> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <8 x half>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d9b444956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d9b4446505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d9b4449cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2d241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2d24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2d241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2d2403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9b43df23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9b43df086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9b43c3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9b4073166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9b4072e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2d2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2d24050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2d24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9b4072d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 
# | ...
# `---data was truncated (10240/97240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577f8c1756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005577f8c14505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005577f8c17cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb00b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb00b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb00b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb00b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577f8bad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005577f8bad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005577f8b91f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005577f8841166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005577f8840e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdb00b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb00b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb00b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577f8840d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a36dc856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564a36dc5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564a36dc8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64b6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64b658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64b6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64b651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a36d5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564a36d5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564a36d42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564a369f2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564a369f1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f64b651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64b651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64b651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a369f1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056533fb0c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056533fb09505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056533fb0ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fd9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fd998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fd9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fd991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056533faa223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056533faa2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056533fa86f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056533f736166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056533f735e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9fd991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fd991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fd991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056533f735d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a28c14b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a28c148505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a28c14bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fa5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fa54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fa5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fa5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a28c0e123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a28c0e1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a28c0c5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a28bd75166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a28bd74e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6fa5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fa54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fa54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a28bd74d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cbaac456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563cbaac1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563cbaac4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f42e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f42e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f42e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f42e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cbaa5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563cbaa5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563cbaa3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563cba6ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563cba6ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f42e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f42e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f42e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cba6edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af37a5956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af37a56505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af37a59cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28f9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28f9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28f9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28f9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af379ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af379ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af379d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af37683166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af37682e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f28f9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28f9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28f9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af37682d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (848 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed5ec5056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed5ec4d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed5ec50cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95ddd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95ddd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95ddd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95ddd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed5ebe623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed5ebe6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed5ebcaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed5e87a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed5e879e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f95ddd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95ddd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95ddd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed5e879d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056533ddd156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056533ddce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056533ddd1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2444a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2444aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2444a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2444a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056533dd6723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056533dd67086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056533dd4bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056533d9fb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056533d9fae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2444a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2444a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2444a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056533d9fad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056160de9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056160de94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056160de97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f844b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f844b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f844b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f844b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056160de2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056160de2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056160de11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056160dac1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056160dac0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f844b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f844b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f844b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056160dac0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x
# | ...
# `---data was truncated (10240/514173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd3cf1456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dd3cf11505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dd3cf14cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46b3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46b3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46b3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46b3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd3ceaa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dd3ceaa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dd3ce8ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dd3cb3e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dd3cb3de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f46b3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46b3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46b3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd3cb3dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (852 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d12735356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d127350505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d127353cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d9bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d9bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d9bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d9bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1272e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d1272e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d1272cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d126f7d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d126f7ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d9bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d9bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d9bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d126f7cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (853 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x bfloat> %1, i32 1
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x bfloat> %1, i32 7
# |   store bfloat %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_48 = alloca <4 x bfloat>, align 8
# |   %__s0_48 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_48, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_48, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_48, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_48, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_46 = alloca <8 x bfloat>, align 16
# |   %__s0_46 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_46, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_46, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_46, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_46, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_52 = alloca <4 x bfloat>, align 8
# |   %__s0_52 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_52, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_52, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_52, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_52, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_50 = alloca <8 x bfloat>, align 16
# |   %__s0_50 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_50, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_50, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_50, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_50, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %.compoundliteral.i = alloca <4 x bfloat>, align 8
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8
# |   store <4 x bfloat> %5, ptr %__ret.i, align 8
# |   %6 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %.compoundliteral.i = alloca <8 x bfloat>, align 16
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   %5 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4
# |   %6 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5
# |   %7 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6
# |   %8 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7
# |   store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/13833) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000564c3bfd156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c3bfce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c3bfd1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5b3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5b358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5b3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5b351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c3bf6723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c3bf67086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c3bf4bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c3bbfb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c3bbfae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd5b351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5b351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5b351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c3bbfad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>,
# | ...
# `---data was truncated (10240/16521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a32013f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a32013c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a32013fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cd6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cd698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cd6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cd691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3200d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a3200d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a3200b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a31fd69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a31fd68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2cd691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cd691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cd691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a31fd68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d2936356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556d29360505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556d29363cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0ce533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0ce58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0ce533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0ce51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d292f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556d292f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556d292ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556d28f8d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556d28f8ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0ce51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0ce51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0ce51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d28f8cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = al
# | ...
# `---data was truncated (10240/41670) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564f2d7f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005564f2d7c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005564f2d7fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0570133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f057018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0570133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f057011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564f2d1523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005564f2d15086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005564f2cf9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005564f29a9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005564f29a8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f057011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f057011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f057011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564f29a8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056201125756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562011254505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562011257cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a4f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a4f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a4f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a4f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620111ed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005620111ed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005620111d1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562010e81166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562010e80e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7a4f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a4f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a4f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562010e80d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d89482b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d894828505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d89482bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa914b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa914b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa914b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa914b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8947c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8947c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8947a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d894455166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d894454e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa914b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa914b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa914b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d894454d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056519048e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056519048b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056519048ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62d4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62d478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62d4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62d471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056519042423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565190424086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565190408f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005651900b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005651900b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62d471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62d471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62d471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651900b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a675ab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a675a8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a675abcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2731933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f273198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2731933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f273191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a6754123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a67541086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a67525f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a671d5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a671d4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f273191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f273191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f273191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a671d4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce638f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce638f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce638f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8022733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f802278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8022733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f802271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce6388d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce6388d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce63871f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce63521166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce63520e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f802271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f802271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f802271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce63520d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056231c85656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056231c853505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056231c856cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e17333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e1738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e17333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e1731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056231c7ec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056231c7ec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056231c7d0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056231c480166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056231c47fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e1731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e1731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e1731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056231c47fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (863 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, alig
# | ...
# `---data was truncated (10240/150641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605a905a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005605a9057505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005605a905acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f999cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f999cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f999cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f999cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605a8ff023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005605a8ff0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005605a8fd4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005605a8c84166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005605a8c83e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f999cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f999cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f999cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605a8c83d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eda800156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eda7ffe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eda8001cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed94049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed940a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed94049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed94031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eda7f9723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eda7f97086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eda7f7bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eda7c2b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eda7c2ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fed94032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed940330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed940330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eda7c2ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aea876156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aea875e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aea8761cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13d6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aea86f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aea86f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aea86dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aea838b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aea838ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aea838ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (866 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d52d4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d52d4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d52d4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92eb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92eb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92eb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92eb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d52ce523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d52ce5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d52cc9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d52979166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d52978e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f92eb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92eb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92eb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d52978d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056071d44d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056071d44a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056071d44dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd17049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd170a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd17049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd17031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056071d3e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056071d3e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056071d3c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056071d077166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056071d076e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd17032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd170330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd170330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056071d076d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b3777956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b37776505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b37779cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecaef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecaef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecaef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecaeeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b3770f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b3770f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b376f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b373a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b373a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fecaeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecaeeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecaeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b373a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (869 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg             | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vaddh = fadd half %2, %3
# |   store half %vaddh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vsubh = fsub half %2, %3
# |   store half %vsubh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmulh = fmul half %2, %3
# |   store half %vmulh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vdivh = fdiv half %2, %3
# |   store half %vdivh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3)
# |   store half %vmax, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3)
# |   store half %vmaxnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3)
# |   store half %vmin, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3)
# |   store half %vminnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabsh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vabs = call half @llvm.fabs.f16(half %1)
# |   store half %vabs, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.fabs.f16(half) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = all
# | ...
# `---data was truncated (10240/27802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b90230b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b902308505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b90230bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8af5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8af558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8af5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8af551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9022a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b9022a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b902285f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b901f35166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b901f34e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8af551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8af551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8af551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b901f34d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8fc9dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8fc9da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8fc9ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44e6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44e638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44e6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44e631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8fc97323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8fc973086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8fc957f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8fc607166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8fc606e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f44e631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44e631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44e631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8fc606d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ff8f2f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ff8f2c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ff8f2fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f721861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72186725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f721861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7218603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ff8ec523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ff8ec5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ff8ea9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ff8b59166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ff8b58e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7218604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72186050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72186050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ff8b58d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6812a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a68129f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a6812a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b41d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b41d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b41d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b41d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a68123823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a681238086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a68121cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a680ecc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a680ecbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b41d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b41d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b41d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a680ecbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056024abe056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056024abdd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056024abe0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f675b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f675b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f675b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f675b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056024ab7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056024ab76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056024ab5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056024a80a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056024a809e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f675b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f675b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f675b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056024a809d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645ba78c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645ba789505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645ba78ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda8b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda8b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda8b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda8b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645ba72223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645ba722086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645ba706f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645ba3b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645ba3b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda8b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda8b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda8b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645ba3b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 
# | ...
# `---data was truncated (10240/66065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562929b0a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562929b07505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562929b0acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8fbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8fbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8fbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8fbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562929aa023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562929aa0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562929a84f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562929734166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562929733e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb8fbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8fbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8fbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562929733d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f021be056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f021bdd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f021be0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e23849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e23849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e23831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f021b7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f021b76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f021b5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f02180a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f021809e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e23832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e238330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f021809d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/80648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600f48ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005600f48eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005600f48eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13f0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13f038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13f0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13f031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600f488423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600f4884086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600f4868f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005600f4518166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005600f4517e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13f031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13f031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13f031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600f4517d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d1bd6a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557d1bd67505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557d1bd6acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf87905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf8795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf87905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf878ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d1bd0023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557d1bd00086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557d1bce4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557d1b994166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557d1b993e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbf878eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf878ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf878ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d1b993d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (879 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561345c2d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561345c2a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561345c2dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c02649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c026a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c02649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c02631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561345bc323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561345bc3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561345ba7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561345857166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561345856e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2c02632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c026330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c026330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561345856d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (880 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560787c7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560787c72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560787c75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc72f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc72f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc72f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc72f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560787c0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560787c0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560787beff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056078789f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056078789ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc72f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc72f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc72f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056078789ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e173eb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e173e8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e173ebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe234333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe23438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe234333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe23431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e1738123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e17381086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e17365f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e17015166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e17014e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe23431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe23431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe23431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e17014d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cadbbe956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cadbbe6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cadbbe9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe70c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe70c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe70c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe70c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cadbb7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cadbb7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cadbb63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cadb813166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cadb812e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe70c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe70c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe70c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cadb812d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (883 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   
# | ...
# `---data was truncated (10240/11488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fb60b5c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb60b59505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb60b5ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf3a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf3a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf3a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf3a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb60af223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb60af2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb60ad6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb60786166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb60785e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbf3a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf3a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf3a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb60785d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (884 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__ret.i, align 8
# |   %2 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 {
# | entry:
# |   
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x00005620aca4456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005620aca41505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005620aca44cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee2dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee2dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee2dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620ac9da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005620ac9da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005620ac9bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005620ac66e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005620ac66de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fee2dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee2dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee2dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620ac66dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (885 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f8274656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f82743505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f82746cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7c0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7c00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7c0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7c0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f826dc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f826dc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f826c0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f82370166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f8236fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc7c0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7c00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7c00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f8236fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645a4d3656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645a4d33505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645a4d36cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7adc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7adc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7adc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7adc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645a4ccc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645a4ccc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645a4cb0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645a4960166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645a495fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7adc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7adc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7adc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645a495fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f43edc856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f43edc5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f43edc8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc340449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3404a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc340449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc340431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f43ed5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f43ed5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f43ed42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f43e9f2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f43e9f1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc340432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3404330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3404330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f43e9f1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac4918956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac49186505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac49189cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8979a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8979aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8979a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8979a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac4911f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac4911f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac49103f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac48db3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac48db2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8979a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8979a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8979a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac48db2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d88af156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d88aee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d88af1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd237449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2374a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd237449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd237431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d88a8723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d88a87086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d88a6bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d8871b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d8871ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd237432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2374330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2374330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d8871ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055742c2e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055742c2e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055742c2e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a58849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a588a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a58849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a58831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055742c27d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055742c27d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055742c261f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055742bf11166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055742bf10e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a58832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a588330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a588330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055742bf10d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (891 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vmv_v_v_i16mf4(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vmv_v_v_i16mf2(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vmv_v_v_i16m1(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vmv_v_v_i16m2(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vmv_v_v_i16m4(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vmv_v_v_i16m8(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/68067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb8cf8e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eb8cf8b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eb8cf8ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a39249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a392a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a39249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a39231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb8cf2423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eb8cf24086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eb8cf08f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eb8cbb8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eb8cbb7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a39232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a392330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a392330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb8cbb7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (892 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6663e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6663e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6663e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda3f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda3f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda3f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda3f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b66637923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b666379086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b66635df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b66600d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b66600ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda3f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda3f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda3f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b66600cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056079578156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056079577e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560795781cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc727333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc72738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc727333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc72731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056079571723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560795717086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005607956fbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607953ab166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607953aae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc72731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc72731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc72731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607953aad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560aec91c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560aec919505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560aec91ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd98049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd98049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd98031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560aec8b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560aec8b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560aec896f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560aec546166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560aec545e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd98032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd980330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560aec545d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a4d52456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555a4d521505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555a4d524cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ce2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ce2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ce2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ce2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a4d4ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555a4d4ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555a4d49ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555a4d14e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555a4d14de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3ce2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ce2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ce2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a4d14dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (896 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0)
# |   r
# | ...
# `---data was truncated (10240/43005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d86dc356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d86dc0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d86dc3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8219849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82198a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8219849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8219831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d86d5923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d86d59086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d86d3df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d869ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d869ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8219832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82198330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82198330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d869ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, a
# | ...
# `---data was truncated (10240/18875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2864f556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2864f2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2864f5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaa2105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaa215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaa2105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaa20ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e28648b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e28648b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e28646ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e28611f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e28611ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcaa20eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaa20ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaa20ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e28611ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559376c7956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559376c76505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559376c79cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff717533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff71758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff717533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff71751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559376c0f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559376c0f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559376bf3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005593768a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005593768a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff71751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff71751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff71751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593768a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (899 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611bd9b556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005611bd9b2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005611bd9b5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bb221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bb22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bb221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bb2203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611bd94b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005611bd94b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005611bd92ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005611bd5df166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005611bd5dee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8bb2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bb22050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bb22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611bd5ded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056011389456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560113891505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560113894cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b36249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b362a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b36249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b36231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056011382a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056011382a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056011380ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601134be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601134bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b36232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b362330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b362330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601134bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557982be056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557982bdd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557982be0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd5ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd5ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557982b7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557982b76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557982b5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055798280a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557982809e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd5ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557982809d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056514c3c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056514c3c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056514c3c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e9b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e9b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e9b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e9b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056514c35c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056514c35c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056514c340f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056514bff0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056514bfefe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e9b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e9b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e9b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056514bfefd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (903 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622ac8c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005622ac8c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005622ac8c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b14049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b140a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b14049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b14031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622ac85b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005622ac85b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005622ac83ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005622ac4ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005622ac4eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3b14032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b140330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b140330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622ac4eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a77281956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a772816505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a772819cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a4361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a436725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a4361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a43603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7727af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a7727af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a772793f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a772443166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a772442e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a43604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a436050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a436050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a772442d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr,
# | ...
# `---data was truncated (10240/23056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559a6a1056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559a6a0d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559a6a10cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1997649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19976a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1997649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1997631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559a69a623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559a69a6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559a698af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559a663a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559a6639e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1997632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19976330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19976330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559a6639d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (906 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e2b21856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e2b215505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e2b218cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f971c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f971c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f971c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f971c203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e2b1ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e2b1ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e2b192f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e2ae42166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e2ae41e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f971c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f971c2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f971c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e2ae41d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (907 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005617b389b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005617b3898505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005617b389bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f331f305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f331f35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f331f305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f331f2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617b383123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005617b3831086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005617b3815f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005617b34c5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005617b34c4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f331f2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f331f2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f331f2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617b34c4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9c014256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d9c013f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d9c0142cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ab8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ab88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ab8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ab8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9c00d823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9c00d8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9c00bcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9bfd6c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9bfd6be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ab8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ab88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ab88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9bfd6bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vsc
# | ...
# `---data was truncated (10240/207075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a72565b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a725658505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a72565bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb322f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb322f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb322f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb322eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7255f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a7255f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a7255d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a725285166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a725284e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb322eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb322eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb322eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a725284d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i
# | ...
# `---data was truncated (10240/120468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0e74ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b0e74cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b0e74cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3033e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3033ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3033e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3033e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0e746423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0e7464086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0e7448f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b0e70f8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b0e70f7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3033e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3033e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3033e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0e70f7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (911 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <16 x i8> %2, %3
# |   store <16 x i8> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <8 x i16> %2, %3
# |   store <8 x i16> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <4 x i32> %2, %3
# |   store <4 x i32> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   store <1 x i64> %v2, ptr %v2.addr, align 8
# |   %0 = load <1 x i64>, ptr %v1.addr, align 8
# |   %1 = load <1 x i64>, ptr %v2.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <1 x i64> %2, %3
# |   store <1 x i64> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v1.addr = alloca <2 x i64>, align 16
# |   %v2.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %v1, ptr %v1.addr, align 16
# |   store <2 x i64> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x i64>, ptr %v1.addr, align 16
# |   %1 = load <2 x i64>, ptr %v2.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <2 x i64> %2, %3
# |   store <2 x i64> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/170019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055fd22f5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd22f53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd22f56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f009b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f009b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f009b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f009b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd22eec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd22eec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd22ed0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd22b80166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd22b7fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f009b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f009b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f009b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd22b7fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055706f82f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055706f82c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055706f82fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bbf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bbf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bbf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bbf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055706f7c523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055706f7c5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055706f7a9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055706f459166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055706f458e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8bbf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bbf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bbf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055706f458d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567f155e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005567f155b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005567f155ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cb5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cb50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cb5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cb5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567f14f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005567f14f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005567f14d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005567f1188166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005567f1187e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1cb5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cb50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cb50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567f1187d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636764bb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636764b8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636764bbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa09a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa09a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa09a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa09a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056367645123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563676451086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563676435f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005636760e5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005636760e4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa09a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa09a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa09a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636760e4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f47e3e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f47e3b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f47e3ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40b8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40b8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40b8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40b8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f47dd423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f47dd4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f47db8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f47a68166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f47a67e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f40b8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40b8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40b8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f47a67d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609aa51856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005609aa515505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005609aa518cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f239bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f239bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f239bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f239bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609aa4ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005609aa4ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005609aa492f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005609aa142166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005609aa141e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f239bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f239bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f239bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609aa141d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %isneg.i = icmp slt i32 %1, 0
# |   %not.i = xor i32 %1, -1
# |   %2 = select i1 %isneg.i, i32 %not.i, i32 %1
# |   %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false)
# |   %4 = sub nuw i32 %3, 1
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rev_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %2 = call i32 @llvm.bitreverse.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rd.addr.i, align 4
# |   %4 = load i32, ptr %__rs1.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rs1.addr.i, align 4
# |   %4 = load i32, ptr %__rd.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false)
# |   ret i32 %elt.abs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function At
# | ...
# `---data was truncated (10240/1228637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x0000559da677a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559da6777505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559da677acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab9741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab974725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab9741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab97403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559da671023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559da6710086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559da66f4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559da63a4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559da63a3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab97404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab974050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab974050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559da63a3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4d342e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4d342b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4d342ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd12533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd1258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd12533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd1251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4d33c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4d33c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4d33a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4d3058166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4d3057e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd1251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd1251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd1251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4d3057d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d571f6956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d571f66505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d571f69cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f559e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f559e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f559e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f559e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d571eff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d571eff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d571ee3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d571b93166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d571b92e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f559e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f559e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f559e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d571b92d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1c437956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1c4376505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1c4379cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5036533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f503658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5036533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f503651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1c430f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1c430f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1c42f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1c3fa3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1c3fa2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f503651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f503651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f503651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1c3fa2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (921 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae47f5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae47f53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae47f56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f145d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f145d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f145d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f145d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae47eec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae47eec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae47ed0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae47b80166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae47b7fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f145d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f145d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f145d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae47b7fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (922 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562eafa3556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562eafa32505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562eafa35cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf34849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf34849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf34831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562eaf9cb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562eaf9cb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562eaf9aff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562eaf65f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562eaf65ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdf34832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf348330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562eaf65ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587c36b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587c36b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587c36b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e94e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e94e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e94e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e94e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587c364e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005587c364e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005587c3632f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005587c32e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005587c32e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e94e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e94e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e94e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587c32e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, a
# | ...
# `---data was truncated (10240/71115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599f62a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005599f62a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005599f62a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e39c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e39c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e39c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e39c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599f623a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599f623a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005599f621ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005599f5ece166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005599f5ecde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e39c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e39c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e39c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599f5ecdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5950bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5950b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5950bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef83f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef83f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef83f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef83f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b59505223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b595052086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b595036f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b594ce6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b594ce5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef83f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef83f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef83f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b594ce5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu
# | ...
# `---data was truncated (10240/156765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca7f3a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ca7f3a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ca7f3a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda8f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda8f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda8f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda8f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca7f33c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ca7f33c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ca7f320f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ca7efd0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ca7efcfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda8f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda8f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda8f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca7efcfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556156e3256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556156e2f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556156e32cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95bca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95bcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95bca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95bca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556156dc823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556156dc8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556156dacf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556156a5c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556156a5be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f95bca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95bca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95bca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556156a5bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdf413656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bdf4133505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bdf4136cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3340c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3340ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3340c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3340c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdf40cc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bdf40cc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bdf40b0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bdf3d60166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bdf3d5fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3340c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3340c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3340c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdf3d5fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (929 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrffr(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055798cdce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055798cdcb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055798cdcecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facb841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facb84725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facb841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facb8403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055798cd6423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055798cd64086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055798cd48f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055798c9f8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055798c9f7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007facb8404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facb84050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facb84050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055798c9f7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581e7a8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005581e7a84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005581e7a87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5711933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f571198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5711933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f571191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581e7a1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581e7a1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581e7a01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581e76b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581e76b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f571191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f571191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f571191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581e76b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5b1b0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d5b1aff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d5b1b02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e1ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e1ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e1ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e1eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5b1a9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d5b1a98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d5b1a7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d5b172c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d5b172be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e1eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e1eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e1eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5b172bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563933d7f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563933d7c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563933d7fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cf4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cf4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cf4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cf4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563933d1523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563933d15086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563933cf9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639339a9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639339a8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0cf4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cf4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cf4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639339a8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055598b6d056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055598b6cd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055598b6d0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e79e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e79ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e79e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e79e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055598b66623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055598b666086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055598b64af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055598b2fa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055598b2f9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e79e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e79e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e79e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055598b2f9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647bd96856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005647bd965505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005647bd968cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7718849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7718849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7718831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647bd8fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005647bd8fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005647bd8e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005647bd592166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005647bd591e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7718832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77188330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647bd591d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562304c4756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562304c44505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562304c47cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa30333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa3038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa30333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa3031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562304bdd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562304bdd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562304bc1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562304871166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562304870e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa3031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa3031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa3031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562304870d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ccccd756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558ccccd4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558ccccd7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1083449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1083449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1083431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cccc6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558cccc6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558cccc51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558ccc901166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558ccc900e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1083432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10834330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ccc900d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cee45556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cee452505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cee455cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f202ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f202ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f202ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f202ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cee3eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cee3eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cee3cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cee07f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cee07ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f202ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f202ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f202ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cee07ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561727a6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561727a6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561727a6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90eb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90eb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90eb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90eb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561727a0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561727a03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005617279e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561727697166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561727696e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f90eb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90eb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90eb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561727696d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e37a2956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e37a26505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e37a29cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9501c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9501ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9501c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9501c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e379bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e379bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e379a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e37653166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e37652e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9501c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9501c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9501c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e37652d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564aa865656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564aa8653505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564aa8656cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f668d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f668d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f668d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f668d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aa85ec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564aa85ec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564aa85d0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564aa8280166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564aa827fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f668d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f668d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f668d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aa827fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (941 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d8aac8c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8aac89505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8aac8ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb96ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb96ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb96ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb96ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8aac2223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8aac22086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8aac06f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8aa8b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8aa8b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb96ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb96ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb96ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8aa8b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (942 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e00876d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e00876a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e00876dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3765333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f376538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3765333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f376531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e00870323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e008703086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e0086e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e008397166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e008396e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f376531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f376531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f376531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e008396d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc6b6d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc6b6d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc6b6d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09bff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09bff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09bff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09bff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc6b66e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc6b66e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc6b652f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc6b302166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc6b301e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f09bff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09bff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09bff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc6b301d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (944 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon   -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_790 = alloca <4 x i16>, align 8
# |   %__s0_790 = alloca <4 x i16>, align 8
# |   %__s1_790 = alloca <4 x i16>, align 8
# |   %__s2_790 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_790, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_790, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_790, align 16
# |   %3 = load <4 x i16>, ptr %__s0_790, align 8
# |   %4 = load <4 x i16>, ptr %__s1_790, align 8
# |   %5 = load <8 x i16>, ptr %__s2_790, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_790, align 8
# |   %16 = load <4 x i16>, ptr %__ret_790, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_788 = alloca <2 x i32>, align 8
# |   %__s0_788 = alloca <2 x i32>, align 8
# |   %__s1_788 = alloca <2 x i32>, align 8
# |   %__s2_788 = alloca <4 x i32>, align 16
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_788, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_788, align 8
# |   %2 = load <4 x i32>, ptr %v.addr, align 16
# |   store <4 x i32> %2, ptr %__s2_788, align 16
# |   %3 = load <2 x i32>, ptr %__s0_788, align 8
# |   %4 = load <2 x i32>, ptr %__s1_788, align 8
# |   %5 = load <4 x i32>, ptr %__s2_788, align 16
# |   store <4 x i32> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x i32>
# |   %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> <i32 3, i32 3>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %14 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %14, ptr %__ret.i, align 8
# |   %15 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %15, ptr %__ret_788, align 8
# |   %16 = load <2 x i32>, ptr %__ret_788, align 8
# |   store <2 x i32> %16, ptr %tmp1, align 8
# |   %17 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_786 = alloca <8 x i16>, align 16
# |   %__s0_786 = alloca <8 x i16>, align 16
# |   %__s1_786 = alloca <8 x i16>, align 16
# |   %__s2_786 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_786, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_786, align 16
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_786, align 16
# |   %3 = load <8 x i16>, ptr %__s0_786, align 16
# |   %4 = load <8 x i16>, ptr %__s1_786, align 16
# |   %5 = load <8 x i16>, ptr %__s2_786, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   store <8 x i16> %3, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %4, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %10, ptr %__p2.addr.i, align 16
# |   %11 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %14 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %15, ptr %__ret_786, align 16
# |   %16 = load <8 x i16>, ptr %__ret_786, align 16
# |   store <8 x i16> %16, ptr %tmp1, align 16
# |   %17 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_784 = alloca <4 x i32>, align 16
# |   %__s0_784 = alloca <4 x i32>, align 16
# |   %__s1_784 = alloca <4 x i32>, align 16
# |   %__s2_784 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <4
# | ...
# `---data was truncated (10240/50621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x0000559c35b8d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c35b8a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c35b8dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f586f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f586f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f586f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f586f603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c35b2323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c35b23086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c35b07f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c357b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c357b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f586f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f586f6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f586f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c357b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e16782956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e167826505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e167829cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd40305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd4035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd40305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd402ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1677bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e1677bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1677a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e167453166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e167452e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd402eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd402ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd402ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e167452d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9ccf4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c9ccf4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c9ccf4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1f9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1f92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1f9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1f9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9ccee523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c9ccee5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c9ccec9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c9ccb79166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c9ccb78e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb1f9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1f92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1f92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9ccb78d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (947 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale 
# | ...
# `---data was truncated (10240/30627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647a623e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005647a623b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005647a623ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd08a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd08a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd08a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd08a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647a61d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005647a61d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005647a61b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005647a5e68166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005647a5e67e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd08a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd08a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd08a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647a5e67d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589b29d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589b29d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589b29d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8af333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8af38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8af333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8af31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589b296e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589b296e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589b2952f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589b2602166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589b2601e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8af31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8af31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8af31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589b2601d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e10c0db56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e10c0d8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e10c0dbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41e1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41e1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41e1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41e1c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e10c07123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e10c071086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e10c055f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e10bd05166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e10bd04e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f41e1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41e1c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41e1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e10bd04d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/154207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0f24fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0f24fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0f24fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca41533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca4158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca41533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca4151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0f249323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c0f2493086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c0f2477f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c0f2127166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c0f2126e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca4151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca4151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca4151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0f2126d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (951 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a419f1056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a419f0d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a419f10cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44d9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44d918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44d9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44d911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a419ea623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a419ea6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a419e8af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a419b3a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a419b39e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f44d911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44d911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44d911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a419b39d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562adff956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562adff6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562adff9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f453f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f453f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f453f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f453f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562adf8f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562adf8f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562adf73f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562adc23166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562adc22e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f453f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f453f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f453f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562adc22d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573742cf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005573742cc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005573742cfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6da4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6da44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6da4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6da4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055737426523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557374265086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557374249f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557373ef9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557373ef8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6da4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6da44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6da44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557373ef8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (954 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559c10f0356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c10f00505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c10f03cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5128533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f512858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5128533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f512851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c10e9923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c10e99086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c10e7df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c10b2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c10b2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f512851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f512851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f512851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c10b2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64 immar
# | ...
# `---data was truncated (10240/14780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557eb5c9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557eb5c94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557eb5c97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38b7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38b7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38b7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38b7eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557eb5c2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557eb5c2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557eb5c11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557eb58c1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557eb58c0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f38b7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38b7eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38b7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557eb58c0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c1257556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556c12572505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556c12575cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3152049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31520a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3152049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3152031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c1250b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556c1250b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556c124eff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556c1219f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556c1219ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3152032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31520330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31520330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c1219ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (957 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c68c96556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c68c962505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c68c965cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe847333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe84738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe847333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe84731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c68c8fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c68c8fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c68c8dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c68c58f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c68c58ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe84731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe84731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe84731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c68c58ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (958 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cfbf1656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563cfbf13505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563cfbf16cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9506d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9506d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9506d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9506d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cfbeac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563cfbeac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563cfbe90f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563cfbb40166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563cfbb3fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9506d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9506d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9506d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cfbb3fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (959 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp ule <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp ule <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp ule <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f2075856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f20755505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f20758cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff172449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff172449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff172431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f206ee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f206ee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f206d2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f20382166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f20381e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff172432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1724330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f20381d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/13617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2727c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d2727c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d2727c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3b8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3b8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3b8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3b8e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d27275c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d27275c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d272740f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2723f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2723efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3b8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3b8e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3b8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2723efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604a859556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005604a8592505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005604a8595cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f155ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f155ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f155ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f155aaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604a852b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005604a852b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604a850ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005604a81bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005604a81bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f155aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f155aaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f155aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604a81bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568926dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005568926d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005568926dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3c2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3c218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3c2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3c211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055689267223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556892672086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556892656f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556892306166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556892305e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3c211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3c211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3c211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556892305d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (963 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f699ecf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f699ecc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f699ecfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4a5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4a5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4a5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4a5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f699e6523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f699e65086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f699e49f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f699af9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f699af8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4a5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4a5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4a5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f699af8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a977f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a977ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a977f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec71733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec7178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec71733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec7171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a9778723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a97787086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a9776bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a9741b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a9741ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec7171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec7171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec7171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a9741ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (965 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i3
# | ...
# `---data was truncated (10240/57708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e68bb7956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e68bb76505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e68bb79cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76a851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e68bb0f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e68bb0f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e68baf3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e68b7a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e68b7a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f76a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76a851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e68b7a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056530970a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565309707505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056530970acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59ad849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59ad8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59ad849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59ad831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653096a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005653096a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565309684f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565309334166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565309333e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f59ad832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59ad8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59ad8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565309333d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (967 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, half noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca half, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store half %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load half, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync no
# | ...
# `---data was truncated (10240/10512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562f5ac5d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f5ac5a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f5ac5dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f161a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f161a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f161a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f161a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f5abf323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f5abf3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f5abd7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f5a887166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f5a886e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f161a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f161a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f161a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f5a886d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (968 of 27911)
******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c"
# | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128"
# | target triple = "i386-apple-darwin10"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke_copy_to_stack() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 {
# | entry:
# |   %that.addr = alloca ptr, align 4
# |   %methodIndex.addr = alloca i32, align 4
# |   %paramCount.addr = alloca i32, align 4
# |   %params.addr = alloca ptr, align 4
# |   store ptr %that, ptr %that.addr, align 4
# |   store i32 %methodIndex, ptr %methodIndex.addr, align 4
# |   store i32 %paramCount, ptr %paramCount.addr, align 4
# |   store ptr %params, ptr %params.addr, align 4
# |   call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
# | attributes #1 = { nounwind }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"NumRegisterParameters", i32 0}
# | !1 = !{!"clang version 24.0.0"}
# | !2 = !{i64 1623}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# |  #0 0x000055625117056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055625116d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556251170cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd201533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd20158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd201533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd20151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055625110623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556251106086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562510eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556250d9a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556250d99e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd20151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd20151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd20151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556250d99d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i6
# | ...
# `---data was truncated (10240/182165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557eca8c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557eca8c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557eca8c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f360b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f360b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f360b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f360b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557eca85923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557eca859086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557eca83df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557eca4ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557eca4ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f360b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f360b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f360b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557eca4ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (970 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ccfec256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ccfebf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ccfec2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd91df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd91df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd91df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd91df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ccfe5823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ccfe58086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ccfe3cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ccfaec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ccfaebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd91df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd91df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd91df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ccfaebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e127ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e127ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e127edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd70e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd70e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd70e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd70e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e1278323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e12783086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e12767f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e12417166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e12416e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd70e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd70e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd70e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e12416d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e8aeb656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e8aeb3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e8aeb6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9b541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9b54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9b541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9b5403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e8ae4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e8ae4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e8ae30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e8aae0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e8aadfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff9b5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9b54050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9b54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e8aadfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2be96c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b2be969505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b2be96ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bef049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bef0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bef049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bef031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2be90223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b2be902086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b2be8e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b2be596166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b2be595e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5bef032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bef0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bef0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2be595d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1a4b8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b1a4b84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b1a4b87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8132333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f813238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8132333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f813231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1a4b1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b1a4b1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b1a4b01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b1a47b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b1a47b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f813231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f813231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f813231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1a47b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be5232e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be5232b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be5232ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3650849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3650849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3650831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be522c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be522c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be522a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be51f58166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be51f57e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3650832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36508330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be51f57d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (976 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i)
# |   %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8>
# |   store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i)
# |   %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i)
# |   %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8>
# |   store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i)
# |   %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055e3db0c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e3db0c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e3db0c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4288249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42882a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4288249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4288231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3db05c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e3db05c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3db040f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e3dacf0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e3dacefe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4288232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42882330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42882330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3dacefd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637ac2d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637ac2d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637ac2d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a17a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a17aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a17a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a17a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637ac26d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005637ac26d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005637ac251f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005637abf01166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005637abf00e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a17a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a17a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a17a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637abf00d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b851d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b851d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b851d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9873449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9873449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9873431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b8516b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b8516b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b8514ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b84dff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b84dfee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9873432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98734330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b84dfed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test
# | ...
# `---data was truncated (10240/156773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639d3e5b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639d3e58505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639d3e5bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77fb905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77fb95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77fb905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77fb8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639d3df123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639d3df1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639d3dd5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639d3a85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639d3a84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f77fb8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77fb8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77fb8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639d3a84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba64ba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fba64b7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fba64bacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bcd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bcd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bcd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bcd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba645023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fba6450086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fba6434f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fba60e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fba60e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0bcd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bcd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bcd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba60e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (981 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579933f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579933f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579933f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ff4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ff498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ff4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ff491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055799338923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557993389086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055799336df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055799301d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055799301ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ff491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ff491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ff491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055799301cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056100278a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561002787505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056100278acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9429f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9429f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9429f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9429f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056100272023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561002720086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561002704f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005610023b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005610023b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9429f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9429f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9429f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610023b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d43dc956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d43dc6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d43dc9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6acac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6acaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6acac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6acac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d43d5f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d43d5f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d43d43f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d439f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d439f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6acac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6acac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6acac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d439f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_viota_m_u16m4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_viota_m_u16m8(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/40411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644c44f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005644c44ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005644c44f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01b6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01b66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01b6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01b6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644c448723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005644c4487086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005644c446bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005644c411b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005644c411ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f01b6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01b66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01b66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644c411ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/235596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056191170a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561911707505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056191170acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb90f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb90f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb90f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb90f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619116a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005619116a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561911684f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561911334166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561911333e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdb90f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb90f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb90f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561911333d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (986 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 0)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 90)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_2(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 180)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_3(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 270)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 0)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 90)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale
# | ...
# `---data was truncated (10240/21122) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d90dabc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d90dab9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d90dabccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28c6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28c6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28c6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28c6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d90da5223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d90da52086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d90da36f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d90d6e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d90d6e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f28c6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28c6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28c6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d90d6e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba441d256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba441cf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba441d2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1146b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1146b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1146b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1146b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba4416823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba44168086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba4414cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba43dfc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba43dfbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1146b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1146b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1146b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba43dfbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563c352456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563c3521505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563c3524cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a53b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a53b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a53b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a53b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563c34ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005563c34ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005563c349ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005563c314e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005563c314de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a53b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a53b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a53b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563c314dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec346ca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ec346c7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ec346cacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f281a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f281a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f281a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f281a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec3466023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ec34660086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ec34644f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ec342f4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ec342f3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f281a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f281a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f281a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec342f3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f5b05756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f5b054505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f5b057cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd56c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd56c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd56c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd56c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f5afed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f5afed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f5afd1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f5ac81166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f5ac80e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd56c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd56c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd56c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f5ac80d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (991 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpand_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svexpand_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpand_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, al
# | ...
# `---data was truncated (10240/12168) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fe7abd656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fe7abd3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fe7abd6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f565c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f565c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f565c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f565c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe7ab6c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fe7ab6c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fe7ab50f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fe7a800166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fe7a7ffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f565c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f565c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f565c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe7a7ffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (992 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <4 x bfloat>, ptr %__promote, align 8
# |   store <4 x bfloat> %1, ptr %__ret, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %2, ptr %tmp, align 8
# |   %3 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x bfloat>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %low.addr = alloca <4 x bfloat>, align 8
# |   %high.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %low, ptr %low.addr, align 8
# |   store <4 x bfloat> %high, ptr %high.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %low.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %high.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x bfloat>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1, align 8
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x bfloat>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1, align 16
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c8a1b3456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c8a1b31505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c8a1b34cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dd5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dd58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dd5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dd5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8a1aca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c8a1aca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c8a1aaef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c8a175e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c8a175de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7dd5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dd58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dd58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8a175dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbfac8456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fbfac81505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fbfac84cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f80e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f80e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f80e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f80e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbfac1a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fbfac1a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fbfabfef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fbfa8ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fbfa8ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5f80e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f80e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f80e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbfa8add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d0acc256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d0acbf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d0acc2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8eec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8eec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8eec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8eec91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d0ac5823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d0ac58086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d0ac3cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d0a8ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d0a8ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8eec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8eec91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8eec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d0a8ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056230baeb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056230bae8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056230baebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f477341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47734725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f477341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4773403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056230ba8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056230ba81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056230ba65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056230b715166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056230b714e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4773404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47734050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47734050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056230b714d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d34ddf056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d34dded505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d34ddf0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f5e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f5e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f5e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f5e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d34dd8623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d34dd86086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d34dd6af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d34da1a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d34da19e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f5e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f5e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f5e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d34da19d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0,
# | ...
# `---data was truncated (10240/69839) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563326fe656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563326fe3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563326fe6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd34a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd34aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd34a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd34a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563326f7c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563326f7c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563326f60f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563326c10166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563326c0fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd34a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd34a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd34a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563326c0fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0, i64 %2)
# | ...
# `---data was truncated (10240/69831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9444b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b9444b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b9444b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4832c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4832ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4832c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4832c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b94444c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b94444c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b944430f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9440e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9440dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4832c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4832c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4832c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9440dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i6
# | ...
# `---data was truncated (10240/67158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a1d1ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a1d1ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a1d1aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50b9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50b94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50b9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50b9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a1d14423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a1d144086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a1d128f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a1cdd8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a1cdd7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f50b9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50b94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50b94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a1cdd7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (1000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcreate_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %2, <vscale x 4 x bfloat> %1, i64 4)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %4, <vscale x 4 x bfloat> %1, i64 4)
# |   %6 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %5, <vscale x 4 x bfloat> %2, i64 8)
# |   %7 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %6, <vscale x 4 x bfloat> %3, i64 12)
# |   ret <vscale x 16 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v4.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v5.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v6.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v7.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x bfloat> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x bfloat> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x bfloat> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x bfloat> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x bfloat>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x bfloat>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x bfloat>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x bfloat>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %9 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %8, <vscale x 4 x bfloat> %1, i64 4)
# |   %10 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %9, <vscale x 4 x bfloat> %2, i64 8)
# |   %11 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %10, <vscale x 4 x bfloat> %3, i64 12)
# |   %12 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %11, <vscale x 4 x bfloat> %4, i64 16)
# |   %13 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %12, <vscale x 4 x bfloat> %5, i64 20)
# |   %14 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %13, <vscale x 4 x bfloat> %6, i64 24)
# |   %15 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %14, <vscale x 4 x bfloat> %7, i64 28)
# |   ret <vscale x 32 x bfloat> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %2, <vscale x 8 x bfloat> %1, i64 8)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %4, <vscale x 8 x bfloat> %1, i64 8)
# |   %6 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %5, <vscale x 8 x bfloat> %2, i64 16)
# |   %7 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %6, <vscale x 8 x bfloat> %3, i64 24)
# |   ret <vscale x 32 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m4_bf16m8(<vscale x 16 x bfloat> %v0, <vscale x 16 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %2, <vscale x 16 x bfloat> %1, i64 16)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vcreate_v_bf16mf4x2(<vscale x 1 x bfloat> %v0, <vscale x 1 x bfloat> %v1) #0 {
# | entry:
# |   %v0.add
# | ...
# `---data was truncated (10240/71275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d196f456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559d196f1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559d196f4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ecf21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ecf2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ecf21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ecf203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d1968a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559d1968a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559d1966ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559d1931e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559d1931de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ecf204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ecf2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ecf2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d1931dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (1001 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557d8e69a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557d8e697505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557d8e69acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f983f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f983f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f983f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f983f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d8e63023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557d8e630086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557d8e614f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557d8e2c4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557d8e2c3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f983f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f983f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f983f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d8e2c3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (1002 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d812f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d812f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d812f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38c1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38c1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38c1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38c1e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d8128c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d8128c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d81270f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d80f20166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d80f1fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f38c1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38c1e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38c1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d80f1fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (1003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee1992956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee19926505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee19929cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0385133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f038518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0385133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f038511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee198bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee198bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee198a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee19553166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee19552e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f038511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f038511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f038511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee19552d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (1004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c0a6d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c0a6d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c0a6d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc050449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc050449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc050431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c0a66b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c0a66b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c0a64ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c0a2ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c0a2fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc050432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c0a2fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (1005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055999d73356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055999d730505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055999d733cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5ef849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5ef8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5ef849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5ef831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055999d6c923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055999d6c9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055999d6adf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055999d35d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055999d35ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5ef832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5ef8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5ef8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055999d35cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (1006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b97a04356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b97a040505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b97a043cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66a7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66a715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66a7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66a70ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b979fd923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b979fd9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b979fbdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b979c6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b979c6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f66a70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66a70ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66a70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b979c6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (1007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585f369056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005585f368d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005585f3690cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f990fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f990fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f990fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f990fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585f362623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005585f3626086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005585f360af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005585f32ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005585f32b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f990fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f990fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f990fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585f32b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (1008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src, ptr %src.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %src.addr, align 8
# |   %1 = call <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, i32 1)
# |   ret <vscale x 4 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, <vscale x 4 x i64> %val) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %val.addr = alloca <vscale x 4 x i64>, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, ptr %dest.addr, align 8
# |   store <vscale x 4 x i64> %val, ptr %val.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %dest.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %val.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, <vscale x 4 x i64> %1, i32 1)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), <vscale x 4 x i64>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637ef22556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637ef222505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637ef225cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f071701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07170725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f071701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0717003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637ef1bb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005637ef1bb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005637ef19ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005637eee4f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005637eee4ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0717004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07170050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07170050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637eee4ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (1009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557721f0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557721eff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557721f02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb09b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb09b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb09b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb09b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557721e9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557721e98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557721e7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557721b2c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557721b2be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb09b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb09b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb09b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557721b2bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (1010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b23491756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b234914505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b234917cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0f2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0f2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0f2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0f2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2348ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b2348ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b234891f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b234541166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b234540e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa0f2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0f2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0f2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b234540d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (1011 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 29, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 30, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005642afcfd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005642afcfa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005642afcfdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f2fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f2fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f2fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f2fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642afc9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005642afc93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005642afc77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005642af927166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005642af926e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f2fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f2fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f2fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642af926d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (1012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e3418556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e34182505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e34185cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3914a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3914aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3914a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3914a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e3411b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e3411b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e340fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e33daf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e33daee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3914a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3914a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3914a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e33daed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (1013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 
# | ...
# `---data was truncated (10240/117397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad864b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad864b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad864b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b19649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b196a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b19649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b19631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad8644a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad8644a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad8642ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad860de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad860dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b19632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b196330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b196330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad860ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (1014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ffa68456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555ffa681505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555ffa684cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde7da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde7daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde7da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde7da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ffa61a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555ffa61a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555ffa5fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555ffa2ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555ffa2ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde7da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde7da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde7da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ffa2add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (1015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615b14db56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615b14d8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615b14dbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3440f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3440f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3440f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3440eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615b147123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615b1471086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615b1455f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615b1105166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615b1104e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3440eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3440eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3440eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615b1104d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (1016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/79671) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d80341a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d803417505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d80341acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a1c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a1c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a1c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a1c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8033b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8033b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d803394f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d803044166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d803043e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0a1c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a1c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a1c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d803043d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (1017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.
# | ...
# `---data was truncated (10240/28427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e67cf8956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e67cf86505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e67cf89cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f529e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f529e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f529e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f529e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e67cf1f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e67cf1f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e67cf03f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e67cbb3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e67cbb2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f529e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f529e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f529e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e67cbb2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (1018 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dd6b0156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557dd6afe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557dd6b01cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f182d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f182d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f182d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f182d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dd6a9723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557dd6a97086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557dd6a7bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557dd672b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557dd672ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f182d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f182d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f182d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dd672ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (1019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6f557356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6f5570505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6f5573cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff60e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff60e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff60e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff60e0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6f550923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6f5509086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6f54edf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6f519d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6f519ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff60e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff60e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff60e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6f519cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (1020 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc7a2c856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc7a2c5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc7a2c8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd330133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd33018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd330133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd33011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc7a25e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc7a25e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc7a242f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc79ef2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc79ef1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd33011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd33011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd33011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc79ef1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (1021 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637c8af556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637c8af2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637c8af5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3631733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f363178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3631733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f363171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637c8a8b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005637c8a8b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005637c8a6ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005637c871f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005637c871ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f363171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f363171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f363171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637c871ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (1022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e8e02356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556e8e020505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556e8e023cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77b2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77b24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77b2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77b2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e8dfb923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556e8dfb9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556e8df9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556e8dc4d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556e8dc4ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f77b2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77b24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77b24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e8dc4cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (1023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9da75056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d9da74d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d9da750cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5af61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5af6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5af61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5af603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9da6e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9da6e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9da6caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9da37a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9da379e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd5af604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5af6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5af6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9da379d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (1024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637712d256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637712cf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637712d2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17bf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17bf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17bf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17bf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056377126823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563771268086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056377124cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563770efc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563770efbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f17bf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17bf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17bf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563770efbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (1025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/223809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f033da956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f033da6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f033da9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a72333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a7238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a72333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a7231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f033d3f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f033d3f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f033d23f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f0339d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f0339d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a7231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a7231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a7231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0339d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (1026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d0caa156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d0ca9e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d0caa1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfdac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfdaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfdac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfdac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d0ca3723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d0ca37086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d0ca1bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d0c6cb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d0c6cae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcfdac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfdac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfdac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d0c6cad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (1027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055673073e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055673073b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055673073ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe8081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe808725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe8081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe80803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567306d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005567306d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005567306b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556730368166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556730367e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbe80804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe808050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe808050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556730367d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (1028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/60817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593717f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005593717f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005593717f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafe5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafe5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafe5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafe5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055937178923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559371789086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055937176df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055937141d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055937141ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fafe5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafe5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafe5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055937141cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (1029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a71cde356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a71cde0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a71cde3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eed249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eed2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eed249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eed231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a71cd7923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a71cd79086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a71cd5df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a71ca0d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a71ca0ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2eed232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eed2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eed2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a71ca0cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (1030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x 
# | ...
# `---data was truncated (10240/292007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056375d18756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056375d184505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056375d187cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd68305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd6835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd68305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd682ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056375d11d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056375d11d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056375d101f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056375cdb1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056375cdb0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd682eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd682ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd682ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056375cdb0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (1031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619fb3af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005619fb3ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005619fb3afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f362f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f362f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f362f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f362f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619fb34523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005619fb345086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005619fb329f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005619fafd9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005619fafd8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f362f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f362f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f362f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619fafd8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (1032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d10678556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d106782505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d106785cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e13e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e13ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e13e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e13e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d10671b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d10671b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d1066fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d1063af166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d1063aee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e13e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e13e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e13e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1063aed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (1033 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623bec0956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005623bec06505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005623bec09cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ab4105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ab415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ab4105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ab40ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623beb9f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005623beb9f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005623beb83f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005623be833166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005623be832e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ab40eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ab40ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ab40ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623be832d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (1034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_and_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.and
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_or_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.or
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_xor_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.xor
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smax_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smin_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umax_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umin_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmax_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmin_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmaximum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.maximum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fminimum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.minimum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32_m8(<vscale x 16 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i32>, align 4
# |   store <vscale x 16 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 16 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @reduce_add_i64(<vscale x 1 x i64> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 1 x i64>, align 8
# |   store <vscale x 1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %a.addr, align 8
# |   %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %0)
# |   ret i64 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_mul_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.mul
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055f11291f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f11291c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f11291fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bd2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bd2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bd2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bd2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1128b523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f1128b5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f112899f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f112549166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f112548e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1bd2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bd2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bd2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f112548d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (1035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %
# | ...
# `---data was truncated (10240/21774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056332bf3f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056332bf3c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056332bf3fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9698f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9698f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9698f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9698f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056332bed523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056332bed5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056332beb9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056332bb69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056332bb68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9698f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9698f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9698f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056332bb68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (1036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e5419256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555e5418f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555e54192cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2d1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2d1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2d1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2d1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e5412823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555e54128086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555e5410cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555e53dbc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555e53dbbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd2d1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2d1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2d1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e53dbbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (1037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621e94a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005621e94a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005621e94a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8317249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83172a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8317249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8317231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621e943c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005621e943c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005621e9420f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005621e90d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005621e90cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8317232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83172330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83172330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621e90cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (1038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed4887456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed48871505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed48874cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3044533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f304458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3044533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f304451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed4880a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed4880a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed487eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed4849e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed4849de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f304451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f304451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f304451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed4849dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (1039 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5fdb3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5fdb2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5fdb31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11ea533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11ea58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11ea533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11ea51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5fdac723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5fdac7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5fdaabf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5fd75b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5fd75ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f11ea51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11ea51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11ea51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5fd75ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (1040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570bfd9356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005570bfd90505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005570bfd93cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3265133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f326518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3265133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f326511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570bfd2923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570bfd29086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570bfd0df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570bf9bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570bf9bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f326511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f326511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f326511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570bf9bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (1041 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e14c6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564e14c65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564e14c68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb5df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e14bfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564e14bfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564e14be2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564e14892166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564e14891e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdb5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e14891d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (1042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055656482b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556564828505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055656482bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78ece1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78ece725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78ece1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78ece03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565647c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565647c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565647a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556564455166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556564454e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78ece04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78ece050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78ece050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556564454d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (1043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   
# | ...
# `---data was truncated (10240/92362) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612d9d4b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005612d9d48505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005612d9d4bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdee1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdee138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdee1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdee131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612d9ce123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005612d9ce1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005612d9cc5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005612d9975166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005612d9974e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdee131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdee131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdee131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612d9974d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (1044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055786f60e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055786f60b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055786f60ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2e8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2e8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2e8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2e8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055786f5a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055786f5a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055786f588f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055786f238166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055786f237e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2e8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2e8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2e8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055786f237d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (1045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e44ca4956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e44ca46505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e44ca49cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd157a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd157aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd157a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd157a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e44c9df23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e44c9df086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e44c9c3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e44c673166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e44c672e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd157a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd157a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd157a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e44c672d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (1046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg
# | ...
# `---data was truncated (10240/20531) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a4d41c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564a4d419505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564a4d41ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd339305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd33935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd339305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3392ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a4d3b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564a4d3b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564a4d396f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564a4d046166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564a4d045e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd3392eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3392ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3392ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a4d045d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (1047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603a6b5756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603a6b54505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603a6b57cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcd4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcd498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcd4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcd491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603a6aed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005603a6aed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005603a6ad1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005603a6781166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005603a6780e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efcd491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcd491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcd491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603a6780d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (1048 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/201234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cdd9dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cdd9d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cdd9dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb953f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb953f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb953f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb953f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cdd97223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cdd972086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cdd956f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cdd606166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cdd605e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb953f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb953f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb953f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cdd605d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (1049 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %w.addr = alloca float, align 4
# |   store float %w, ptr %w.addr, align 4
# |   %0 = load float, ptr %w.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %1, i32 0
# |   %2 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1
# |   %3 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2
# |   %4 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %5 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   store <4 x float> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 {
# | entry:
# |   %V.addr = alloca <1 x double>, align 8
# |   %__ret_379 = alloca <2 x double>, align 16
# |   %__s0_379 = alloca <1 x double>, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   %tmp1 = alloca <2 x double>, align 16
# |   store <1 x double> %V, ptr %V.addr, align 8
# |   %0 = load <1 x double>, ptr %V.addr, align 8
# |   store <1 x double> %0, ptr %__s0_379, align 8
# |   %1 = load <1 x double>, ptr %__s0_379, align 8
# |   store <1 x double> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer
# |   store <2 x double> %lane, ptr %ref.tmp, align 16
# |   %4 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %4, ptr %__ret, align 16
# |   %5 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %5, ptr %tmp, align 16
# |   %6 = load <2 x double>, ptr %tmp, align 16
# |   store <2 x double> %6, ptr %__ret_379, align 16
# |   %7 = load <2 x double>, ptr %__ret_379, align 16
# |   store <2 x double> %7, ptr %tmp1, align 16
# |   %8 = load <2 x double>, ptr %tmp1, align 16
# |   ret <2 x double> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %6 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %6, ptr %__ret, align 8
# |   %7 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %7, ptr %tmp, align 8
# |   %8 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6
# |   %9 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %10 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %10, ptr %__ret, align 16
# |   %11 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %11, ptr %tmp, align 16
# |   %12 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %12
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005590edd5856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005590edd55505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005590edd58cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe703905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe70395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe703905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7038ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590edcee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005590edcee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005590edcd2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005590ed982166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005590ed981e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe7038eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7038ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7038ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590ed981d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (1050 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593225af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005593225ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005593225afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26bec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26bec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26bec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26bec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055932254523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559322545086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559322529f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005593221d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005593221d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f26bec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26bec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26bec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593221d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (1051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639ce68e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639ce68b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639ce68ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1ad533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1ad58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1ad533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1ad51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639ce62423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639ce624086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639ce608f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639ce2b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639ce2b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe1ad51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1ad51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1ad51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639ce2b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (1052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c930a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560c930a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560c930a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3256f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3256f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3256f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3256f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c9303923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560c93039086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560c9301df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560c92ccd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560c92ccce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3256f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3256f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3256f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c92cccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mfp8.c (1053 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 {
# | entry:
# |   %mfp8.addr = alloca <1 x i8>, align 1
# |   %f1n = alloca [10 x <1 x i8>], align 1
# |   store <1 x i8> %mfp8, ptr %mfp8.addr, align 1
# |   %0 = load <1 x i8>, ptr %mfp8.addr, align 1
# |   %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   store <1 x i8> %0, ptr %arrayidx, align 1
# |   %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   %1 = load <1 x i8>, ptr %arrayidx1, align 1
# |   ret <1 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   ret <1 x i8> %mfp8ext
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   %v.addr = alloca <1 x i8>, align 1
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   store <1 x i8> %v, ptr %v.addr, align 1
# |   %0 = load <1 x i8>, ptr %v.addr, align 1
# |   %1 = load i32, ptr %i.addr, align 4
# |   %2 = load <16 x i8>, ptr %x.addr, align 16
# |   %3 = bitcast <1 x i8> %0 to i8
# |   %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1
# |   store <16 x i8> %vecins, ptr %x.addr, align 16
# |   %4 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# |  #0 0x0000559239d7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559239d72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559239d75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5212c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5212ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5212c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5212c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559239d0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559239d0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559239ceff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055923999f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055923999ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5212c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5212c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5212c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055923999ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (1054 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579453cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579453c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579453cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c1eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c1eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c1eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c1eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055794536123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557945361086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557945345f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557944ff5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557944ff4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c1eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c1eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c1eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557944ff4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/aapcs-bitfield.c (1055 of 27911)
******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-eabi"
# | 
# | %struct.st6 = type { i16, i8, i8 }
# | %struct.st7b = type { i8, [3 x i8], %struct.st7a }
# | %struct.st7a = type { i8, i8, [2 x i8] }
# | %struct.st11 = type <{ i8, i16, i8 }>
# | %struct.st13 = type <{ i8, i32 }>
# | %struct.st16 = type { i32, i16, i32, i16 }
# | %struct.st17 = type <{ i32, i8 }>
# | %struct.zero_bitfield = type { i8, i8, [2 x i8] }
# | %struct.zero_bitfield_ok = type { i16, i32 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st0_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st0_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st1_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.ashr = ashr i16 %bf.load, 10
# |   %conv = sext i16 %bf.ashr to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st1_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, 1023
# |   %bf.set = or i16 %bf.clear, 1024
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st2_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 9
# |   %bf.ashr = ashr i32 %bf.shl, 25
# |   %bf.cast = trunc i32 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st2_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -8323073
# |   %bf.set = or i32 %bf.clear, 65536
# |   store i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st3_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st3_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store volatile i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st4_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 2
# |   %bf.ashr = ashr i16 %bf.shl, 11
# |   %bf.cast = trunc i16 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -15873
# |   %bf.set = or i16 %bf.clear, 512
# |   store volatile i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -512
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st5_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 11
# |   %bf.ashr = ashr i32 %bf.shl, 27
# |   %bf.cast = trunc i32 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st5_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -2031617
# |   %bf.set = or i32 %bf.clear, 65536
# |   store volatile i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st6_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %x = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 4
# |   %bf.ashr = ashr i16 %bf.shl, 4
# |   %bf.cast = sext i16 %bf.ashr to i32
# |   store i32 %bf.cast, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   %2 = load volatile i8, ptr %b, align 2
# |   %conv = sext i8 %2 to i32
# |   %3 = load i32, ptr %x, align 4
# |   %add = add nsw i32 %3, %conv
# |   store i32 %add, ptr %x, align 4
# |   %4 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2
# |   %bf.load1 = load volatile i8, ptr %c, align 1
# |   %bf.shl2 = shl i8 %bf.load1, 3
# |   %bf.ashr3 = ashr i8 %bf.shl2, 3
# |   %bf.cast4 = sext i8 %bf.ashr3 to i32
# |   %5 = load i32, ptr %x, align 4
# |   %add5 = add nsw i32 %5, %bf.cast4
# |   store i32 %add5, ptr %x, align 4
# |   %6 = load i32, ptr %x, align 4
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st6_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -4096
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   store i8 2, ptr %b, align 2
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2
# |   %bf.load1 = load i8, ptr %c, align 1
# |   %bf.clear2 = and i8 %bf.load1, -32
# |   %bf.set3 = or i8 %bf.clear2, 3
# |   store i8 %bf.set3, ptr %c, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st7_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %r = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   %1 = load i8, ptr %x, align 4
# |   %conv = sext i8 %1 to i32
# |   store i32 %conv, ptr %r, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   %3 = load volatile i8, ptr %a, align 4
# |   %conv1 = sext i8 %3 to i32
# |   %4 = load i32, ptr %r, align 4
# |   %add = add nsw i32 %4, %conv1
# |   store i32 %add, ptr %r, align 4
# |   %5 = load ptr, ptr %m.addr, align 4
# |   %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.shl = shl i8 %bf.load, 3
# |   %bf.ashr = ashr i8 %bf.shl, 3
# |   %bf.cast = sext i8 %bf.ashr to i32
# |   %6 = load i32, ptr %r, align 4
# |   %add3 = add nsw i32 %6, %bf.cast
# |   store i32 %add3, ptr %r, align 4
# |   %7 = load i32, ptr %r, align 4
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st7_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   store i8 1, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   store volatile i8 2, ptr %a, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.clear = and i8 %bf.load, -32
# |   %bf.set = or i8 %bf.clear, 3
# |   store volatile i8 %bf.set, ptr %b, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   store i16 -1, ptr %0, align 4
# |   ret i32 65535
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @read_st9(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 4
# |   %bf.cast = sext i8 %bf.load to i32
# |   r
# | ...
# `---data was truncated (10240/24998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624b934c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005624b9349505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005624b934ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a0a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a0a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a0a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a0a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624b92e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005624b92e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005624b92c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005624b8f76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005624b8f75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a0a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a0a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a0a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624b8f75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (1056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d6a55856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d6a555505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d6a558cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07ab649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07ab6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07ab649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07ab631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d6a4ee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d6a4ee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d6a4d2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d6a182166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d6a181e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f07ab632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07ab6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07ab6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d6a181d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (1057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nx
# | ...
# `---data was truncated (10240/83629) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b28cb156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561b28cae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561b28cb1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5026705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f502675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5026705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50266ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b28c4723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561b28c47086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561b28c2bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561b288db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561b288dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f50266eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50266ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50266ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b288dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (1058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/88436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7e231a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c7e2317505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c7e231acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ffe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ffe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ffe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ffe71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7e22b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c7e22b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c7e2294f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c7e1f44166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c7e1f43e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6ffe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ffe71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ffe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7e1f43d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (1059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b5797d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562b5797a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562b5797dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f866ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f866ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f866ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f866feed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b5791323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562b57913086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562b578f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562b575a7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562b575a6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f866feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f866feef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f866feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b575a6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (1060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fc8f0c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555fc8f09505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555fc8f0ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25fd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fc8ea223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555fc8ea2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555fc8e86f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555fc8b36166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555fc8b35e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f25fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25fd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fc8b35d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (1061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644b316456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005644b3161505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005644b3164cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f959e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f959e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f959e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f959e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644b30fa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005644b30fa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005644b30def39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005644b2d8e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005644b2d8de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f959e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f959e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f959e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644b2d8dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (1062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c9f4da56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c9f4d7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c9f4dacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3142649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31426a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3142649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3142631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c9f47023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c9f470086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c9f454f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c9f104166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c9f103e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3142632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31426330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31426330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c9f103d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (1063 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofre
# | ...
# `---data was truncated (10240/183431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f41af3356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f41af30505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f41af33cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3843d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3843d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3843d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3843d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f41aec923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f41aec9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f41aeadf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f41ab5d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f41ab5ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3843d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3843d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3843d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f41ab5cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (1064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b05de056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561b05ddd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561b05de0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1de1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1de1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1de1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1de1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b05d7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561b05d76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561b05d5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561b05a0a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561b05a09e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1de1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1de1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1de1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b05a09d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (1065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bf9d5256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555bf9d4f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555bf9d52cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4e9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4e9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4e9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4e9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bf9ce823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555bf9ce8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555bf9cccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555bf997c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555bf997be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc4e9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4e9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4e9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bf997bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (1066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dbecf156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563dbecee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563dbecf1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a88a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a88aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a88a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a88a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dbec8723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563dbec87086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563dbec6bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563dbe91b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563dbe91ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a88a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a88a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a88a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dbe91ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (1067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587717d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587717d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587717d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0ed849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0ed8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0ed849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0ed831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055877176b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055877176b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055877174ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005587713ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005587713fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0ed832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0ed8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0ed8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587713fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (1068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ed5fc456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ed5fc1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ed5fc4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce97533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce9758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce97533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce9751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ed5f5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ed5f5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ed5f3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ed5bee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ed5bede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce9751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce9751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce9751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ed5bedd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (1069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565131e0356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565131e00505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565131e03cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6d8305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6d835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6d8305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6d82ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565131d9923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565131d99086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565131d7df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565131a2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565131a2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa6d82eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6d82ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6d82ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565131a2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (1070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a57f2e256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a57f2df505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a57f2e2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b5d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b5d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b5d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b5d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a57f27823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a57f278086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a57f25cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a57ef0c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a57ef0be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b5d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b5d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b5d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a57ef0bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (1071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vs
# | ...
# `---data was truncated (10240/210427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b403fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b403f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b403facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f17c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f17ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f17c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f17c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b4039023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b40390086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b40374f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b40024166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b40023e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f17c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f17c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f17c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b40023d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (1072 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6)
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6)
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__p1.addr.i.i = alloca <4 x half>, align 8
# |   %__p2.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %13, ptr %__ret.i.i, align 8
# |   %14 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <8 x half>, align 16
# |   %__p1.addr.i.i = alloca <8 x half>, align 16
# |   %__p2.addr.i.i = alloca <8 x half>, align 16
# |   %__ret.i.i = alloca <8 x half>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i.i, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i.i, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16
# |   store <8 x half> %13, ptr %__ret.i.i, align 16
# |   %14 = load <8 x half>, ptr %__ret.i.i, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1)
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1
# | ...
# `---data was truncated (10240/42739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056341731f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056341731c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056341731fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54e6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54e618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54e6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54e611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634172b523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634172b5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563417299f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563416f49166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563416f48e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f54e611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54e611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54e611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563416f48d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (1073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf4_f16(<vscale x 1 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf2_f16(<vscale x 2 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m1_f16(<vscale x 4 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m2_f16(<vscale x 8 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m4_f16(<vscale x 16 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m8_f16(<vscale x 32 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32mf2_f32(<vscale x 1 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m1_f32(<vscale x 2 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m2_f32(<vscale x 4 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m4_f32(<vscale x 8 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m8_f32(<vscale x 16 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m1_f64(<vscale x 1 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m2_f64(<vscale x 2 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m4_f64(<vscale x 4 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m8_f64(<vscale x 8 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1c810256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a1c80ff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a1c8102cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd76f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd76f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd76f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd76eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1c809823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a1c8098086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a1c807cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a1c7d2c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a1c7d2be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd76eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd76eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd76eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1c7d2bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (1074 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_u8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_u16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_u32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_u64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_s8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_s16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_s32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_s64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbxq_f16(<vscale x 8 x half> %passthru, <vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbxq_f32(<vscale x 4 x float> %passthru, <vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.tbxq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/14102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005602a0b0456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005602a0b01505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005602a0b04cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b4ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b4ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b4ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b4ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602a0a9a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005602a0a9a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005602a0a7ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005602a072e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005602a072de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1b4ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b4ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b4ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602a072dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (1075 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e2f7ae556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2f7ae2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2f7ae5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18c8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18c898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18c8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18c891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2f7a7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2f7a7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2f7a5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2f770f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2f770ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f18c891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18c891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18c891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2f770ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (1076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea4196d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea4196a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea4196dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0135533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f013558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0135533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f013551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea4190323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea41903086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea418e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea41597166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea41596e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f013551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f013551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f013551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea41596d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (1077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635d4a9e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005635d4a9b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005635d4a9ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe55a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe55a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe55a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe55a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635d4a3423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005635d4a34086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005635d4a18f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005635d46c8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005635d46c7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe55a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe55a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe55a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635d46c7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (1078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale
# | ...
# `---data was truncated (10240/70021) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bca48a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bca489f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bca48a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22aab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22aab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22aab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22aab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bca483823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bca4838086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bca481cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bca44cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bca44cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22aab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22aab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22aab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bca44cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (1079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e365d4856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e365d45505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e365d48cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a5da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a5daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a5da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a5da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e365cde23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e365cde086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e365cc2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e365972166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e365971e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a5da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a5da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a5da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e365971d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (1080 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcd797756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fcd7974505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fcd7977cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1b1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcd790d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fcd790d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fcd78f1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fcd75a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fcd75a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc1b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcd75a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (1081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/94157) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6e9d1a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f6e9d17505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f6e9d1acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fad649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fad6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fad649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fad631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6e9cb023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f6e9cb0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f6e9c94f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f6e9944166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f6e9943e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5fad632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fad6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fad6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6e9943d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (1082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d140a6e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d140a6b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d140a6ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2c101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2c10725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2c101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2c1003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d140a0423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d140a04086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d1409e8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d140698166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d140697e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2c1004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2c10050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2c10050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d140697d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (1083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb84b5756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb84b54505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb84b57cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d0c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d0c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d0c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d0c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb84aed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb84aed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb84ad1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb84781166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb84780e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6d0c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d0c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d0c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb84780d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (1084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c673c956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c673c6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c673c9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f207aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f207aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f207aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f207aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c6735f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c6735f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c67343f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c66ff3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c66ff2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f207aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f207aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f207aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c66ff2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (1085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573fabdb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005573fabd8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005573fabdbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1e3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1e3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1e3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1e3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573fab7123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005573fab71086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005573fab55f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005573fa805166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005573fa804e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc1e3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1e3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1e3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573fa804d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (1086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056401eefc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056401eef9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056401eefccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6706649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67066a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6706649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6706631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056401ee9223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056401ee92086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056401ee76f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056401eb26166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056401eb25e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6706632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67066330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67066330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056401eb25d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (1087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a04bd956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a04bd6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a04bd9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2f2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2f2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2f2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2f2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a04b6f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a04b6f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a04b53f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a04803166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a04802e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2f2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2f2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2f2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a04802d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (1088 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %
# | ...
# `---data was truncated (10240/93831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556b7548d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b7548a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b7548dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea10b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea10b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea10b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea10b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b7542323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b75423086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b75407f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b750b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b750b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fea10b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea10b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea10b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b750b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (1089 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/121927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2bf0fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d2bf0f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d2bf0fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f943d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f943d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f943d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f943d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2bf09223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d2bf092086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d2bf076f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2bed26166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2bed25e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f943d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f943d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f943d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2bed25d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (1090 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a1214d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a1214a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a1214dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b3f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b3f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b3f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b3f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a120e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a120e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a120c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a11d77166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a11d76e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1b3f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b3f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b3f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a11d76d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (1091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x 
# | ...
# `---data was truncated (10240/70013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055838ce5b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055838ce58505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055838ce5bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a1f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a1f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a1f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a1f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055838cdf123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055838cdf1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055838cdd5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055838ca85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055838ca84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a1f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a1f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a1f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055838ca84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (1092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/87191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628f811356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005628f8110505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005628f8113cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7e3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7e398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7e3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7e391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628f80a923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005628f80a9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005628f808df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005628f7d3d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005628f7d3ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa7e391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7e391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7e391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628f7d3cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (1093 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0)
# |   %2 = extractvalue { <8 x half>, <8 x half> } %1, 0
# |   %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0
# |   %4 = extractvalue { <8 x half>, <8 x half> } %1, 1
# |   %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1
# |   ret %struct.float16x8x2_t %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0)
# |   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
# |   %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0
# |   %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
# |   %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1
# |   %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
# |   %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2
# |   %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
# |   %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3
# |   ret %struct.uint8x16x4_t %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.uint32x4x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.uint32x4x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0
# |   store [2 x <4 x i32>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0
# |   %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.int8x16x4_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.int8x16x4_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0
# |   store [4 x <16 x i8>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false)
# |   %3 = load %struct.int8x16x4_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.int8x16x4_t %3, 0, 0
# |   %5 = extractvalue %struct.int8x16x4_t %3, 0, 1
# |   %6 = extractvalue %struct.int8x16x4_t %3, 0, 2
# |   %7 = extractvalue %struct.int8x16x4_t %3, 0, 3
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.float16x8x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.float16x8x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0
# |   store [2 x <8 x half>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.float16x8x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.float16x8x2_t %3, 0, 0
# |   %5 = extractvalue %struct.float16x8x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %values.addr = alloca ptr, align 4
# |   %v = alloca %struct.uint16x8x2_t, align 8
# |   %tmp = alloca %struct.uint16x8x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %values, ptr %values.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0)
# |   %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0
# |   %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0
# |   %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1
# |   %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1
# |   store %struct.uint16x8x2_t %5, ptr %tmp, align 8
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false)
# |   %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0
# |   %6 = load <8 x i16>, ptr %arrayidx, align 8
# |   %7 = load ptr, ptr %values.addr, align 4
# |   %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0
# |   store <8 x i16> %6, ptr %arrayidx1, align 8
# |   %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1
# |   %8 = load <8 x i16>, ptr %arrayidx3, align 8
# |   %9 = load ptr, ptr %values.addr, align 4
# |   %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1
# |   store <8 x i16> %8, ptr %arrayidx4, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %ref.tmp = alloca %struct.int32x4x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0)
# |   %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0
# |   %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1
# |   %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1
# |   store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8
# |   %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0
# |   %6 = load <4 x i32>, ptr %arrayidx, align 8
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x00005593a370f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005593a370c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005593a370fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5ae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5ae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5ae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5ae71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593a36a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005593a36a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005593a3689f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005593a3339166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005593a3338e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5ae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5ae71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5ae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593a3338d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (1094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0843cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b0843c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b0843cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc476533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc47658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc476533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc47651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b08436223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b084362086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b084346f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b083ff6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b083ff5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc47651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc47651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc47651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b083ff5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (1095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/68247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557607be556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557607be2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557607be5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d3f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d3f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d3f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d3f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557607b7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557607b7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557607b5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055760780f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055760780ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d3f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d3f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d3f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055760780ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (1096 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.srshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nos
# | ...
# `---data was truncated (10240/11578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a28302356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a283020505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a283023cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff86c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff86c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff86c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff86c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a282fb923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a282fb9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a282f9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a282c4d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a282c4ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff86c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff86c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff86c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a282c4cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (1097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560e925f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005560e925c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005560e925fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a1a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a1a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a1a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a1a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560e91f523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005560e91f5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005560e91d9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005560e8e89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005560e8e88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0a1a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a1a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a1a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560e8e88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (1098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056317c83856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056317c835505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056317c838cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7417d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7417d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7417d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7417d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056317c7ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056317c7ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056317c7b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056317c462166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056317c461e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7417d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7417d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7417d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056317c461d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (1099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cde25c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558cde259505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558cde25ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5430249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54302a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5430249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5430231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cde1f223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558cde1f2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558cde1d6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558cdde86166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558cdde85e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5430232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54302330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54302330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cdde85d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (1100 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = add <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fadd <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = add <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fadd <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000555b4073d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555b4073a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555b4073dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fd5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fd5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fd5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fd5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b406d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555b406d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555b406b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555b40367166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555b40366e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0fd5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fd5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fd5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b40366d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (1101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055702181456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557021811505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557021814cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27e4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27e48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27e4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27e4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570217aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570217aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055702178ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055702143e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055702143de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f27e4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27e48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27e48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055702143dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (1102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a721fba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a721fb7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a721fbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51cc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51cc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51cc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51cc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a721f5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a721f50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a721f34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a721be4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a721be3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f51cc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51cc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51cc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a721be3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (1103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ed040556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563ed0402505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563ed0405cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a5a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a5a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a5a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a5a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ed039b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563ed039b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563ed037ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563ed002f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563ed002ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4a5a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a5a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a5a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ed002ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (1104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651c1ced56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005651c1cea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005651c1cedcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7363649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73636a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7363649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7363631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651c1c8323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651c1c83086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651c1c67f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005651c1917166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005651c1916e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7363632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73636330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73636330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651c1916d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (1105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba4475556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba44752505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba44755cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae25933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae2598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae25933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae2591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba446eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba446eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba446cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba4437f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba4437ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae2591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae2591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae2591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba4437ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (1106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 
# | ...
# `---data was truncated (10240/126436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056554bd3e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056554bd3b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056554bd3ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbb9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbb90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbb9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbb9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056554bcd423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056554bcd4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056554bcb8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056554b968166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056554b967e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdbb9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbb90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbb90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056554b967d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (1107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e3999b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e39998505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e3999bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2149249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21492a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2149249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2149231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e3993123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e39931086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e39915f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e395c5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e395c4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2149232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21492330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21492330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e395c4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (1108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b741ee556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b741ee2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b741ee5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f59133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f5918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f59133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f5911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b741e7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b741e7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b741e5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b741b0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b741b0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f5911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f5911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f5911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b741b0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (1109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a22fa7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a22fa74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a22fa77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e29933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e2998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e29933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e2991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a22fa0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a22fa0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a22f9f1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a22f6a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a22f6a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e2991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e2991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e2991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a22f6a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (1110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a7189156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557a7188e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557a71891cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef30b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef30b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef30b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef30b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a7182723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557a71827086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557a7180bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557a714bb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557a714bae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef30b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef30b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef30b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a714bad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (1111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631d51b056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005631d51ad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005631d51b0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20f2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20f258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20f2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20f251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631d514623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005631d5146086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005631d512af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005631d4dda166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005631d4dd9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f20f251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20f251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20f251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631d4dd9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (1112 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   
# | ...
# `---data was truncated (10240/17536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff838a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ff838a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ff838a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6316049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6316049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6316031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff8383c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ff8383c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ff83820f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ff834d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ff834cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6316032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63160330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff834cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (1113 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = fneg <8 x half> %1
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = fneg <4 x float> %1
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %c, ptr %c.addr, align 2
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = mul <8 x i16> %0, %.splat
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = add <8 x i16> %2, %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i32 %c, ptr %c.addr, align 4
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = mul <4 x i32> %0, %.splat
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = add <4 x i32> %2, %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, ali
# | ...
# `---data was truncated (10240/60411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b7fb26356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b7fb260505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b7fb263cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe772849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7728a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe772849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe772831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7fb1f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b7fb1f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b7fb1ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b7fae8d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b7fae8ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe772832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7728330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7728330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7fae8cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (1114 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005589aedc656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589aedc3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589aedc6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f974f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f974f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f974f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f974f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589aed5c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589aed5c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589aed40f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589ae9f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589ae9efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f974f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f974f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f974f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589ae9efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (1115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055712be8456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055712be81505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055712be84cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff98ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff98ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff98ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff98feed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055712be1a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055712be1a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055712bdfef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055712baae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055712baade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff98feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff98feef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff98feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055712baadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (1116 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055602dc0c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055602dc09505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055602dc0ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08a0305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08a035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08a0305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08a02ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055602dba223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055602dba2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055602db86f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055602d836166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055602d835e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f08a02eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08a02ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08a02ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055602d835d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (1117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d12ae2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d12ae29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d12ae2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61fa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61fa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61fa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61fa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d12adc223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d12adc2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d12ada6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d12aa56166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d12aa55e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61fa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61fa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61fa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d12aa55d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (1118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055601751d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055601751a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055601751dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4210849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42108a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4210849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4210831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560174b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005560174b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556017497f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556017147166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556017146e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4210832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42108330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42108330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556017146d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (1119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563600efb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563600ef8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563600efbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a4f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a4f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a4f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a4f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563600e9123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563600e91086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563600e75f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563600b25166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563600b24e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a4f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a4f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a4f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563600b24d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (1120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056509301856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565093015505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565093018cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2673a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2673aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2673a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2673a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565092fae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565092fae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565092f92f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565092c42166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565092c41e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2673a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2673a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2673a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565092c41d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (1121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd44d7056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd44d6d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd44d70cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd192d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd192d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd192d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd192ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd44d0623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd44d06086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd44ceaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd4499a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd44999e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd192ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd192cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd192cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd44999d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (1122 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 
# | ...
# `---data was truncated (10240/39417) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562723f9156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562723f8e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562723f91cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2025133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f202518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2025133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f202511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562723f2723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562723f27086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562723f0bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562723bbb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562723bbae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f202511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f202511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f202511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562723bbad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (1123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562addd5a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562addd57505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562addd5acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79ab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79ab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79ab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79ab31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562addcf023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562addcf0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562addcd4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562add984166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562add983e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f79ab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79ab31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79ab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562add983d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (1124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576bff2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576bff1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576bff20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e0f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e0f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e0f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e0f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576bfeb623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576bfeb6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576bfe9af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576bfb4a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576bfb49e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5e0f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e0f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e0f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576bfb49d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (1125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581b064b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005581b0648505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005581b064bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f317c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f317c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f317c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f317c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581b05e123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581b05e1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581b05c5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581b0275166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581b0274e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f317c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f317c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f317c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581b0274d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/X86/sse.c (1126 of 27911)
******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c98bc2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c98bc1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c98bc20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa74705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa7475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa74705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa746ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c98bbb623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c98bbb6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c98bb9af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c98b84a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c98b849e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa746eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa746ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa746ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c98b849d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (1127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed3e1fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed3e1f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed3e1facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88b4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88b498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88b4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88b491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed3e19023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed3e190086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed3e174f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed3de24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed3de23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f88b491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88b491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88b491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed3de23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (1128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555aa70c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555aa70c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555aa70c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9314e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9314ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9314e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9314e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555aa705c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555aa705c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555aa7040f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555aa6cf0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555aa6cefe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9314e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9314e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9314e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aa6cefd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (1129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/124036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626586dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005626586d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005626586dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42f7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42f7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42f7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42f7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056265867223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562658672086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562658656f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562658306166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562658305e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42f7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42f7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42f7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562658305d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (1130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bf1b2656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bf1b23505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bf1b26cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24e3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24e3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24e3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24e3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bf1abc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bf1abc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bf1aa0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bf1750166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bf174fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f24e3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24e3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24e3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bf174fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (1131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32
# | ...
# `---data was truncated (10240/75405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557315deb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557315de8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557315debcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1010f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1010f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1010f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1010f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557315d8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557315d81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557315d65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557315a15166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557315a14e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1010f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1010f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1010f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557315a14d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (1132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %sr
# | ...
# `---data was truncated (10240/288111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec7334e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ec7334b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ec7334ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaa3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaa3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaa3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaa3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec732e423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ec732e4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ec732c8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ec72f78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ec72f77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feaa3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaa3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaa3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec72f77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (1133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %o
# | ...
# `---data was truncated (10240/76627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602a558656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005602a5583505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005602a5586cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73b9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73b938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73b9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73b931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602a551c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005602a551c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005602a5500f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005602a51b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005602a51afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f73b931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73b931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73b931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602a51afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (1134 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmad_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ae8efae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae8efab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae8efaecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0271849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02718a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0271849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0271831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae8ef4423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae8ef44086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae8ef28f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae8ebd8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae8ebd7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0271832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02718330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02718330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae8ebd7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (1135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a823ac856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a823ac5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a823ac8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc44cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc44cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc44cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc44cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a823a5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a823a5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a823a42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a8236f2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a8236f1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc44cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc44cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc44cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8236f1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (1136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559f2b9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559f2b94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559f2b97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69f6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69f658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69f6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69f651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559f2b2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559f2b2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559f2b11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559f27c1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559f27c0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f69f651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69f651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69f651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559f27c0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (1137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b23dc256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b23dbf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b23dc2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dec249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dec2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dec249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dec231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b23d5823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b23d58086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b23d3cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b239ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b239ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4dec232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dec2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dec2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b239ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (1138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5b419d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f5b419a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f5b419dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9a3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9a3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9a3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9a3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5b413323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5b4133086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5b4117f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5b3dc7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5b3dc6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd9a3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9a3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9a3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5b3dc6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (1139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 
# | ...
# `---data was truncated (10240/47772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d81cf7956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d81cf76505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d81cf79cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f574de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f574dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f574de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f574de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d81cf0f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d81cf0f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d81cef3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d81cba3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d81cba2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f574de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f574de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f574de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d81cba2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (1140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4d3fcf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d4d3fcc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d4d3fcfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae78b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae78b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae78b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae78b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4d3f6523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d4d3f65086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d4d3f49f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d4d3bf9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d4d3bf8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae78b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae78b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae78b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4d3bf8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (1141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | ...
# `---data was truncated (10240/66298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af8bd4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af8bd4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af8bd4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84fc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af8bce523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af8bce5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af8bcc9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af8b979166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af8b978e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84fc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af8b978d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (1142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653dc4cd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005653dc4ca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005653dc4cdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f957e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f957e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f957e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f957e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653dc46323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005653dc463086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005653dc447f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653dc0f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653dc0f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f957e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f957e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f957e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653dc0f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (1143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584d4d4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005584d4d40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005584d4d43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4217b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4217b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4217b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4217b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584d4cd923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005584d4cd9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005584d4cbdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005584d496d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005584d496ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4217b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4217b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4217b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584d496cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (1144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e817ae756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e817ae4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e817ae7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f483f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f483f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f483f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f483f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e817a7d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e817a7d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e817a61f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e817711166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e817710e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f483f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f483f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f483f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e817710d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (1145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652a775a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652a7757505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652a775acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67fbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67fbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67fbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67fbaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652a76f023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005652a76f0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005652a76d4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005652a7384166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005652a7383e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f67fbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67fbaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67fbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652a7383d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (1146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/27055) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eff14b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564eff148505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564eff14bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ae7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ae7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ae7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ae7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eff0e123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564eff0e1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564eff0c5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564efed75166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564efed74e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ae7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ae7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ae7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564efed74d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (1147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x hal
# | ...
# `---data was truncated (10240/514165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561849d5d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561849d5a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561849d5dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9bd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9bd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9bd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9bd6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561849cf323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561849cf3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561849cd7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561849987166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561849986e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd9bd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9bd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9bd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561849986d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (1148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %
# | ...
# `---data was truncated (10240/29809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2cbdcd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2cbdca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2cbdcdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6399f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6399f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6399f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6399f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2cbd6323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2cbd63086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2cbd47f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2cb9f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2cb9f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6399f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6399f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6399f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2cb9f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (1149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b92fd7056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b92fd6d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b92fd70cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44bbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44bbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44bbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44bbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b92fd0623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b92fd06086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b92fceaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b92f99a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b92f999e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f44bbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44bbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44bbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b92f999d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (1150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565168e6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565168e65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565168e68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4929049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49290a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4929049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4929031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565168dfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565168dfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565168de2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565168a92166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565168a91e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4929032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49290330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49290330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565168a91d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (1151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree n
# | ...
# `---data was truncated (10240/15237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d15fe3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d15fe2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d15fe31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8373f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8373f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8373f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8373f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d15fdc723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d15fdc7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d15fdabf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d15fa5b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d15fa5ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8373f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8373f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8373f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d15fa5ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (1152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055726c02656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055726c023505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055726c026cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4f8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4f818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4f8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4f811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055726bfbc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055726bfbc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055726bfa0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055726bc50166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055726bc4fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb4f811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4f811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4f811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055726bc4fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (1153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636304c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636304c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636304c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56b4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56b42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56b4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56b4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056363045923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563630459086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056363043df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005636300ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005636300ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f56b4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56b42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56b42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636300ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (1154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dac09856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563dac095505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563dac098cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94efa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94efaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94efa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94efa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dac02e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563dac02e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563dac012f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563dabcc2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563dabcc1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f94efa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94efa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94efa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dabcc1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (1155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fadf74f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fadf74c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fadf74fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d5a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d5a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d5a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d5a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fadf6e523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fadf6e5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fadf6c9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fadf379166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fadf378e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d5a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d5a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d5a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fadf378d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (1156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d9c24b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d9c248505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d9c24bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98e5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98e5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98e5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98e5c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d9c1e123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d9c1e1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d9c1c5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d9be75166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d9be74e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f98e5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98e5c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98e5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d9be74d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (1157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vs
# | ...
# `---data was truncated (10240/18591) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ed4f7656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ed4f73505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ed4f76cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68e7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68e758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68e7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68e751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ed4f0c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ed4f0c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ed4ef0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ed4ba0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ed4b9fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f68e751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68e751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68e751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ed4b9fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (1158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555682e9f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555682e9c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555682e9fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72ed449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72ed4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72ed449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72ed431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555682e3523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555682e35086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555682e19f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555682ac9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555682ac8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72ed432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72ed4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72ed4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555682ac8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (1159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   %1 = fpext bfloat %0 to float
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   %1 = fptrunc float %0 to bfloat
# |   ret bfloat %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e30f85856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e30f855505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e30f858cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f973d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f973d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f973d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f973d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e30f7ee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e30f7ee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e30f7d2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e30f482166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e30f481e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f973d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f973d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f973d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e30f481d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (1160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.
# | ...
# `---data was truncated (10240/28162) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ffed0c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555ffed09505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555ffed0ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bcbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bcbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bcbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bcbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ffeca223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555ffeca2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555ffec86f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555ffe936166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555ffe935e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2bcbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bcbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bcbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ffe935d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (1161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/97514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604bd57c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005604bd579505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005604bd57ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc48e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc48e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc48e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc48e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604bd51223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005604bd512086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604bd4f6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005604bd1a6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005604bd1a5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc48e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc48e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc48e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604bd1a5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (1162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dde25d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dde25d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dde25d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23aed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23aed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23aed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23aed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dde256d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dde256d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dde2551f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dde2201166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dde2200e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f23aed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23aed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23aed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dde2200d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (1163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055574790856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555747905505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555747908cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effed049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effed0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effed049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effed031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055574789e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055574789e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555747882f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555747532166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555747531e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007effed032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effed0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effed0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555747531d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (1164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4aca5956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d4aca56505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d4aca59cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc464f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc464f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc464f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc464f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4ac9ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d4ac9ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d4ac9d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d4ac683166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d4ac682e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc464f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc464f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc464f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4ac682d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (1165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d87a34756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d87a344505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d87a347cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7ffe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7ffea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7ffe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7ffe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d87a2dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d87a2dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d87a2c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d879f71166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d879f70e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa7ffe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7ffe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7ffe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d879f70d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (1166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559947f1c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559947f19505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559947f1ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6cf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6cf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6cf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6cf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559947eb223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559947eb2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559947e96f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559947b46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559947b45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa6cf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6cf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6cf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559947b45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (1167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055785d05b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055785d058505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055785d05bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16f1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16f1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16f1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16f1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055785cff123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055785cff1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055785cfd5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055785cc85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055785cc84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f16f1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16f1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16f1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055785cc84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (1168 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c0ca38956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0ca386505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0ca389cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f550c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f550c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f550c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f550c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0ca31f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c0ca31f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c0ca303f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c0c9fb3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c0c9fb2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f550c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f550c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f550c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0c9fb2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (1169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e72cc456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e72cc1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e72cc4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f181dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f181dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f181dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f181dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e72c5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e72c5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e72c3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e728ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e728ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f181dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f181dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f181dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e728edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (1170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a435b856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a435b5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a435b8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6381933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f638198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6381933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f638191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a4354e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a4354e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a43532f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a431e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a431e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f638191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f638191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f638191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a431e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (1171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557d5be656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005557d5be3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005557d5be6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3e2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3e2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3e2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3e2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557d5b7c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005557d5b7c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005557d5b60f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005557d5810166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005557d580fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb3e2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3e2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3e2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557d580fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (1172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b3da0b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b3da08505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b3da0bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd21c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd21c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd21c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd21c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b3d9a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b3d9a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b3d985f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b3d635166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b3d634e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd21c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd21c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd21c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b3d634d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (1173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606121d356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606121d0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606121d3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08cbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08cbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08cbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08cbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056061216923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560612169086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056061214df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560611dfd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560611dfce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f08cbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08cbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08cbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560611dfcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (1174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562f909756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562f9094505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562f9097cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f444d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f444d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f444d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f444d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562f902d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562f902d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562f9011f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562f8cc1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562f8cc0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f444d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f444d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f444d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562f8cc0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (1175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651b7e1c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005651b7e19505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005651b7e1ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b11049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b110a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b11049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b11031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651b7db223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651b7db2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651b7d96f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005651b7a46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005651b7a45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b11032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b110330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b110330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651b7a45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (1176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da2b25456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055da2b251505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055da2b254cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f67a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f67a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f67a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f67a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da2b1ea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055da2b1ea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055da2b1cef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055da2ae7e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055da2ae7de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f67a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f67a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f67a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da2ae7dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (1177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603941f856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603941f5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603941f8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f82b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f82b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f82b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f82b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056039418e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056039418e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560394172f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560393e22166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560393e21e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f82b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f82b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f82b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560393e21d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (1178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055562d87c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055562d879505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055562d87ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0099849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00998a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0099849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0099831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055562d81223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055562d812086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055562d7f6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055562d4a6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055562d4a5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0099832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00998330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00998330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055562d4a5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (1179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e721bd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564e721ba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564e721bdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe784133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe78418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe784133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe78411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e7215323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564e72153086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564e72137f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564e71de7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564e71de6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe78411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe78411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe78411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e71de6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (1180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b714fb456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b714fb1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b714fb4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84c871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b714f4a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b714f4a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b714f2ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b714bde166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b714bdde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84c871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b714bddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (1181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3a929556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e3a9292505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e3a9295cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f856d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f856d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f856d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f856d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3a922b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e3a922b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3a920ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e3a8ebf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e3a8ebee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f856d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f856d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f856d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3a8ebed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (1182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a81f4d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a81f4d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a81f4d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c9ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c9eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c9ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c9ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a81f46a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a81f46a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a81f44ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a81f0fe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a81f0fde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9c9ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c9ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c9ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a81f0fdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (1183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9e12a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9e12a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9e12a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f866ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f866ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f866ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f866ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9e123923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f9e1239086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f9e121df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f9e0ecd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f9e0ecce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f866ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f866ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f866ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9e0eccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (1184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055981a14756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055981a144505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055981a147cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55d0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55d058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55d0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55d051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055981a0dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055981a0dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055981a0c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559819d71166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559819d70e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f55d051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55d051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55d051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559819d70d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (1185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651feaa256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005651fea9f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005651feaa2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22c9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22c9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22c9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22c9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651fea3823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651fea38086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651fea1cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005651fe6cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005651fe6cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22c9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22c9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22c9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651fe6cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (1186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563593e2856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563593e25505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563593e28cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadd6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadd60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadd6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadd6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563593dbe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563593dbe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563593da2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563593a52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563593a51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fadd6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadd60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadd60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563593a51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (1187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056121d32856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056121d325505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056121d328cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71dd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71dd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71dd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71dd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056121d2be23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056121d2be086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056121d2a2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056121cf52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056121cf51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f71dd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71dd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71dd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056121cf51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (1188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635b83c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005635b83c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005635b83c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7fd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7fd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7fd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7fd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635b835b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005635b835b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005635b833ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005635b7fef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005635b7feee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe7fd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7fd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7fd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635b7feed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (1189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056304652856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563046525505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563046528cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fcf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fcf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fcf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fcf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630464be23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005630464be086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005630464a2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563046152166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563046151e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4fcf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fcf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fcf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563046151d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (1190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ea855556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ea8552505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ea8555cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4963133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f496318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4963133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f496311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ea84eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ea84eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ea84cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ea817f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ea817ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f496311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f496311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f496311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ea817ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: Modules/pr93497.cppm (1191 of 27911)
******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 3
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm      -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp      -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm      -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.Thing = type { i32 }
# | %struct.C = type { i32 }
# | %struct.NonConstexprDtor = type { i32 }
# | 
# | $needed = comdat any
# | 
# | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4
# | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4
# | @_ZW3mod11ConstantPtr = external global ptr, align 8
# | @_ZW3mod16NonConstantValue = external global %struct.C, align 4
# | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4
# | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }]
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z3usev() #0 {
# | entry:
# |   %t1 = alloca %struct.Thing, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | declare noundef i32 @_Z7consumei(i32 noundef) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use2v() #0 {
# | entry:
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %0 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0)
# |   ret i32 %call
# | }
# | 
# | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use3v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ptr = alloca ptr, align 8
# |   %agg.tmp = alloca %struct.C, align 4
# |   %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8
# |   store ptr %0, ptr %Ptr, align 8
# |   %1 = load ptr, ptr %Ptr, align 8
# |   %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0
# |   %2 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %2, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %3 = load ptr, ptr %Ptr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %4 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr i32 @needed() #0 comdat {
# | entry:
# |   %call = call noundef i32 @_Z7consumei(i32 noundef 43)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use4v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ref = alloca %struct.C, align 4
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false)
# |   %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0
# |   %0 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %1 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use5v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %V = alloca %struct.NonConstexprDtor, align 4
# |   %cleanup.dest.slot = alloca i32, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %1 = load i32, ptr %raw1, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %1)
# |   store i32 %call, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | if.end:                                           ; preds = %entry
# |   %call2 = call i32 @needed()
# |   store i32 %call2, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %if.end, %if.then
# |   call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3
# | 
# | declare void @_ZGIW3mod()
# | 
# | ; Function Attrs: noinline nounwind
# | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" {
# | entry:
# |   call void @_ZGIW3mod()
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #5 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# |  #0 0x000055daf9c2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055daf9c1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055daf9c20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f904b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f904b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f904b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f904b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daf9bb623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055daf9bb6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055daf9b9af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055daf984a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055daf9849e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f904b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f904b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f904b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daf9849d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (1192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056069344d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056069344a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056069344dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdebfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdebfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdebfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdebfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606933e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606933e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606933c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560693077166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560693076e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdebfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdebfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdebfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560693076d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (1193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x
# | ...
# `---data was truncated (10240/112817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592f058c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005592f0589505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005592f058ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce47533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce4758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce47533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce4751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592f052223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005592f0522086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005592f0506f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005592f01b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005592f01b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce4751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce4751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce4751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592f01b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (1194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b292f8456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b292f81505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b292f84cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a73933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a7398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a73933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a7391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b292f1a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b292f1a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b292efef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b292bae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b292bade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a7391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a7391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a7391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b292badd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (1195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/246614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626df46f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005626df46c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005626df46fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe591f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe591f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe591f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe591f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626df40523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005626df405086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005626df3e9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005626df099166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005626df098e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe591f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe591f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe591f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626df098d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (1196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/12644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617cf70556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005617cf702505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005617cf705cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fbbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fbbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fbbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fbbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617cf69b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005617cf69b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005617cf67ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005617cf32f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005617cf32ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9fbbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fbbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fbbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617cf32ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (1197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac765aa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac765a7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac765aacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c9d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c9d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c9d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c9d2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac7654023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac76540086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac76524f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac761d4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac761d3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7c9d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c9d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c9d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac761d3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (1198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b448f4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b448f40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b448f43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43b1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43b12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43b1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43b1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b448ed923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b448ed9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b448ebdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b448b6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b448b6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f43b1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43b12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43b12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b448b6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (1199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055618764456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556187641505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556187644cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa020933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa02098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa020933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa02091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561875da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561875da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561875bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055618726e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055618726de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa02091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa02091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa02091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055618726dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (1200 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d152ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d152ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d152aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb91333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb9138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb91333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb9131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d1524423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d15244086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d15228f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d14ed8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d14ed7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb9131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb9131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb9131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d14ed7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (1201 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/69495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562882bce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562882bcb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562882bcecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa25c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa25ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa25c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa25c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562882b6423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562882b64086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562882b48f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005628827f8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005628827f7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa25c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa25c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa25c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628827f7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (1202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617803c856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005617803c5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005617803c8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb57105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb5715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb57105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb570ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056178035e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056178035e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561780342f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056177fff2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056177fff1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb570eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb570ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb570ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056177fff1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (1203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x
# | ...
# `---data was truncated (10240/84802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056373b0e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056373b0e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056373b0e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f21133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f2118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f21133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f2111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056373b07b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056373b07b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056373b05ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056373ad0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056373ad0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f2111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f2111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f2111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056373ad0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (1204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entr
# | ...
# `---data was truncated (10240/18361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632d8d4756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005632d8d44505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005632d8d47cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9871d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9871d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9871d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9871d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632d8cdd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005632d8cdd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005632d8cc1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005632d8971166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005632d8970e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9871d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9871d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9871d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632d8970d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (1205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c1e22b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556c1e228505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556c1e22bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fbdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fbdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fbdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fbdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c1e1c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556c1e1c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556c1e1a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556c1de55166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556c1de54e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2fbdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fbdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fbdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c1de54d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (1206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad281d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad281d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad281d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47bfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47bfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47bfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47bfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad2816a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad2816a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad2814ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad27dfe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad27dfde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47bfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47bfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47bfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad27dfdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (1207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/58334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566f410856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005566f4105505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005566f4108cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ce3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ce34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ce3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ce3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566f409e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005566f409e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005566f4082f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005566f3d32166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005566f3d31e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3ce3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ce34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ce34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566f3d31d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (1208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abc06fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055abc06f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055abc06fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbed2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbed238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbed2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbed231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abc069223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055abc0692086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055abc0676f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055abc0326166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055abc0325e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbed231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbed231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbed231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abc0325d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (1209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bbff4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556bbff43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556bbff46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6c7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6c798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6c7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6c791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bbfedc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556bbfedc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556bbfec0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556bbfb70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556bbfb6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe6c791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6c791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6c791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bbfb6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (1210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f2e9f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f2e9ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f2e9f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f2e98723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f2e987086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f2e96bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f2e61b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f2e61ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbeb1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f2e61ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (1211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b59597c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b595979505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b59597ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5acc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5acca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5acc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5acc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b59591223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b595912086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5958f6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5955a6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5955a5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff5acc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5acc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5acc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5955a5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (1212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e74b71756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e74b714505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e74b717cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc68a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc68a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc68a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc68a2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e74b6ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e74b6ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e74b691f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e74b341166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e74b340e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc68a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc68a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc68a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e74b340d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (1213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558345e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558345e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558345e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a1ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a1caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a1ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a1ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055583457d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055583457d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555834561f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555834211166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555834210e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a1ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a1ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a1ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555834210d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (1214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfm
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d577b3456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d577b31505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d577b34cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed8d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed8d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed8d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed8d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d577aca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d577aca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d577aaef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d57775e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d57775de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fed8d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed8d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed8d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d57775dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (1215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa8f8d056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa8f8cd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa8f8d0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d4b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d4b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d4b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d4b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa8f86623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa8f866086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa8f84af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa8f4fa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa8f4f9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d4b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d4b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d4b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa8f4f9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (1216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3d537456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b3d5371505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b3d5374cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f593b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f593b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f593b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f593b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3d530a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b3d530a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b3d52eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b3d4f9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b3d4f9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f593b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f593b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f593b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3d4f9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (1217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056100c11556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056100c112505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056100c115cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f590b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f590b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f590b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f590b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056100c0ab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056100c0ab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056100c08ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056100bd3f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056100bd3ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f590b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f590b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f590b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056100bd3ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (1218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056394eb8c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056394eb89505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056394eb8ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4fda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4fdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4fda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4fda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056394eb2223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056394eb22086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056394eb06f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056394e7b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056394e7b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa4fda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4fda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4fda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056394e7b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (1219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055736ebae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055736ebab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055736ebaecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0218b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0218b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0218b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0218b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055736eb4423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055736eb44086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055736eb28f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055736e7d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055736e7d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0218b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0218b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0218b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055736e7d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (1220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmclr_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmclr_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmclr_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmclr_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmclr_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmclr_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmclr_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e014e8d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e014e8a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e014e8dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f3081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f308725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f3081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f30803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e014e2323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e014e23086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e014e07f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e014ab7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e014ab6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5f30804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f308050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f308050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e014ab6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (1221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> 
# | ...
# `---data was truncated (10240/12298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fb821756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561fb8214505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561fb8217cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d23b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d23b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d23b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d23b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fb81ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561fb81ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561fb8191f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561fb7e41166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561fb7e40e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d23b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d23b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d23b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fb7e40d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (1222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c  -check-prefix=RV32ZBC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055713583756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557135834505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557135837cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87e8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87e895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87e8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87e88ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571357cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571357cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571357b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557135461166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557135460e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87e88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87e88ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87e88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557135460d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (1223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598f7a1756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005598f7a14505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005598f7a17cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c1df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c1df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c1df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c1df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598f79ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005598f79ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005598f7991f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005598f7641166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005598f7640e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c1df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c1df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c1df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598f7640d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (1224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6d0b3c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a6d0b39505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a6d0b3ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82f1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82f1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82f1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82f1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6d0ad223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a6d0ad2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a6d0ab6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a6d0766166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a6d0765e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82f1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82f1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82f1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6d0765d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (1225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0da34256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e0da33f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e0da342cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78c9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78c9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78c9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78c9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0da2d823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e0da2d8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e0da2bcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e0d9f6c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e0d9f6be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78c9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78c9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78c9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0d9f6bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (1226 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlasta_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlasta_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlasta_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ffa61f256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ffa61ef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ffa61f2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ee1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ee158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ee1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ee151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffa618823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ffa6188086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ffa616cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ffa5e1c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ffa5e1be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ee151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ee151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ee151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffa5e1bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (1227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/51193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056033467456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560334671505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560334674cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb190d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb190d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb190d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb190d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056033460a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056033460a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005603345eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056033429e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056033429de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb190d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb190d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb190d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056033429dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (1228 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557b6bcab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b6bca8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b6bcabcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2625649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26256a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2625649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2625631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b6bc4123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b6bc41086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b6bc25f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b6b8d5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b6b8d4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2625632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26256330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26256330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b6b8d4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (1229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c29da6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c29da6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c29da6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fbdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fbdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fbdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fbdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c29da0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c29da03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c29d9e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c29d697166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c29d696e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6fbdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fbdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fbdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c29d696d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (1230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfs
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581e265e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005581e265b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005581e265ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c07f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c07f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c07f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c07f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581e25f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581e25f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581e25d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581e2288166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581e2287e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7c07f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c07f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c07f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581e2287d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (1231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb0698656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb06983505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb06986cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44a9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44a958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44a9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44a951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb0691c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb0691c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb06900f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb065b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb065afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f44a951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44a951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44a951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb065afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (1232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/176535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559097d8e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559097d8b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559097d8ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f226b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f226b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f226b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f226b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559097d2423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559097d24086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559097d08f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005590979b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005590979b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f226b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f226b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f226b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590979b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (1233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea425c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea425bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea425c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f165601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16560725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f165601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1656003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea4255823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea42558086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea4253cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea421ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea421ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1656004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16560050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16560050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea421ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (1234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056067e26756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056067e264505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056067e267cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5b891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056067e1fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056067e1fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056067e1e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056067de91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056067de90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc5b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5b891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056067de90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (1235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ff862856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ff8625505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ff8628cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea73933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea7398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea73933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea7391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ff85be23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ff85be086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ff85a2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ff8252166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ff8251e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fea7391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea7391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea7391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ff8251d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (1236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c  -check-prefix=RV32ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574a4e9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005574a4e8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005574a4e90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e11849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e118a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e11849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e11831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574a4e2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005574a4e26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005574a4e0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005574a4aba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005574a4ab9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e11832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e118330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e118330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574a4ab9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (1237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055daf290356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055daf2900505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055daf2903cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5501d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5501d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5501d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5501d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daf289923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055daf2899086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055daf287df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055daf252d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055daf252ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5501d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5501d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5501d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daf252cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (1238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsmul_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9e7f2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b9e7f27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b9e7f2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93a8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93a8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93a8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93a8e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9e7ec023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b9e7ec0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b9e7ea4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9e7b54166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9e7b53e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f93a8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93a8e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93a8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9e7b53d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (1239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eded59356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eded590505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eded593cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5773b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5773b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5773b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5773b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eded52923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eded529086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eded50df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eded1bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eded1bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5773b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5773b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5773b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eded1bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (1240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscal
# | ...
# `---data was truncated (10240/12471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cdfffa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cdfff7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cdfffacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe299a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe299aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe299a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe299a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cdff9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cdff90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cdff74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cdfc24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cdfc23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe299a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe299a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe299a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cdfc23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (1241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b16017c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b160179505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b16017ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f7dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f7dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f7dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f7dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b16011223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b160112086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b1600f6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b15fda6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b15fda5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f7dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f7dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f7dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b15fda5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (1242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2a64b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a2a64b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a2a64b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6ee905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6ee95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6ee905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6ee8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2a644a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a2a644a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a2a642ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a2a60de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a2a60dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc6ee8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6ee8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6ee8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2a60ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (1243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cec005056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cec004d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cec0050cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4238933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f423898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4238933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f423891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cebffe623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cebffe6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cebffcaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cebfc7a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cebfc79e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f423891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f423891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f423891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cebfc79d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (1244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddd600e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ddd600b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ddd600ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6290b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6290b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6290b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6290b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddd5fa423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ddd5fa4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ddd5f88f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ddd5c38166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ddd5c37e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6290b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6290b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6290b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddd5c37d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (1245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afb87ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055afb87cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055afb87cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ad1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ad198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ad1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ad191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afb876423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055afb8764086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055afb8748f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055afb83f8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055afb83f7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0ad191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ad191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ad191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afb83f7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (1246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c3a9ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557c3a9aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557c3a9adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff09c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff09c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff09c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff09c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c3a94323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557c3a943086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557c3a927f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557c3a5d7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557c3a5d6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff09c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff09c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff09c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c3a5d6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (1247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/72143) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615ea52456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615ea521505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615ea524cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa28a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa28a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa28a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa28a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615ea4ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615ea4ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615ea49ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615ea14e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615ea14de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa28a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa28a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa28a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615ea14dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (1248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f
# | ...
# `---data was truncated (10240/165246) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7ccef256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7cceef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7ccef2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb4b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb4b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb4b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb4b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7cce8823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7cce88086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7cce6cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7ccb1c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7ccb1be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb4b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb4b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb4b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7ccb1bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve/andv.c (1249 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055e79752f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e79752c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e79752fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8eeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7974c523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7974c5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7974a9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e797159166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e797158e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e797158d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (1250 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/22149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562dac98456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562dac981505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562dac984cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7b4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7b4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7b4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7b4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dac91a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562dac91a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562dac8fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562dac5ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562dac5ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7b4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7b4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7b4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dac5add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (1251 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3f6ab156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b3f6aae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b3f6ab1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1f9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1f9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1f9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1f9eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3f6a4723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b3f6a47086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b3f6a2bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b3f66db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b3f66dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe1f9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1f9eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1f9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3f66dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (1252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565135af756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565135af4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565135af7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70c871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565135a8d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565135a8d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565135a71f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565135721166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565135720e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f70c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70c871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565135720d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (1253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b1bb4c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b1bb49505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b1bb4ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f484c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f484c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f484c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f484c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b1bae223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b1bae2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b1bac6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b1b776166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b1b775e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f484c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f484c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f484c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b1b775d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (1254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055728683c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557286839505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055728683ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec5af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec5af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec5af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec5af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572867d223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005572867d2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005572867b6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557286466166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557286465e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec5af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec5af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec5af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557286465d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (1255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vsc
# | ...
# `---data was truncated (10240/65701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d5cf2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d5cf29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d5cf2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4c0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4c018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4c0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4c011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d5cec223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d5cec2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d5cea6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d5cb56166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d5cb55e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc4c011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4c011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4c011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d5cb55d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (1256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632eccb656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005632eccb3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005632eccb6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0501733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f050178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0501733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f050171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632ecc4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005632ecc4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005632ecc30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005632ec8e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005632ec8dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f050171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f050171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f050171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632ec8dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (1257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582d0c1656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005582d0c13505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005582d0c16cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11f0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11f098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11f0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11f091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582d0bac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582d0bac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582d0b90f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582d0840166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582d083fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f11f091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11f091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11f091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582d083fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (1258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/72501) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfa521456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dfa5211505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dfa5214cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f257e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f257e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f257e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f257e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfa51aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dfa51aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dfa518ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dfa4e3e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dfa4e3de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f257e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f257e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f257e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa4e3dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (1259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc130fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dc130f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dc130facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8f3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8f3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8f3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8f3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc1309023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dc13090086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dc13074f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dc12d24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dc12d23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8f3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8f3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8f3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc12d23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (1260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563494d2956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563494d26505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563494d29cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f218f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f218f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f218f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f218f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563494cbf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563494cbf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563494ca3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563494953166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563494952e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f218f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f218f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f218f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563494952d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (1261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634c56fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005634c56fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005634c56fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9951649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99516a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9951649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9951631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634c569323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634c5693086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005634c5677f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005634c5327166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005634c5326e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9951632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99516330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99516330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634c5326d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (1262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b26aa356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b26aa0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b26aa3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f498cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f498cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f498cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f498cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b26a3923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b26a39086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b26a1df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b266cd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b266cce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f498cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f498cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f498cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b266ccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (1263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056053521156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056053520e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560535211cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdff51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605351a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005605351a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056053518bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560534e3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560534e3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcdff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdff51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560534e3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (1264 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005633eb74856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633eb745505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633eb748cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcab1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcab158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcab1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcab151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633eb6de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005633eb6de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005633eb6c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005633eb372166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005633eb371e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcab151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcab151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcab151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633eb371d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (1265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d2cdd956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d2cdd6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d2cdd9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdb3a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdb3a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdb3a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdb3a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d2cd6f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d2cd6f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d2cd53f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d2ca03166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d2ca02e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efdb3a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdb3a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdb3a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d2ca02d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (1266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cd6eaa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564cd6ea7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564cd6eaacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4451649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44516a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4451649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4451631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cd6e4023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564cd6e40086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564cd6e24f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564cd6ad4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564cd6ad3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4451632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44516330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44516330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cd6ad3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (1267 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a02552356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a025520505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a025523cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca5f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca5f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca5f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca5f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0254b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a0254b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a02549df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a02514d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a02514ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca5f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca5f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca5f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a02514cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (1268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5cfcb156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f5cfcae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f5cfcb1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f885af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f885af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f885af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f885af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5cfc4723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5cfc47086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5cfc2bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5cf8db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5cf8dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f885af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f885af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f885af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5cf8dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (1269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d25269056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d25268d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d252690cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7f5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7f515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7f5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7f50ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d25262623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d252626086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d25260af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2522ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2522b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb7f50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7f50ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7f50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2522b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (1270 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac76bb756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac76bb4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac76bb7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3958b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3958b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3958b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3958b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac76b4d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac76b4d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac76b31f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac767e1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac767e0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3958b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3958b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3958b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac767e0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (1271 of 27911)
******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | @con_unify_unimap_p1 = global ptr null, align 8
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @con_unify_unimap_q1() #0 {
# | entry:
# |   %p.addr.i = alloca ptr, align 8
# |   %q.addr.i = alloca ptr, align 8
# |   %size.addr.i = alloca i64, align 8
# |   %0 = load ptr, ptr @con_unify_unimap_p1, align 8
# |   store ptr %0, ptr %p.addr.i, align 8
# |   store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8
# |   store i64 4, ptr %size.addr.i, align 8
# |   %1 = load ptr, ptr %p.addr.i, align 8
# |   %2 = load ptr, ptr %q.addr.i, align 8
# |   %3 = load i64, ptr %size.addr.i, align 8
# |   %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2
# |   ret i32 %call.i
# | }
# | 
# | ; Function Attrs: alwaysinline nobuiltin nounwind
# | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #2 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# |  #0 0x000055ca5ed7056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ca5ed6d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ca5ed70cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9976f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9976f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9976f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9976f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca5ed0623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ca5ed06086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ca5eceaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ca5e99a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ca5e999e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9976f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9976f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9976f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca5e999d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (1272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ddfc5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555ddfc53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555ddfc56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6369849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63698a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6369849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6369831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ddfbec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555ddfbec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555ddfbd0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555ddf880166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555ddf87fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6369832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63698330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63698330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ddf87fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (1273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/31876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e35c67f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e35c67c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e35c67fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2f8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2f80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2f8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2f8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e35c61523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e35c615086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e35c5f9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e35c2a9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e35c2a8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe2f8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2f80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2f80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e35c2a8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (1274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f7a50a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f7a507505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f7a50acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d23f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d23f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d23f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d23eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f7a4a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f7a4a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f7a484f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f7a134166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f7a133e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d23eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d23eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d23eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f7a133d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (1275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/54480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfe9d0f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bfe9d0c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bfe9d0fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efde1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efde198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efde1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efde191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfe9ca523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bfe9ca5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bfe9c89f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bfe9939166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bfe9938e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efde191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efde191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efde191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfe9938d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (1276 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610b29d956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005610b29d6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005610b29d9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e1e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e1e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e1e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e1e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610b296f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005610b296f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005610b2953f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005610b2603166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005610b2602e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3e1e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e1e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e1e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610b2602d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (1277 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 3
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 2
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_374 = alloca <4 x bfloat>, align 8
# |   %__s0_374 = alloca <4 x bfloat>, align 8
# |   %__s2_374 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.add
# | ...
# `---data was truncated (10240/18871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619a391c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005619a3919505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005619a391ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff841533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff84158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff841533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff84151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619a38b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005619a38b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005619a3896f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005619a3546166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005619a3545e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff84151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff84151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff84151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619a3545d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (1278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7b6f3e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a7b6f3b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a7b6f3ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd02bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd02bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd02bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd02bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7b6ed423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a7b6ed4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a7b6eb8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a7b6b68166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a7b6b67e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd02bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd02bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd02bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7b6b67d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (1279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dd0da656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557dd0da3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557dd0da6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd287133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd28718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd287133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd28711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dd0d3c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557dd0d3c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557dd0d20f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557dd09d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557dd09cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd28711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd28711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd28711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dd09cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (1280 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d2898156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d2897e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d28981cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca26849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca268a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca26849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca26831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d2891723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d28917086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d288fbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d285ab166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d285aae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca26832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca268330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca268330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d285aad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (1281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587566c156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587566be505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587566c1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0e3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0e3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0e3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0e3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055875665723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558756657086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055875663bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005587562eb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005587562eae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff0e3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0e3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0e3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587562ead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (1282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad328f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad328f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad328f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f731041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73104725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f731041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7310403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad3288c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad3288c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad32870f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad32520166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad3251fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7310404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73104050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73104050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad3251fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (1283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603bf83b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603bf838505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603bf83bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4b3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4b3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4b3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4b3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603bf7d123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005603bf7d1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005603bf7b5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005603bf465166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005603bf464e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4b3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4b3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4b3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603bf464d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (1284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bd831d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559bd831a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559bd831dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e75649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e75649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e75631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bd82b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559bd82b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559bd8297f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559bd7f47166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559bd7f46e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e75632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e756330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bd7f46d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (1285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c12540e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c12540b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c12540ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c14d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c14d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c14d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c14d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1253a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1253a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c125388f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c125038166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c125037e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6c14d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c14d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c14d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c125037d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (1286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056156d12f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056156d12c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056156d12fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9485049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94850a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9485049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9485031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056156d0c523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056156d0c5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056156d0a9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056156cd59166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056156cd58e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9485032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94850330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94850330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056156cd58d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (1287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1a325156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1a324e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1a3251cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b31d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b31d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b31d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b31d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1a31e723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1a31e7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1a31cbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1a2e7b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1a2e7ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b31d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b31d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b31d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1a2e7ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (1288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1df79956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a1df796505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a1df799cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0b2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0b2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0b2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0b2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1df72f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a1df72f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a1df713f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a1df3c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a1df3c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb0b2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0b2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0b2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1df3c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (1289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb6c90156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb6c8fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb6c901cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febac533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febac58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febac533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febac51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb6c89723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb6c897086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb6c87bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb6c52b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb6c52ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007febac51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febac51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febac51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb6c52ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (1290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae6206856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae62065505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae62068cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f1ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f1eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f1ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f1ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae61ffe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae61ffe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae61fe2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae61c92166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae61c91e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2f1ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f1ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f1ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae61c91d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (1291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/26512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d051cd356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d051cd0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d051cd3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28de533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28de58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28de533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28de51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d051c6923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d051c69086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d051c4df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d0518fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d0518fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f28de51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28de51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28de51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0518fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (1292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628e6b0f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005628e6b0c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005628e6b0fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f977a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f977a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f977a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f977a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628e6aa523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005628e6aa5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005628e6a89f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005628e6739166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005628e6738e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f977a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f977a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f977a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628e6738d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (1293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a332a556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563a332a2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563a332a5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f982f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f982f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f982f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f982f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a3323b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563a3323b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563a3321ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563a32ecf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563a32ecee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f982f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f982f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f982f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a32eced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (1294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7e572456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a7e5721505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a7e5724cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f412c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f412c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f412c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f412c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7e56ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a7e56ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a7e569ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a7e534e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a7e534de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f412c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f412c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f412c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7e534dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (1295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b9899356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b98990505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b98993cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd47449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd474a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd47449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd47431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b9892923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b98929086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b9890df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b985bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b985bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd47432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd474330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd474330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b985bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (1296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef
# | ...
# `---data was truncated (10240/78336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d05af4e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d05af4b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d05af4ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb152933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb15298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb152933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb15291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d05aee423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d05aee4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d05aec8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d05ab78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d05ab77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb15291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb15291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb15291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d05ab77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (1297 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561832fcb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561832fc8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561832fcbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b70f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b70f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b70f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b70f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561832f6123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561832f61086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561832f45f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561832bf5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561832bf4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b70f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b70f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b70f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561832bf4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (1298 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0cd05c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a0cd059505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a0cd05ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd17da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd17daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd17da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd17da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0ccff223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a0ccff2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a0ccfd6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a0ccc86166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a0ccc85e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd17da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd17da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd17da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0ccc85d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (1299 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f787b1456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f787b11505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f787b14cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa01ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa01ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa01ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa01ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f787aaa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f787aaa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f787a8ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f78773e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f78773de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa01ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa01ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa01ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f78773dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (1300 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x
# | ...
# `---data was truncated (10240/78032) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056041fa0a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056041fa07505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056041fa0acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6886133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f688618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6886133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f688611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056041f9a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056041f9a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056041f984f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056041f634166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056041f633e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f688611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f688611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f688611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056041f633d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (1301 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055578352456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555783521505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555783524cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd31db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd31db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd31db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd31db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557834ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005557834ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055578349ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055578314e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055578314de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd31db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd31db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd31db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055578314dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (1302 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f902aa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f902a7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f902aacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd9d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd9d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd9d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd9d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f9024023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f90240086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f90224f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f8fed4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f8fed3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd9d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd9d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd9d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f8fed3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (1303 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x 
# | ...
# `---data was truncated (10240/59787) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db9c1dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055db9c1d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055db9c1dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1f2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1f22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1f2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1f2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db9c17223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055db9c172086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055db9c156f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055db9be06166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055db9be05e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe1f2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1f22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1f22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db9be05d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (1304 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a784adc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a784ad9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a784adccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb723a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb723aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb723a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb723a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a784a7223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a784a72086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a784a56f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a784706166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a784705e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb723a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb723a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb723a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a784705d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (1305 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# |  #0 0x000055720e07b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055720e078505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055720e07bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70a7505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70a755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70a7505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70a74ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055720e01123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055720e011086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055720dff5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055720dca5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055720dca4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f70a74eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70a74ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70a74ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055720dca4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (1306 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <4 x float> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = fcmp oeq <4 x float> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = icmp eq <4 x i32> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = 
# | ...
# `---data was truncated (10240/125481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fbd9e956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562fbd9e6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562fbd9e9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d49f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d49f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d49f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d49f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fbd97f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562fbd97f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562fbd963f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562fbd613166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562fbd612e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d49f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d49f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d49f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fbd612d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (1307 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635db36356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005635db360505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005635db363cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9a2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9a2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9a2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9a2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635db2f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005635db2f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005635db2ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005635daf8d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005635daf8ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc9a2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9a2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9a2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635daf8cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (1308 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc  -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <8 x i8>, ptr %__promote, align 8
# |   store <8 x i8> %1, ptr %__ret, align 8
# |   %2 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %2, ptr %tmp, align 8
# |   %3 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %.compoundliteral.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8>
# |   store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8
# |   store <8 x i8> %9, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %.compoundliteral.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> <i32 0, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> <i32 0, i32 1, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> <i32 0, i32 1, i32 2, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %9 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison
# | ...
# `---data was truncated (10240/101594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000563bee28856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563bee285505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563bee288cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf48f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf48f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf48f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf48eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bee21e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563bee21e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563bee202f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563bedeb2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563bedeb1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbf48eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf48eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf48eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bedeb1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (1309 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651c601456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005651c6011505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005651c6014cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4313705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f431375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4313705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43136ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651c5faa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651c5faa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651c5f8ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005651c5c3e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005651c5c3de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f43136eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43136ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43136ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651c5c3dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (1310 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b89ea2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b89ea1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b89ea20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f5621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f562725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f5621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f56203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b89e9b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b89e9b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b89e99af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b89e64a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b89e649e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f56204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f562050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f562050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b89e649d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-crc32.c (1311 of 27911)
******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652c122056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652c121d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652c1220cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52bdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52bdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52bdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52bdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652c11b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005652c11b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005652c119af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005652c0e4a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005652c0e49e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f52bdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52bdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52bdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652c0e49d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (1312 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056220dde256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056220dddf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056220dde2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82d6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82d6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82d6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82d6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056220dd7823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056220dd78086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056220dd5cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056220da0c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056220da0be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82d6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82d6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82d6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056220da0bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (1313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# | ...
# `---data was truncated (10240/170489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056203830356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562038300505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562038303cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04b2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04b2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04b2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04b2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056203829923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562038299086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056203827df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562037f2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562037f2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f04b2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04b2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04b2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562037f2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (1314 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf0b75056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf0b74d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf0b750cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57bc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57bc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57bc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57bc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf0b6e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf0b6e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf0b6caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf0b37a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf0b379e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f57bc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57bc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57bc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf0b379d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (1315 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652da75656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652da753505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652da756cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda93a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda93aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda93a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda93a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652da6ec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005652da6ec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005652da6d0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005652da380166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005652da37fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda93a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda93a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda93a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652da37fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (1316 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acfcf1c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055acfcf19505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055acfcf1ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd20f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd20f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd20f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd20f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acfceb223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055acfceb2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055acfce96f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055acfcb46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055acfcb45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd20f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd20f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd20f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acfcb45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (1317 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscal
# | ...
# `---data was truncated (10240/26704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649c280a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649c2807505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649c280acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f451cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f451cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f451cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f451cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649c27a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005649c27a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005649c2784f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005649c2434166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005649c2433e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f451cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f451cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f451cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649c2433d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (1318 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557652e7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557652e72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557652e75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4df705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4df75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4df705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4df6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557652e0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557652e0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557652deff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557652a9f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557652a9ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4df6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4df6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4df6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557652a9ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (1319 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055848288e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055848288b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055848288ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b1ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b1cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b1ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b1ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055848282423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558482824086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558482808f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005584824b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005584824b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b1ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b1ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b1ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584824b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (1320 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16
# | ...
# `---data was truncated (10240/62095) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618467e956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005618467e6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005618467e9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35b0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35b0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35b0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35b0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056184677f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056184677f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561846763f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561846413166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561846412e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f35b0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35b0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35b0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561846412d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (1321 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc5a42f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dc5a42c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dc5a42fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a05849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a058a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a05849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a05831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc5a3c523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dc5a3c5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dc5a3a9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dc5a059166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dc5a058e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a05832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a058330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a058330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc5a058d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (1322 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 
# | ...
# `---data was truncated (10240/26572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6dd05456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c6dd051505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c6dd054cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1efef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1efef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1efef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1efeeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6dcfea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c6dcfea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c6dcfcef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c6dcc7e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c6dcc7de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1efeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1efeeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1efeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6dcc7dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (1323 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/25279) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5a6d6356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a5a6d60505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a5a6d63cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4703f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4703f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4703f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4703f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5a6cf923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a5a6cf9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a5a6cddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a5a698d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a5a698ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4703f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4703f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4703f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5a698cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (1324 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056373270756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563732704505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563732707cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54bbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54bbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54bbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54bbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056373269d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056373269d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563732681f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563732331166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563732330e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f54bbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54bbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54bbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563732330d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (1325 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055908557756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559085574505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559085577cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4309449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4309449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4309431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055908550d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055908550d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005590854f1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005590851a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005590851a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4309432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43094330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590851a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (1326 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055566f79056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055566f78d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055566f790cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facbc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facbc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facbc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facbc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055566f72623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055566f726086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055566f70af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055566f3ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055566f3b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007facbc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facbc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facbc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055566f3b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (1327 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/12389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd3f60a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dd3f607505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dd3f60acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ebd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ebd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ebd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ebd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd3f5a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dd3f5a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dd3f584f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dd3f234166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dd3f233e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ebd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ebd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ebd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd3f233d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (1328 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   
# | ...
# `---data was truncated (10240/19123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b2d9c056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559b2d9bd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559b2d9c0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e1b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e1b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e1b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e1b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b2d95623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559b2d956086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559b2d93af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559b2d5ea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559b2d5e9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e1b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e1b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e1b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b2d5e9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (1329 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, 
# | ...
# `---data was truncated (10240/24959) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576bee1256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576bee0f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576bee12cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16cf305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16cf35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16cf305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16cf2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576beda823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576beda8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576bed8cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576bea3c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576bea3be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f16cf2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16cf2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16cf2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576bea3bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (1330 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b23a02856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b23a025505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b23a028cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c7ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c7aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c7ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c7ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b239fbe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b239fbe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b239fa2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b239c52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b239c51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9c7ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c7ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c7ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b239c51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (1331 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056327d4f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056327d4ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056327d4f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f130a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f130a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f130a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f130a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056327d48723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056327d487086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056327d46bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056327d11b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056327d11ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f130a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f130a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f130a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056327d11ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (1332 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d6fd1d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d6fd1a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d6fd1dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dd1305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dd135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dd1305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dd12ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d6fcb323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d6fcb3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d6fc97f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d6f947166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d6f946e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0dd12eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dd12ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dd12ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d6f946d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (1333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcf472356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bcf4720505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bcf4723cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5f1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5f1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5f1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5f1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcf46b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bcf46b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bcf469df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bcf434d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bcf434ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5f1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5f1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5f1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcf434cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (1334 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8f41a856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a8f41a5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a8f41a8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb65b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb65b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb65b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb65b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f413e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a8f413e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a8f4122f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a8f3dd2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a8f3dd1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb65b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb65b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb65b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f3dd1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (1335 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x
# | ...
# `---data was truncated (10240/101475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637c2e6456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637c2e61505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637c2e64cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f226db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f226db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f226db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f226db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637c2dfa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005637c2dfa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005637c2ddef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005637c2a8e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005637c2a8de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f226db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f226db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f226db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637c2a8dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (1336 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <v
# | ...
# `---data was truncated (10240/65080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4215a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b4215a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b4215a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd88649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd886a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd88649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd88631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b42153f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b42153f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b421523f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b4211d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b4211d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd88632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd886330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd886330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4211d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (1337 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16
# | ...
# `---data was truncated (10240/84971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e033d5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e033d53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e033d56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5912d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5912d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5912d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5912d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e033cec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e033cec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e033cd0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e033980166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e03397fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5912d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5912d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5912d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e03397fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (1338 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# | 
# | ...
# `---data was truncated (10240/26460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601907b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005601907b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601907b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5516f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5516f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5516f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5516f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056019074c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056019074c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560190730f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601903e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601903dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5516f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5516f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5516f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601903dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (1339 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639d4c8b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639d4c88505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639d4c8bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6dd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6dd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6dd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6dd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639d4c2123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639d4c21086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639d4c05f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639d48b5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639d48b4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa6dd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6dd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6dd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639d48b4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (1340 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e20da2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e20da29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e20da2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc059905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc05995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc059905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0598ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e20d9c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e20d9c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e20d9a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e20d656166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e20d655e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0598eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0598ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0598ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e20d655d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (1341 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x
# | ...
# `---data was truncated (10240/93466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c529e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561c529e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561c529e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f577cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f577cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f577cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f577cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c5297923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561c52979086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561c5295df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561c5260d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561c5260ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f577cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f577cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f577cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c5260cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (1342 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.
# | ...
# `---data was truncated (10240/16654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562ee9b556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562ee9b2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562ee9b5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2511133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f251118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2511133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f251111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562ee94b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562ee94b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562ee92ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562ee5df166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562ee5dee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f251111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f251111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f251111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562ee5ded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (1343 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9b731a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d9b7317505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d9b731acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f537e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f537e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f537e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f537e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9b72b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9b72b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9b7294f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9b6f44166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9b6f43e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f537e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f537e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f537e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9b6f43d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (1344 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x ha
# | ...
# `---data was truncated (10240/18235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c493bec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c493be9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c493beccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60c7505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60c755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60c7505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60c74ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c493b8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c493b82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c493b66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c493816166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c493815e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f60c74eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60c74ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60c74ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c493815d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (1345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16
# | ...
# `---data was truncated (10240/12536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b594be056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b594bdd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b594be0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa12b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa12b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa12b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa12b8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b594b7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b594b76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b594b5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b59480a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b594809e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa12b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa12b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa12b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b594809d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (1346 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde
# | ...
# `---data was truncated (10240/31748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641dedbb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005641dedb8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005641dedbbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c1f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c1f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c1f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c1f8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641ded5123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005641ded51086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005641ded35f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005641de9e5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005641de9e4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8c1f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c1f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c1f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641de9e4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (1347 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055617ca5156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055617ca4e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055617ca51cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cf0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cf0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cf0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cf0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055617c9e723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055617c9e7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055617c9cbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055617c67b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055617c67ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6cf0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cf0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cf0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055617c67ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (1348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl
# | ...
# `---data was truncated (10240/27434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7f8a8e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c7f8a8b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c7f8a8ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18c0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18c04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18c0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18c0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7f8a2423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c7f8a24086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c7f8a08f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c7f86b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c7f86b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f18c0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18c04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18c04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7f86b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (1349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <
# | ...
# `---data was truncated (10240/66998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfd6e3256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfd6e2f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfd6e32cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd01d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd01d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd01d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd01d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd6dc823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfd6dc8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfd6dacf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfd6a5c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfd6a5be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd01d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd01d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd01d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd6a5bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (1350 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056283e04056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056283e03d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056283e040cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7466b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7466b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7466b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7466b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056283dfd623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056283dfd6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056283dfbaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056283dc6a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056283dc69e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7466b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7466b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7466b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056283dc69d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (1351 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad4d7a156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad4d79e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad4d7a1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0d0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0d058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0d0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0d051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad4d73723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad4d737086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad4d71bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad4d3cb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad4d3cae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe0d051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0d051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0d051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad4d3cad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (1352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055667891e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055667891b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055667891ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd40733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd4078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd40733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd4071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566788b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005566788b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556678898f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556678548166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556678547e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd4071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd4071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd4071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556678547d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (1353 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bc311856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bc3115505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bc3118cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69a4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69a40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69a4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69a4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bc30ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bc30ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bc3092f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bc2d42166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bc2d41e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f69a4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69a40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69a40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bc2d41d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (1354 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store targ
# | ...
# `---data was truncated (10240/14667) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cba58c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563cba589505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563cba58ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea8fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea8fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea8fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea8fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cba52223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563cba522086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563cba506f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563cba1b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563cba1b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fea8fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea8fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea8fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cba1b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (1355 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b75c6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b75c63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b75c66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbea9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbea9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbea9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbea9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b75bfc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b75bfc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b75be0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b75890166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b7588fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbea9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbea9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbea9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b7588fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (1356 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %bas
# | ...
# `---data was truncated (10240/60209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbea8f956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fbea8f6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fbea8f9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f141fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f141fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f141fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f141fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbea88f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fbea88f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fbea873f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fbea523166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fbea522e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f141fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f141fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f141fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbea522d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (1357 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560de58bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560de58b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560de58bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4691849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46918a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4691849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4691831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560de585223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560de5852086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560de5836f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560de54e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560de54e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4691832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46918330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46918330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560de54e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (1358 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fefb7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563fefb74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563fefb77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b48649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b486a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b48649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b48631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fefb0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563fefb0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563fefaf1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563fef7a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563fef7a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b48632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b486330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b486330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fef7a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (1359 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a567bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a567b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a567bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd4df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd4df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd4df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd4df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a5675223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a56752086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a56736f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a563e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a563e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd4df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd4df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd4df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a563e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (1360 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c645e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c645e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c645e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa06e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa06e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa06e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa06e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c6457a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c6457a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c6455ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c6420e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c6420de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa06e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa06e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa06e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c6420dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (1361 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afa71c456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055afa71c1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055afa71c4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fb8705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fb875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fb8705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fb86ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afa715a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055afa715a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055afa713ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055afa6dee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055afa6dede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7fb86eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fb86ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fb86ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afa6dedd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (1362 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d51f9e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d51f9e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d51f9e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5ff01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5ff0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5ff01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5ff003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d51f97923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d51f979086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d51f95df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d51f60d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d51f60ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff5ff004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5ff0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5ff0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d51f60cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (1363 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p2.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %retval = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %c = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   %coerce4 = alloca <4 x half>, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b1 = load <4 x half>, ptr %b, align 8
# |   store <2 x i32> %c.coerce, ptr %c, align 8
# |   %c2 = load <4 x half>, ptr %c, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b1, ptr %b.addr, align 8
# |   store <4 x half> %c2, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %1, ptr %coerce, align 8
# |   %3 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %2, ptr %coerce3, align 8
# |   %4 = load <2 x i32>, ptr %coerce3, align 8
# |   store <2 x i32> %3, ptr %__p1.i, align 8
# |   %__p11.i = load <4 x half>, ptr %__p1.i, align 8
# |   store <2 x i32> %4, ptr %__p2.i, align 8
# |   %__p22.i = load <4 x half>, ptr %__p2.i, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8
# |   store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %7 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %9, ptr %retval.i, align 8
# |   %10 = load <2 x i32>, ptr %retval.i, align 8
# |   store <2 x i32> %10, ptr %coerce4, align 8
# |   %11 = load <4 x half>, ptr %coerce4, align 8
# |   store <4 x half> %11, ptr %retval, align 8
# |   %12 = load <2 x i32>, ptr %retval, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p2.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %retval = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %c = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   %coerce4 = alloca <8 x half>, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b1 = load <8 x half>, ptr %b, align 16
# |   store <4 x i32> %c.coerce, ptr %c, align 16
# |   %c2 = load <8 x half>, ptr %c, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b1, ptr %b.addr, align 16
# |   store <8 x half> %c2, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %1, ptr %coerce, align 16
# |   %3 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %2, ptr %coerce3, align 16
# |   %4 = load <4 x i32>, ptr %coerce3, align 16
# |   store <4 x i32> %3, ptr %__p1.i, align 16
# |   %__p11.i = load <8 x half>, ptr %__p1.i, align 16
# |   store <4 x i32> %4, ptr %__p2.i, align 16
# |   %__p22.i = load <8 x half>, ptr %__p2.i, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16
# |   store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %7 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7)
# |   store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %9, ptr %retval.i, align 16
# |   %10 = load <4 x i32>, ptr %retval.i, align 16
# |   store <4 x i32> %10, ptr %coerce4, align 16
# |   %11 = load <8 x half>, ptr %coerce4, align 16
# |   store <8 x half> %11, ptr %retval, align 16
# |   %12 = load <4 x i32>, ptr %retval, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %a = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   store <2 x i32> %a.coerce, ptr %a, align 8
# |   %a1 = load <4 x half>, ptr %a, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b2 = load <4 x half>, ptr %b, align 8
# |   store <4 x half> %a1, ptr %a.addr, align 8
# |   store <4 x half> %b2, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %coerce, align 8
# |   %2 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %1, ptr %coerce3, align 8
# |   %3 = load <2 x i32>, ptr %coerce3, align 8
# |   call void @llvm.experimental.noalias.scope.decl(metadata !3)
# |   store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3
# |   %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3
# |   store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3
# |   %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3
# |   store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3
# |   store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3
# |   %6 = bitcast <8 x i8> %4 to <4 x i16>
# |   %7 = bitcast <8 x i8> %5 to <4 x i16>
# |   %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3
# |   %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %a = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   store <4 x i32> %a.coerce, ptr %a, align 16
# |   %a1 = load <8 x half>, ptr %a, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b2 = load <8 x half>, ptr %b, align 16
# |   store <8 x half> %a1, ptr %a.addr, align 16
# |   store <8 x half> %b2, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %coerce, align 16
# |   %2 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %1, ptr %coerce3, align 16
# |   %3 = load <4 x i32>, ptr %coerce3, align 16
# |   call void @llvm.experimental.noalias.scope.decl(metadata !6)
# |   store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6
# |   %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6
# |   store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6
# |   %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6
# |   store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6
# |   store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6
# |   %6 = bitcast <16 x i8> %4 to <8 x i16>
# |   %7 = bitcast <16 x i8> %5 to <8 x i16>
# |   %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6
# |   %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef
# | ...
# `---data was truncated (10240/35874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055bd2014856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bd20145505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bd20148cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e90733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e9078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e90733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e9071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd200de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bd200de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bd200c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bd1fd72166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bd1fd71e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e9071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e9071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e9071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd1fd71d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (1364 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606cebd556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606cebd2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606cebd5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c9b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c9b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c9b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c9b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606ceb6b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606ceb6b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606ceb4ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606ce7ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606ce7fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9c9b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c9b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c9b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606ce7fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (1365 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind 
# | ...
# `---data was truncated (10240/77062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056097a30956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056097a306505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056097a309cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f449ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f449ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f449ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f449ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056097a29f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056097a29f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056097a283f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560979f33166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560979f32e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f449ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f449ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f449ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560979f32d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (1366 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2297da56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c2297d7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c2297dacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16f9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16f96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16f9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16f9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c22977023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c229770086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c229754f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c229404166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c229403e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f16f9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16f96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16f96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c229403d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (1367 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6c63d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e6c63d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e6c63d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff831249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8312a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff831249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff831231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6c636a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e6c636a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e6c634ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e6c5ffe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e6c5ffde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff831232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8312330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8312330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6c5ffdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (1368 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625d560356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625d5600505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625d5603cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35eb21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35eb2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35eb21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35eb203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625d559923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005625d5599086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005625d557df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005625d522d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005625d522ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f35eb204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35eb2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35eb2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625d522cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (1369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642529c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005642529c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005642529c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c14f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c14f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c14f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c14f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056425295923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564252959086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056425293df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005642525ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005642525ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c14f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c14f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c14f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642525ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (1370 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdc974856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fdc9745505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fdc9748cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f4d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f4d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f4d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f4d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdc96de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fdc96de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fdc96c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fdc9372166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fdc9371e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5f4d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f4d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f4d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdc9371d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (1371 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055640de6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055640de65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055640de68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4761449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47614a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4761449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4761431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055640ddfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055640ddfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055640dde2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055640da92166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055640da91e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4761432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47614330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47614330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055640da91d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (1372 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561aa5d9956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561aa5d96505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561aa5d99cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d9c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d9c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d9c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d9c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aa5d2f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561aa5d2f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561aa5d13f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561aa59c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561aa59c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d9c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d9c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d9c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aa59c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (1373 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vasub_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055726bb2d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055726bb2a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055726bb2dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88bf705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88bf75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88bf705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88bf6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055726bac323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055726bac3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055726baa7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055726b757166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055726b756e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f88bf6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88bf6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88bf6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055726b756d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (1374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> poison, half %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> poison, half %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> poison, half %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> poison, half %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> poison, half %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> poison, half %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> poison, float %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> poison, float %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> poison, float %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> poison, float %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float> poison, float %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double> poison, double %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double> poison, double %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(<vscale x 4 x double> poison, double %0, i64 %1)
# |   
# | ...
# `---data was truncated (10240/30849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16817956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c168176505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c168179cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96d2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96d2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96d2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96d2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c16810f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c16810f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1680f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c167da3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c167da2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f96d2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96d2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96d2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c167da2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (1375 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a321e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558a321e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558a321e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa903649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9036a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa903649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa903631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a3217b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558a3217b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558a3215ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558a31e0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558a31e0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa903632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9036330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9036330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a31e0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (1376 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555773b2656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555773b23505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555773b26cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0acbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0acbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0acbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0acbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555773abc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555773abc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555773aa0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555773750166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055577374fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0acbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0acbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0acbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055577374fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (1377 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586cb6c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005586cb6c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005586cb6c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b93d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b93d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b93d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b93d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586cb65b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005586cb65b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005586cb63ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586cb2ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586cb2eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7b93d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b93d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b93d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586cb2eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (1378 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575f2b6f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005575f2b6c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005575f2b6fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe562733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe56278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe562733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe56271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575f2b0523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005575f2b05086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005575f2ae9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005575f2799166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005575f2798e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe56271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe56271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe56271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575f2798d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (1379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db685d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055db685d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055db685d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ab3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ab398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ab3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ab391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db6856d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055db6856d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055db68551f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055db68201166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055db68200e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ab391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ab391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ab391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db68200d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (1380 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %low.addr = alloca <4 x half>, align 8
# |   %high.addr = alloca <4 x half>, align 8
# |   store <4 x half> %low, ptr %low.addr, align 8
# |   store <4 x half> %high, ptr %high.addr, align 8
# |   %0 = load <4 x half>, ptr %low.addr, align 8
# |   %1 = load <4 x half>, ptr %high.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 {
# | entry:
# |   %__p0.addr.
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7d831856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a7d8315505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a7d8318cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52a9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52a938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52a9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52a931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7d82ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a7d82ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a7d8292f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a7d7f42166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a7d7f41e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f52a931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52a931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52a931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7d7f41d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (1381 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2f4c4956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2f4c46505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2f4c49cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe64b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe64b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe64b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe64b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2f4bdf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f2f4bdf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f2f4bc3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f2f4873166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f2f4872e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe64b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe64b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe64b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2f4872d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (1382 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -252)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 -243)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 195)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 8978432)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 27391)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 -5570561)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 -18689)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 1023410175)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -11265)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -13893633)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -37)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -1644167169)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 13568)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 654311424)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 175)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 89)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce8352a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce83527505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce8352acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc150d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc150d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc150d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc150d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce834c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce834c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce834a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce83154166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce83153e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc150d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc150d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc150d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce83153d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (1383 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<vscale x
# | ...
# `---data was truncated (10240/11396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648b9d8c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005648b9d89505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005648b9d8ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5878049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58780a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5878049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5878031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648b9d2223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005648b9d22086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005648b9d06f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005648b99b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005648b99b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5878032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58780330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58780330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648b99b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (1384 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfeb00d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bfeb00a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bfeb00dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba4af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba4af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba4af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba4af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfeafa323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bfeafa3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bfeaf87f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bfeac37166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bfeac36e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fba4af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba4af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba4af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfeac36d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (1385 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>
# | ...
# `---data was truncated (10240/76635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c7c30756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c7c304505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c7c307cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fb8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fb818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fb8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fb811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c7c29d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c7c29d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c7c281f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c7bf31166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c7bf30e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7fb811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fb811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fb811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c7bf30d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (1386 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a734a9b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a734a98505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a734a9bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9113049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91130a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9113049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9113031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a734a3123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a734a31086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a734a15f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a7346c5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a7346c4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9113032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91130330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91130330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7346c4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (1387 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2938cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2938c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2938cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7931249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79312a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7931249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7931231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f29386123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f293861086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f293845f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f2934f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f2934f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7931232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79312330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79312330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2934f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (1388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d76fb0d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d76fb0a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d76fb0dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaded1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d76faa323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d76faa3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d76fa87f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d76f737166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d76f736e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feaded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaded1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d76f736d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (1389 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7084cd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c7084ca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c7084cdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08ebb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08ebb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08ebb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08ebaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c70846323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c708463086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c708447f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c7080f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c7080f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f08ebaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08ebaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08ebaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7080f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (1390 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i16>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i32>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, <vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void
# | ...
# `---data was truncated (10240/179328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a01a8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556a01a87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556a01a8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb24f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb24f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb24f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb24f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a01a2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556a01a20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556a01a04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556a016b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556a016b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feb24f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb24f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb24f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a016b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (1391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee8528d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee8528a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee8528dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cf7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cf718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cf7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cf711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee8522323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee85223086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee85207f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee84eb7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee84eb6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9cf711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cf711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cf711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee84eb6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (1392 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555839bc956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555839bc6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555839bc9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7508533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f750858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7508533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f750851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555839b5f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555839b5f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555839b43f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558397f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558397f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f750851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f750851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f750851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558397f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (1393 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dde9d4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dde9d4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dde9d4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc65fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc65faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc65fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc65fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dde9ce523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dde9ce5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dde9cc9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dde9979166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dde9978e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc65fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc65fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc65fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dde9978d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (1394 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005597400a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005597400a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005597400a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9c9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9c9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9c9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9c9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055974003923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559740039086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055974001df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055973fccd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055973fccce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb9c9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9c9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9c9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055973fcccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (1395 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load 
# | ...
# `---data was truncated (10240/29128) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a729f5156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a729f4e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a729f51cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63e3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63e3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63e3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63e3aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a729ee723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a729ee7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a729ecbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a729b7b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a729b7ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f63e3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63e3aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63e3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a729b7ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (1396 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1d020f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e1d020c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e1d020fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f84e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f84ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f84e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f84e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1d01a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e1d01a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1d0189f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e1cfe39166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e1cfe38e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f84e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f84e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f84e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1cfe38d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (1397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f2396456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560f23961505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560f23964cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78d2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78d2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78d2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78d2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f238fa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560f238fa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560f238def39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560f2358e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560f2358de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78d2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78d2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78d2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f2358dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (1398 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055670f5f956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055670f5f6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055670f5f9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4be1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4be158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4be1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4be151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055670f58f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055670f58f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055670f573f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055670f223166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055670f222e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4be151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4be151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4be151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055670f222d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (1399 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/80640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a7239956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a72396505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a72399cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb765733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb76578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb765733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb76571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a7232f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a7232f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a72313f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a71fc3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a71fc2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb76571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb76571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb76571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a71fc2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (1400 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nof
# | ...
# `---data was truncated (10240/11966) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583744fb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005583744f8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005583744fbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff808333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff80838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff808333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff80831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055837449123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558374491086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558374475f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558374125166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558374124e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff80831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff80831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff80831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558374124d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (1401 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7fcbd256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f7fcbcf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f7fcbd2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e44c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e44c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e44c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e44c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7fcb6823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f7fcb68086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f7fcb4cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7fc7fc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7fc7fbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e44c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e44c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e44c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7fc7fbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (1402 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = mul <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = mul <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = mul <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fmul <4 x float> %0, %1
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.m
# | ...
# `---data was truncated (10240/21288) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055acf657e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055acf657b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055acf657ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92ab849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92ab8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92ab849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92ab831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acf651423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055acf6514086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055acf64f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055acf61a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055acf61a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f92ab832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92ab8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92ab8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acf61a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (1403 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558df8d4856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558df8d45505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558df8d48cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4abe505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4abe55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4abe505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4abe4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558df8cde23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558df8cde086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558df8cc2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558df8972166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558df8971e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4abe4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4abe4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4abe4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558df8971d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (1404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f047de156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f047dde505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f047de1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfcb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfcb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfcb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfcb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f047d7723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f047d77086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f047d5bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f047a0b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f047a0ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdfcb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfcb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfcb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f047a0ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (1405 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a489b056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a489ad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a489b0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa204b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa204b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa204b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa204b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a4894623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a48946086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a4892af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a485da166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a485d9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa204b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa204b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa204b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a485d9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (1406 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055707d74a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055707d747505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055707d74acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd817449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd817449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd817431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055707d6e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055707d6e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055707d6c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055707d374166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055707d373e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd817432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8174330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055707d373d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (1407 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bfc53556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555bfc532505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555bfc535cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4236f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4236f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4236f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4236f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bfc4cb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555bfc4cb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555bfc4aff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555bfc15f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555bfc15ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4236f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4236f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4236f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bfc15ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (1408 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr 
# | ...
# `---data was truncated (10240/18895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056414b41d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056414b41a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056414b41dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a99a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a99a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a99a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a99a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056414b3b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056414b3b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056414b397f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056414b047166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056414b046e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a99a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a99a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a99a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056414b046d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (1409 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/142024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055812d4a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055812d49f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055812d4a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f781e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f781e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f781e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f781e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055812d43823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055812d438086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055812d41cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055812d0cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055812d0cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f781e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f781e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f781e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055812d0cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (1410 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale
# | ...
# `---data was truncated (10240/410383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0d266a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b0d2667505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b0d266acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc61f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc61f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc61f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc61f203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0d260023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0d2600086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0d25e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b0d2294166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b0d2293e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc61f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc61f2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc61f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0d2293d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (1411 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571c672756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005571c6724505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005571c6727cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9e6705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9e675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9e6705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9e66ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571c66bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571c66bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571c66a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571c6351166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571c6350e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9e66eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9e66ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9e66ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571c6350d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (1412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a28e9d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a28e9a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a28e9dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f134b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f134b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f134b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f134b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a28e3323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a28e33086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a28e17f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a28ac7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a28ac6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f134b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f134b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f134b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a28ac6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (1413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b05e7856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b05e75505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b05e78cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ce1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ce175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ce1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ce16ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b05e0e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b05e0e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b05df2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b05aa2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b05aa1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ce16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ce16ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ce16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b05aa1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (1414 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 
# | ...
# `---data was truncated (10240/69943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcc0f8b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fcc0f88505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fcc0f8bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ff4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ff4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ff4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ff4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcc0f2123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fcc0f21086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fcc0f05f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fcc0bb5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fcc0bb4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0ff4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ff4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ff4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcc0bb4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (1415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d914b7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d914b74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d914b77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac8da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac8daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac8da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac8da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d914b0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d914b0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d914af1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9147a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9147a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac8da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac8da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac8da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9147a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (1416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605c590156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005605c58fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005605c5901cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddfef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddfef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddfef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddfef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605c589723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005605c5897086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005605c587bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005605c552b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005605c552ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fddfef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddfef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddfef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605c552ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (1417 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsc
# | ...
# `---data was truncated (10240/65905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558379a6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558379a65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558379a68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d2ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d2ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d2ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d2ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583799fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005583799fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005583799e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558379692166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558379691e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d2ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d2ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d2ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558379691d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (1418 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <
# | ...
# `---data was truncated (10240/84810) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056352c04e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056352c04b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056352c04ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ff9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ff918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ff9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ff911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056352bfe423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056352bfe4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056352bfc8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056352bc78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056352bc77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ff911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ff911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ff911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056352bc77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (1419 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i)
# |   store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i)
# |   store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i)
# |   store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i)
# |   store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i)
# |   store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i)
# |   store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/162735) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005602aab9256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005602aab8f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005602aab92cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa497849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa497849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa497831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602aab2823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005602aab28086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005602aab0cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005602aa7bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005602aa7bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa497832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4978330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602aa7bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (1420 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr =
# | ...
# `---data was truncated (10240/124514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f68ee556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f68ee2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f68ee5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4478c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4478ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4478c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4478c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f68e7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f68e7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f68e5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f68b0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f68b0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4478c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4478c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4478c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f68b0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (1421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056304628856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563046285505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563046288cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbca8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbca858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbca8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbca851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056304621e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056304621e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563046202f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563045eb2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563045eb1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbca851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbca851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbca851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563045eb1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (1422 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564e1de456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005564e1de1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005564e1de4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb04a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb04aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb04a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb04a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564e1d7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005564e1d7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005564e1d5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005564e1a0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005564e1a0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feb04a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb04a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb04a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564e1a0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (1423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618ff98d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005618ff98a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005618ff98dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e3f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e3f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e3f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e3f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618ff92323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005618ff923086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005618ff907f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005618ff5b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005618ff5b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4e3f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e3f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e3f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618ff5b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (1424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e21a79356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e21a790505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e21a793cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f168b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f168b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f168b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f168b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e21a72923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e21a729086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e21a70df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e21a3bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e21a3bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f168b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f168b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f168b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e21a3bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (1425 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627371f856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005627371f5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005627371f8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3ffe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3ffea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3ffe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3ffe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056273718e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056273718e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562737172f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562736e22166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562736e21e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa3ffe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3ffe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3ffe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562736e21d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (1426 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c56af4056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c56af3d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c56af40cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c14905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c1495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c14905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c148ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c56aed623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c56aed6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c56aebaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c56ab6a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c56ab69e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9c148eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c148ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c148ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c56ab69d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (1427 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056118ce2756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056118ce24505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056118ce27cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aba733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aba78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aba733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aba71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056118cdbd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056118cdbd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056118cda1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056118ca51166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056118ca50e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0aba71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aba71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aba71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056118ca50d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (1428 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/153813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056344870956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563448706505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563448709cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00b3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00b38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00b3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00b3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056344869f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056344869f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563448683f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563448333166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563448332e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f00b3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00b38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00b38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563448332d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (1429 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlastb_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlastb_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlastb_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f541bcc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f541bc9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f541bcccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee6e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee6e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee6e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee6e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f541b6223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f541b62086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f541b46f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5417f6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5417f5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fee6e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee6e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee6e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5417f5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (1430 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f1a98c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f1a989505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f1a98ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f951ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f951cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f951ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f951ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f1a92223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f1a922086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f1a906f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f1a5b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f1a5b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f951ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f951ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f951ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f1a5b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (1431 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e06bc656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e06bc3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e06bc6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb106a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb106aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb106a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb106a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e06b5c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e06b5c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e06b40f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e067f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e067efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb106a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb106a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb106a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e067efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (1432 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601f6d2656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005601f6d23505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601f6d26cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c4fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c4fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c4fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c4fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601f6cbc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005601f6cbc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005601f6ca0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601f6950166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601f694fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4c4fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c4fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c4fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601f694fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/builtins-arm64.c (1433 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load ptr, ptr %b.addr, align 8
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @tp() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbitl(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.bitreverse.i64(i64) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbit64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @hints() #0 {
# | entry:
# |   call void @llvm.aarch64.hint(i32 0)
# |   call void @llvm.aarch64.hint(i32 1)
# |   call void @llvm.aarch64.hint(i32 2)
# |   call void @llvm.aarch64.hint(i32 3)
# |   call void @llvm.aarch64.hint(i32 4)
# |   call void @llvm.aarch64.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.aarch64.hint(i32) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @barriers() #0 {
# | entry:
# |   call void @llvm.aarch64.dmb(i32 1)
# |   call void @llvm.aarch64.dsb(i32 2)
# |   call void @llvm.aarch64.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dmb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dsb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.isb(i32) #5
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch_x() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @read_intent_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch.ir(ptr null)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @jcvt(double noundef %v) #7 {
# | entry:
# |   %v.addr = alloca double, align 8
# |   store double %v, ptr %v.addr, align 8
# |   %0 = load double, ptr %v.addr, align 8
# |   %1 = call i32 @llvm.aarch64.fjcvtzs(double %0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.fjcvtzs(double) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rsr() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = trunc i64 %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i64 @llvm.read_volatile_register.i64(metadata) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rsr64() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @rsrp() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = inttoptr i64 %0 to ptr
# |   ret ptr %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %1 = zext i32 %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nounwind
# | declare void @llvm.write_register.i64(metadata, i64) #8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr64(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   call void @llvm.write_register.i64(metadata !7, i64 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsrp(ptr noundef %v) #0 {
# | entry:
# |   %v.addr = alloca ptr, align 8
# |   store ptr %v, ptr %v.addr, align 8
# |   %0 = load ptr, ptr %v.addr, align 8
# |   %1 = ptrtoint ptr %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cls(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %cls = call i32 @llvm.aarch64.cls(i32 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsl(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls64(i64) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsll(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndr(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndr()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndr() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndrrs()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndrrs() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @trap() #0 {
# | entry:
# |   call void @llvm.aarch64.break(i32 42)
# |   ret void
# | }
# | 
# | ; Function Attrs: cold noreturn nounwind
# | declare void @llvm.aarch64.break(i32 immarg) #10
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca i64, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8
# |   %2 = load ptr, ptr %a.addr, align 8
# |   %3 = load i64, ptr %b.addr, a
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   243 |   __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint
# |       |   ^                                                            ~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type]
# |   305 |   __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type]
# |   306 |   __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type]
# |   307 |   __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH);
# |       |   ^                                                                ~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   308 |   return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5);
# |       |          ^                                                                ~
# | 5 warnings generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603e0ae856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603e0ae5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603e0ae8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b33c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b33ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b33c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b33c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603e0a7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005603e0a7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005603e0a62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005603e0712166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005603e0711e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b33c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b33c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b33c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603e0711d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (1434 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6bd06c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a6bd069505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a6bd06ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef5b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef5b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef5b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef5b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6bd00223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a6bd002086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a6bcfe6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a6bcc96166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a6bcc95e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef5b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef5b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef5b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6bcc95d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (1435 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c031c156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c031be505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c031c1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa48c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa48c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa48c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa48c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c0315723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c03157086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c0313bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c02deb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c02deae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa48c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa48c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa48c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c02dead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (1436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fc6d6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563fc6d63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563fc6d66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9939133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f993918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9939133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f993911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fc6cfc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563fc6cfc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563fc6ce0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563fc6990166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563fc698fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f993911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f993911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f993911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fc698fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (1437 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b120a0a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b120a07505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b120a0acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3be821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3be82725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3be821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3be8203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1209a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b1209a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b120984f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b120634166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b120633e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3be8204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3be82050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3be82050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b120633d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (1438 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580766cd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005580766ca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005580766cdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fcc705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fcc75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fcc705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fcc6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055807666323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558076663086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558076647f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005580762f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005580762f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6fcc6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fcc6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fcc6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580762f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (1439 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc312f456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc312f1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc312f4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e70105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e7015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e70105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e700ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc3128a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc3128a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc3126ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc30f1e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc30f1de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e700eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e700ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e700ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc30f1dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (1440 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f314f8c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f314f89505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f314f8ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c90533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c9058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c90533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c9051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f314f2223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f314f22086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f314f06f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f314bb6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f314bb5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c9051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c9051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c9051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f314bb5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (1441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_
# | ...
# `---data was truncated (10240/10440) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8babe856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e8babe5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e8babe8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb038849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0388a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb038849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb038831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8bab7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e8bab7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8bab62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e8ba812166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e8ba811e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb038832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0388330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0388330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8ba811d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (1442 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056397a3ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056397a3aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056397a3adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f307fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f307fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f307fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f307faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056397a34323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056397a343086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056397a327f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563979fd7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563979fd6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f307faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f307faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f307faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563979fd6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (1443 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e57867256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e57866f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e578672cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c8e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c8e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c8e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c8e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e57860823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e578608086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e5785ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e57829c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e57829be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8c8e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c8e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c8e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e57829bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (1444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a6394156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a6393e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a63941cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b40333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b4038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b40333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b4031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a638d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a638d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a638bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a6356b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a6356ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b4031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b4031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b4031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a6356ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (1445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd0630f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd0630c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd0630fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f564a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f564a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f564a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f564a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd062a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd062a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd06289f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd05f39166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd05f38e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f564a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f564a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f564a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd05f38d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (1446 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d7d68c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d7d689505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d7d68ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1e8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1e858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1e8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1e851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d7d62223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d7d622086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d7d606f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d7d2b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d7d2b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb1e851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1e851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1e851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d7d2b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (1447 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bc4bf856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556bc4bf5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556bc4bf8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaf8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaf895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaf8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaf88ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bc4b8e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556bc4b8e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556bc4b72f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556bc4822166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556bc4821e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffaf88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaf88ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaf88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bc4821d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (1448 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb9133b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb91338505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb9133bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff392933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff39298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff392933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff39291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb912d123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb912d1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb912b5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb90f65166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb90f64e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff39291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff39291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff39291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb90f64d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (1449 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a54660f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a54660c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a54660fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7e0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7e018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7e0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7e011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5465a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a5465a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a546589f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a546239166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a546238e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa7e011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7e011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7e011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a546238d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (1450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vsc
# | ...
# `---data was truncated (10240/41579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653d459256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005653d458f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005653d4592cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8097505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f809755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8097505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80974ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653d452823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005653d4528086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005653d450cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653d41bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653d41bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80974eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80974ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80974ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653d41bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (1451 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ae08bf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560ae08bc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560ae08bfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9dec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9dec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9dec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9dec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ae085523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560ae0855086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560ae0839f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560ae04e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560ae04e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc9dec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9dec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9dec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ae04e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (1452 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a77dfa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563a77df7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563a77dfacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cef649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cef6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cef649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cef631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a77d9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563a77d90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563a77d74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563a77a24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563a77a23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8cef632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cef6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cef6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a77a23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (1453 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfirst_b(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557171ca156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557171c9e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557171ca1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d4fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d4fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d4fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d4fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557171c3723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557171c37086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557171c1bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571718cb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571718cae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d4fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d4fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d4fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571718cad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (1454 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a88d9cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a88d9c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a88d9cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcebfd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcebfd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcebfd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcebfced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a88d96123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a88d961086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a88d945f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a88d5f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a88d5f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcebfceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcebfcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcebfcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a88d5f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (1455 of 27911)
******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type { ptr, ptr, %struct.A }
# | %struct.A = type { i32 }
# | 
# | $_ZTV1B = comdat any
# | 
# | $_ZTI1B = comdat any
# | 
# | $_ZTS1B = comdat any
# | 
# | $_ZTI1A = comdat any
# | 
# | $_ZTS1A = comdat any
# | 
# | @y = local_unnamed_addr global i8 2, align 1
# | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8
# | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8
# | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8
# | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr]
# | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1
# | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8
# | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr]
# | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x0000557ea37f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557ea37ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557ea37f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f855a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f855a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f855a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f855a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea378723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557ea3787086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557ea376bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557ea341b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557ea341ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f855a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f855a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f855a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea341ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (1456 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6b24e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6b24e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6b24e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd88b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd88b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd88b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd88b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6b247a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6b247a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6b245ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6b210e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6b210de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd88b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd88b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd88b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6b210dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (1457 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vundefined_f16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vundefined_f16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vundefined_f16m1() #0 {
# | entry:
# |   ret <vscale x 4 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vundefined_f16m2() #0 {
# | entry:
# |   ret <vscale x 8 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vundefined_f16m4() #0 {
# | entry:
# |   ret <vscale x 16 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vundefined_f16m8() #0 {
# | entry:
# |   ret <vscale x 32 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vundefined_f32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vundefined_f32m1() #0 {
# | entry:
# |   ret <vscale x 2 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vundefined_f32m2() #0 {
# | entry:
# |   ret <vscale x 4 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vundefined_f32m4() #0 {
# | entry:
# |   ret <vscale x 8 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vundefined_f32m8() #0 {
# | entry:
# |   ret <vscale x 16 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vundefined_f64m1() #0 {
# | entry:
# |   ret <vscale x 1 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vundefined_f64m2() #0 {
# | entry:
# |   ret <vscale x 2 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vundefined_f64m4() #0 {
# | entry:
# |   ret <vscale x 4 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vundefined_f64m8() #0 {
# | entry:
# |   ret <vscale x 8 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_i8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_i8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_i8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_i8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_i8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_i8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_i8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_i16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_i16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_i16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_i16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_i16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_i16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_i32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_i32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_i32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_i32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_i32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_i64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_i64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_i64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_i64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_u8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_u8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_u8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_u8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_u8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_u8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_u8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_u16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_u16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_u16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_u16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_u16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_u16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_u32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_u32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_u32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_u32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_u32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_u64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_u64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_u64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_u64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/63140) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606b387e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606b387b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606b387ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ce2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ce278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ce2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ce271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606b381423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606b3814086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606b37f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606b34a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606b34a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ce271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ce271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ce271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606b34a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (1458 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a4251456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555a42511505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555a42514cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34c5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34c52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34c5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34c5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a424aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555a424aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555a4248ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555a4213e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555a4213de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f34c5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34c52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34c52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a4213dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (1459 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558702ed656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558702ed3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558702ed6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf83733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf8378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf83733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf8371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558702e6c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558702e6c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558702e50f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558702b00166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558702affe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faf8371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf8371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf8371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558702affd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (1460 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, a
# | ...
# `---data was truncated (10240/98437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628ef26b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005628ef268505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005628ef26bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb06a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb06a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb06a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb06a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628ef20123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005628ef201086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005628ef1e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005628eee95166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005628eee94e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb06a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb06a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb06a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628eee94d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (1461 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64.p0(<vscale x 8 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale 
# | ...
# `---data was truncated (10240/39900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bd475556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bd4752505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bd4755cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6258905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f625895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6258905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62588ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bd46eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bd46eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bd46cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bd437f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bd437ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62588eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62588ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62588ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bd437ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (1462 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = loa
# | ...
# `---data was truncated (10240/18917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e742bd156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e742bce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e742bd1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f547cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f547cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f547cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f547cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e742b6723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e742b67086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e742b4bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7427fb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7427fae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f547cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f547cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f547cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7427fad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (1463 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055583003256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055583002f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555830032cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7430049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74300a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7430049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7430031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055582ffc823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055582ffc8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055582ffacf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055582fc5c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055582fc5be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7430032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74300330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74300330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055582fc5bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (1464 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf4048d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf4048a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf4048dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47d0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47d02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47d0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47d0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf4042323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf40423086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf40407f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf400b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf400b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47d0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47d02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47d02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf400b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (1465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f0408c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f04089505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f0408ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb8e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb8e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb8e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb8e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f0402223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f04022086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f04006f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f03cb6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f03cb5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb8e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb8e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb8e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f03cb5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (1466 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b7478c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b74789505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b7478ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98af333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98af38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98af333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98af31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b7472223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b74722086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b74706f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b743b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b743b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f98af31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98af31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98af31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b743b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (1467 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622f43b356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005622f43b0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005622f43b3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0d331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622f434923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005622f4349086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005622f432df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005622f3fdd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005622f3fdce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0d331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622f3fdcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (1468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b11ba3a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b11ba37505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b11ba3acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a02a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a02aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a02a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a02a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b11b9d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b11b9d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b11b9b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b11b664166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b11b663e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4a02a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a02a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a02a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b11b663d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (1469 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e30f7d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e30f7a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e30f7dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1aab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1aab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1aab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1aab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e30f1323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e30f13086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e30ef7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e30ba7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e30ba6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc1aab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1aab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1aab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e30ba6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (1470 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fde607e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fde607b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fde607ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8eadc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8eadca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8eadc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8eadc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fde601423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fde6014086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fde5ff8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fde5ca8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fde5ca7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8eadc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8eadc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8eadc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fde5ca7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (1471 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bi
# | ...
# `---data was truncated (10240/136481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a11f6be56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a11f6bb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a11f6becab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf38249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf382a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf38249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf38231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a11f65423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a11f654086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a11f638f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a11f2e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a11f2e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcf38232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf382330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf382330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a11f2e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (1472 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b1c08956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b1c086505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b1c089cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3b2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3b24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3b2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3b2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b1c01f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b1c01f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b1c003f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b1bcb3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b1bcb2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3b2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3b24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3b24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b1bcb2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (1473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a329e6256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a329e5f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a329e62cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff688705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff68875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff688705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6886ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a329df823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a329df8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a329ddcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a329a8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a329a8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff6886eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6886ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6886ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a329a8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (1474 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df15b0e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055df15b0b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055df15b0ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f364b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f364b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f364b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f364b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df15aa423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055df15aa4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055df15a88f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055df15738166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055df15737e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f364b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f364b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f364b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df15737d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (1475 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ff4af456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561ff4af1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561ff4af4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fa5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fa56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fa5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fa5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ff4a8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561ff4a8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561ff4a6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561ff471e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561ff471de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0fa5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fa56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fa56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ff471dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (1476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056252e4df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056252e4dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056252e4dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2e9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2e998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2e9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2e991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056252e47523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056252e475086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056252e459f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056252e109166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056252e108e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2e991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2e991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2e991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056252e108d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (1477 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <v
# | ...
# `---data was truncated (10240/157467) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055635cfe956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055635cfe6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055635cfe9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1500b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1500b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1500b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1500b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055635cf7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055635cf7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055635cf63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055635cc13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055635cc12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1500b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1500b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1500b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055635cc12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (1478 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f64fbd356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f64fbd0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f64fbd3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc501c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc501ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc501c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc501c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f64fb6923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f64fb69086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f64fb4df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f64f7fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f64f7fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc501c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc501c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc501c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f64f7fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (1479 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc92f6b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dc92f68505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dc92f6bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a79849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a798a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a79849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a79831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc92f0123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dc92f01086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dc92ee5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dc92b95166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dc92b94e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a79832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a798330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a798330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc92b94d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (1480 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0f9f4e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0f9f4b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0f9f4ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ec1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ec195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ec1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ec18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0f9ee423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c0f9ee4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c0f9ec8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c0f9b78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c0f9b77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ec18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ec18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ec18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0f9b77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (1481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c4af9856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c4af95505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c4af98cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f95449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f954a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f95449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f95431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c4af2e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c4af2e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c4af12f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c4abc2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c4abc1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5f95432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f954330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f954330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c4abc1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (1482 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect
# | ...
# `---data was truncated (10240/32932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3a962f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e3a962c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e3a962fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5124333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f512438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5124333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f512431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3a95c523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e3a95c5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3a95a9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e3a9259166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e3a9258e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f512431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f512431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f512431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3a9258d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (1483 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ff1f7456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561ff1f71505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561ff1f74cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12eea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12eea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12eea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12eea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ff1f0a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561ff1f0a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561ff1eeef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561ff1b9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561ff1b9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f12eea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12eea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12eea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ff1b9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (1484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv
# | ...
# `---data was truncated (10240/53548) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f769bd156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f769bce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f769bd1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b74849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b748a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b74849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b74831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f769b6723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f769b67086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f769b4bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7697fb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7697fae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b74832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b748330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b748330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7697fad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (1485 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055769bab756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055769bab4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055769bab7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd32d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd32d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd32d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd32d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055769ba4d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055769ba4d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055769ba31f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055769b6e1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055769b6e0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd32d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd32d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd32d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055769b6e0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (1486 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae162e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae162e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae162e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fd6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fd68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fd6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fd6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae1627a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae1627a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae1625ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae15f0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae15f0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6fd6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fd68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fd68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae15f0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (1487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c1e4c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c1e4c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c1e4c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f926a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f926a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f926a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f926a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c1e45b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c1e45b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c1e43ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c1e0ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c1e0eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f926a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f926a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f926a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c1e0eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (1488 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d4a31856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d4a315505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d4a318cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8625d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8625d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8625d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8625d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d4a2ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d4a2ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d4a292f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d49f42166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d49f41e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8625d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8625d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8625d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d49f41d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (1489 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e17daa656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e17daa3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e17daa6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a54133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a5418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a54133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a5411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e17da3c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e17da3c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e17da20f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e17d6d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e17d6cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a5411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a5411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a5411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e17d6cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (1490 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/39586) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f24440156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2443fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f244401cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26f6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26f618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26f6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26f611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f24439723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f244397086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f24437bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f24402b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f24402ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f26f611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26f611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26f611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f24402ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (1491 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 
# | ...
# `---data was truncated (10240/73182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aed942956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aed9426505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aed9429cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ae541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ae54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ae541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ae5403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aed93bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aed93bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aed93a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aed9053166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aed9052e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ae5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ae54050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ae54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aed9052d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (1492 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_rsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %splat.splat = shufflevector <vscale x 16 x i8> %splat.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %shl = shl <vscale x 16 x i8> %0, %splat.splat
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_lsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %0, i64 0
# |   %splat.splat
# | ...
# `---data was truncated (10240/32491) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005597466ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005597466ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005597466aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfd8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfd8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfd8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfd8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055974664423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559746644086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559746628f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005597462d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005597462d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdfd8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfd8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfd8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597462d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (1493 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, pt
# | ...
# `---data was truncated (10240/73955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634c80c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005634c80c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005634c80c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09f8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09f8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09f8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09f8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634c805b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634c805b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005634c803ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005634c7cef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005634c7ceee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f09f8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09f8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09f8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634c7ceed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (1494 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp eq <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 2 x double> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @neq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ne <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @neq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @neq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @neq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @neq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   stor
# | ...
# `---data was truncated (10240/44453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056082e5b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056082e5b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056082e5b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f66c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f66ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f66c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f66c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056082e54a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056082e54a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056082e52ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056082e1de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056082e1dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f66c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f66c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f66c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056082e1ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (1495 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ee1670356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee16700505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee16703cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cccb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cccb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cccb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cccb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee1669923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee16699086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee1667df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee1632d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee1632ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0cccb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cccb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cccb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee1632cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (1496 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559025ec556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559025ec2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559025ec5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcae2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcae278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcae2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcae271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559025e5b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559025e5b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559025e3ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559025aef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559025aeee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcae271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcae271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcae271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559025aeed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (1497 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e65af5f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e65af5c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e65af5fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9250133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f925018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9250133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f925011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e65aef523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e65aef5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e65aed9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e65ab89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e65ab88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f925011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f925011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f925011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e65ab88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (1498 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e90d67256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e90d66f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e90d672cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b99c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b99ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b99c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b99c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e90d60823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e90d608086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e90d5ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e90d29c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e90d29be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6b99c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b99c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b99c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e90d29bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (1499 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055998cf5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055998cf53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055998cf56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0110f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0110f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0110f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0110f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055998ceec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055998ceec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055998ced0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055998cb80166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055998cb7fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0110f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0110f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0110f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055998cb7fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (1500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c99d50456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c99d501505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c99d504cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1075c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1075c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1075c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1075c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c99d49a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c99d49a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c99d47ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c99d12e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c99d12de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1075c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1075c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1075c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c99d12dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (1501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local signext i32 @test() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
# |   %conv = trunc i64 %0 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636503ca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636503c7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636503cacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8608d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8608d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8608d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8608d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056365036023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563650360086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563650344f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056364fff4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056364fff3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8608d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8608d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8608d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056364fff3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (1502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2d151156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2d150e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2d1511cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc605933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc60598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc605933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc60591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2d14a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2d14a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2d148bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2d113b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2d113ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc60591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc60591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc60591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2d113ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (1503 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d436c6a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d436c67505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d436c6acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f656f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f656f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f656f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f656f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d436c0023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d436c00086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d436be4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d436894166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d436893e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f656f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f656f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f656f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d436893d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (1504 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055889170b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558891708505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055889170bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32e9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32e918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32e9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32e911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588916a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005588916a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558891685f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558891335166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558891334e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f32e911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32e911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32e911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558891334d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (1505 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561431e5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561431e53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561431e56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f924cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f924cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f924cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f924cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561431dec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561431dec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561431dd0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561431a80166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561431a7fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f924cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f924cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f924cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561431a7fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (1506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c69ed256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c69ecf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c69ed2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a70a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a70aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a70a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a70a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c69e6823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c69e68086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c69e4cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c69afc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c69afbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1a70a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a70a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a70a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c69afbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (1507 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/72135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056204652656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562046523505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562046526cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0287133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f028718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0287133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f028711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620464bc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005620464bc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005620464a0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562046150166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056204614fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f028711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f028711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f028711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056204614fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (1508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dab7ca256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dab7c9f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dab7ca2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f157fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f157faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f157fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f157fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dab7c3823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dab7c38086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dab7c1cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dab78cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dab78cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f157fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f157fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f157fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dab78cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (1509 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/83080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571aa4f456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005571aa4f1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005571aa4f4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d2e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d2e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d2e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d2e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571aa48a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571aa48a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571aa46ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571aa11e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571aa11de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d2e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d2e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d2e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571aa11dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (1510 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vsqrth_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %vsqrt, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %__s2 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load half, ptr %__s0, align 2
# |   %4 = load half, ptr %__s1, align 2
# |   %5 = load half, ptr %__s2, align 2
# |   %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %6, ptr %ref.tmp, align 2
# |   %7 = load half, ptr %ref.tmp, align 2
# |   store half %7, ptr %__ret, align 2
# |   %8 = load half, ptr %__ret, align 2
# |   store half %8, ptr %tmp, align 2
# |   %9 = load half, ptr %tmp, align 2
# |   ret half %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# |  #0 0x0000557e010e056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e010dd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e010e0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19d2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19d20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19d2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19d2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e0107623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e01076086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e0105af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e00d0a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e00d09e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f19d2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19d20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19d20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e00d09d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (1511 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ac60a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555ac60a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555ac60a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80cbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80cbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80cbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80cbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ac603c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555ac603c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555ac6020f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555ac5cd0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555ac5ccfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80cbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80cbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80cbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ac5ccfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (1512 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 8 x 
# | ...
# `---data was truncated (10240/124028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f87ed756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f87ed4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f87ed7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80ed849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80ed8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80ed849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80ed831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f87e6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f87e6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f87e51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f87b01166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f87b00e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80ed832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80ed8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80ed8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f87b00d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (1513 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570bb9c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005570bb9bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005570bb9c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7c621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7c62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7c621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7c6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570bb95823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570bb958086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570bb93cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570bb5ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570bb5ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7c6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7c62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7c62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570bb5ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (1514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616ba50d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005616ba50a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005616ba50dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e39049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e390a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e39049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e39031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616ba4a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005616ba4a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005616ba487f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005616ba137166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005616ba136e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3e39032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e390330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e390330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616ba136d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (1515 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557075d8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557075d87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557075d8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27fb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27fb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27fb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27fb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557075d2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557075d20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557075d04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570759b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570759b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f27fb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27fb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27fb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570759b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (1516 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clastb.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005574b0d2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005574b0d27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005574b0d2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9306249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9306249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9306231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574b0cc023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005574b0cc0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005574b0ca4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005574b0954166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005574b0953e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9306232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93062330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574b0953d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (1517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad4824c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad48249505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad4824ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0166f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0166f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0166f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0166f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad481e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad481e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad481c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad47e76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad47e75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0166f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0166f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0166f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad47e75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (1518 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563afe9d156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563afe9ce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563afe9d1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ec8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ec898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ec8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ec891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563afe96723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563afe967086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563afe94bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563afe5fb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563afe5fae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ec891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ec891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ec891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563afe5fad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (1519 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558c0c6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558c0c65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558c0c68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7223a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7223aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7223a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7223a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558c0bfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005558c0bfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005558c0be2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558c0892166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558c0891e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7223a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7223a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7223a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558c0891d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (1520 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055568614056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055568613d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555686140cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0de0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0de02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0de0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0de0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556860d623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005556860d6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005556860baf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555685d6a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555685d69e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0de0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0de02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0de02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555685d69d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (1521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640aff8256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640aff7f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640aff82cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b78a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b78aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b78a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b78a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640aff1823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640aff18086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640afefcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640afbac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640afbabe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5b78a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b78a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b78a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640afbabd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (1522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cee1c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560cee1c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560cee1c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42fe133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42fe18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42fe133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42fe11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cee15d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560cee15d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560cee141f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560ceddf1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560ceddf0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42fe11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42fe11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42fe11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ceddf0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (1523 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> p
# | ...
# `---data was truncated (10240/24606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055571d01756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055571d014505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055571d017cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb0461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb046725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb0461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb04603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055571cfad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055571cfad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055571cf91f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055571cc41166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055571cc40e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb04604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb046050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb046050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055571cc40d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (1524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055953a84156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055953a83e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055953a841cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ad3305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ad335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ad3305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ad32ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055953a7d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055953a7d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055953a7bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055953a46b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055953a46ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ad32eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ad32ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ad32ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055953a46ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (1525 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a18b4ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a18b4cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a18b4cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe149d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe149d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe149d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe149d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a18b46423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a18b464086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a18b448f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a18b0f8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a18b0f7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe149d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe149d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe149d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a18b0f7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (1526 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b76857b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b768578505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b76857bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b39b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b39b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b39b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b39b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b76851123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b768511086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b7684f5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b7681a5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b7681a4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b39b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b39b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b39b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7681a4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (1527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641cc3c156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005641cc3be505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005641cc3c1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57f7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57f7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57f7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57f7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641cc35723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005641cc357086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005641cc33bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005641cbfeb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005641cbfeae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f57f7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57f7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57f7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641cbfead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (1528 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6f3a9d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c6f3a9a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c6f3a9dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f9af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6f3a3323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c6f3a33086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c6f3a17f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c6f36c7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c6f36c6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6f36c6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (1529 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr =
# | ...
# `---data was truncated (10240/154509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dffa9856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562dffa95505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562dffa98cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21f3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21f3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21f3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21f3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dffa2e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562dffa2e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562dffa12f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562dff6c2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562dff6c1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f21f3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21f3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21f3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dff6c1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (1530 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaa817056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eaa816d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eaa8170cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79b4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79b42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79b4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79b4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa810623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eaa8106086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eaa80eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eaa7d9a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eaa7d99e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f79b4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79b42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79b42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaa7d99d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (1531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eef7ba656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eef7ba3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eef7ba6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd44781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4478725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd44781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd447803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eef7b3c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eef7b3c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eef7b20f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eef77d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eef77cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd447804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4478050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4478050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eef77cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (1532 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ff893756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557ff8934505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557ff8937cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a26649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a26649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a26631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ff88cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557ff88cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557ff88b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557ff8561166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557ff8560e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a26632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a266330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ff8560d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (1533 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9eb81456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a9eb811505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a9eb814cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4b361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4b36725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4b361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4b3603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9eb7aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a9eb7aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a9eb78ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a9eb43e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a9eb43de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4b3604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4b36050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4b36050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9eb43dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (1534 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync
# | ...
# `---data was truncated (10240/183423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642e7a0f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005642e7a0c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005642e7a0fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06c4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06c4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06c4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06c4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642e79a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005642e79a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005642e7989f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005642e7639166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005642e7638e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f06c4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06c4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06c4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642e7638d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (1535 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, ali
# | ...
# `---data was truncated (10240/280217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565dc67956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565dc676505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565dc679cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80b7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80b798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80b7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80b791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565dc60f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565dc60f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565dc5f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565dc2a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565dc2a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80b791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80b791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80b791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565dc2a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (1536 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i1
# | ...
# `---data was truncated (10240/182173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056535e75756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056535e754505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056535e757cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4442905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f444295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4442905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44428ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056535e6ed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056535e6ed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056535e6d1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056535e381166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056535e380e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f44428eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44428ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44428ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056535e380d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (1537 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579e14bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579e14b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579e14bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa332a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa332aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa332a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa332a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579e145223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579e1452086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579e1436f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579e10e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579e10e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa332a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa332a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa332a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579e10e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (1538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ece476756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ece4764505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ece4767cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4714733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f471478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4714733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f471471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ece46fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ece46fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ece46e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ece4391166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ece4390e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f471471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f471471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f471471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ece4390d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (1539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c869a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c869a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c869a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f531c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f531c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f531c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f531c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c8693f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c8693f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c86923f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c865d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c865d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f531c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f531c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f531c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c865d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (1540 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cf462c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cf4629505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cf462ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a9a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a9a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a9a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a9a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cf45c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cf45c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cf45a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cf4256166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cf4255e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0a9a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a9a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a9a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cf4255d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (1541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fcb97956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557fcb976505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557fcb979cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9399e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9399e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9399e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9399e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fcb90f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557fcb90f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557fcb8f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557fcb5a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557fcb5a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9399e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9399e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9399e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fcb5a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (1542 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c75963756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c759634505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c759637cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc1601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc160725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc1601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc16003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7595cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c7595cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c7595b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c759261166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c759260e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc16004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc160050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc160050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c759260d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (1543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558af121056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558af120d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558af1210cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f421de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f421dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f421de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f421de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558af11a623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558af11a6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558af118af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558af0e3a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558af0e39e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f421de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f421de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f421de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558af0e39d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (1544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64 noundef
# | ...
# `---data was truncated (10240/29167) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f0b48956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f0b486505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f0b489cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fd0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fd0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fd0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fd0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f0b41f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f0b41f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f0b403f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f0b0b3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f0b0b2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4fd0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fd0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fd0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f0b0b2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (1545 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c677d0456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c677d01505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c677d04cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc030333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc03038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc030333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc03031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c677c9a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c677c9a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c677c7ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c67792e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c67792de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc03031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc03031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc03031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c67792dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (1546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa2478856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa24785505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa24788cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb18333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb1838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb18333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb1831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa2471e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa2471e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa24702f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa243b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa243b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdb1831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb1831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb1831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa243b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (1547 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633cd12356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633cd120505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633cd123cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5663049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56630a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5663049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5663031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633cd0b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005633cd0b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005633cd09df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005633ccd4d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005633ccd4ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5663032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56630330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56630330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633ccd4cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (1548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> poison, i64 %0)
# |   ret <vscale x 1 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> poison, i64 %0)
# |   ret <vscale x 2 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> poison, i64 %0)
# |   ret <vscale x 4 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> poison, i64 %0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> poison, i64 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> poison, i64 %0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> poison, i64 %0)
# |   ret <vscale x 64 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> poison, i64 %0)
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> poison, i64 %0)
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> poison, i64 %0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> poison, i64 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> poison, i64 %0)
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> poison, i64 %0)
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32> poison, i64 %0)
# |   ret <vscale x 1 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vid_v_u32m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32> poison, i64 %0)
# |   ret <vscale x 2 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vid_v_u32m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32> poison, i64 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vid_v_u32m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32> poison, i64 %0)
# |   ret <vscale x 8 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vid_v_u32m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32> poison, i64 %0)
# |   ret <vscale x 16 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vid_v_u64m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/30303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c781d3856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c781d35505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c781d38cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6160e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6160e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6160e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6160e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c781cce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c781cce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c781cb2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c781962166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c781961e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6160e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6160e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6160e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c781961d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (1549 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de47ed856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de47ed5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de47ed8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1164e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1164ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1164e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1164e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de47e6e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de47e6e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de47e52f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de47b02166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de47b01e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1164e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1164e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1164e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de47b01d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (1550 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4f513756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4f5134505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4f5137cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf0f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf0f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf0f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf0f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4f50cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f4f50cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f4f50b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4f4d61166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4f4d60e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdf0f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf0f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf0f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4f4d60d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (1551 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b632e6356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b632e60505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b632e63cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7331733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f733178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7331733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f733171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b632df923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b632df9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b632dddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b632a8d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b632a8ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f733171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f733171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f733171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b632a8cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (1552 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/94149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055996223856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559962235505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559962238cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8492705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f849275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8492705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84926ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599621ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599621ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005599621b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559961e62166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559961e61e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84926eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84926ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84926ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559961e61d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (1553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567f18cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005567f18c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005567f18cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9dfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9dfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9dfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9dfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567f186123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005567f1861086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005567f1845f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005567f14f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005567f14f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff9dfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9dfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9dfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567f14f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (1554 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1
# | ...
# `---data was truncated (10240/87183) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a0924756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563a09244505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563a09247cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76fb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76fb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76fb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76fb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a091dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563a091dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563a091c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563a08e71166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563a08e70e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f76fb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76fb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76fb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a08e70d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (1555 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056161ffde56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056161ffdb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056161ffdecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b15933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b1598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b15933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b1591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056161ff7423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056161ff74086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056161ff58f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056161fc08166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056161fc07e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b1591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b1591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b1591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056161fc07d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (1556 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f243d6f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f243d6c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f243d6fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f033e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f033e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f033e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f033e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f243d0523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f243d05086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f243ce9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f243999166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f243998e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f033e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f033e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f033e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f243998d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (1557 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564bae7f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005564bae7c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005564bae7fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d6f305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d6f35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d6f305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d6f2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564bae1523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005564bae15086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005564badf9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005564baaa9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005564baaa8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d6f2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d6f2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d6f2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564baaa8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (1558 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %v
# | ...
# `---data was truncated (10240/11349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d08189556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d081892505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d081895cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff75c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff75c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff75c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff75c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d08182b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d08182b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d08180ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d0814bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d0814bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff75c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff75c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff75c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0814bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (1559 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf9650f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bf9650c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bf9650fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7814b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7814b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7814b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7814b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf964a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bf964a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bf96489f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bf96139166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bf96138e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7814b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7814b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7814b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf96138d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (1560 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569ff10456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005569ff101505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005569ff104cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2c1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2c138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2c1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2c131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569ff09a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005569ff09a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005569ff07ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005569fed2e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005569fed2de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa2c131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2c131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2c131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569fed2dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (1561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b17da9e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b17da9b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b17da9ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f283f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f283f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f283f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f283f6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b17da3423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b17da34086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b17da18f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b17d6c8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b17d6c7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f283f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f283f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f283f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b17d6c7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (1562 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3da8cd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a3da8ca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a3da8cdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f653621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65362725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f653621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6536203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3da86323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a3da863086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a3da847f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a3da4f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a3da4f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6536204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65362050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65362050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3da4f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (1563 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055561434a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555614347505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055561434acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0228c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0228ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0228c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0228c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556142e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005556142e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005556142c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555613f74166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555613f73e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0228c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0228c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0228c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555613f73d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (1564 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |  
# | ...
# `---data was truncated (10240/30268) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b58340f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b58340c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b58340fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe65fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe65fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe65fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe65fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5833a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5833a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b583389f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b583039166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b583038e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe65fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe65fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe65fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b583038d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (1565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649644ea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649644e7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649644eacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb620449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb620449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb620431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056496448023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564964480086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564964464f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564964114166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564964113e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb620432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564964113d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (1566 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4b636b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b4b6368505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b4b636bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c1f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c1f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c1f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c1f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4b630123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b4b6301086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b4b62e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b4b5f95166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b4b5f94e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c1f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c1f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c1f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4b5f94d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (1567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586e576b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005586e5768505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005586e576bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c3521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c352725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c3521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c35203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586e570123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005586e5701086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005586e56e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586e5395166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586e5394e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5c35204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c352050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c352050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586e5394d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (1568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556559beb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556559be8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556559bebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7490649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7490649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7490631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556559b8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556559b81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556559b65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556559815166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556559814e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7490632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74906330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556559814d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (1569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056459896156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056459895e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564598961cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5d5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5d538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5d5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5d531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645988f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645988f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645988dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056459858b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056459858ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff5d531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5d531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5d531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056459858ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (1570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8ac60f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8ac60c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8ac60fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20bc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20bc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20bc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20bc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8ac5a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8ac5a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8ac589f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8ac239166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8ac238e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f20bc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20bc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20bc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8ac238d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (1571 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/95437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556be827d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556be827a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556be827dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb10d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556be821323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556be8213086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556be81f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556be7ea7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556be7ea6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feb10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556be7ea6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (1572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c4392a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c43927505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c4392acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4249105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f424915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4249105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42490ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c438c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c438c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c438a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c43554166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c43553e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42490eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42490ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42490ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c43553d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (1573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = e
# | ...
# `---data was truncated (10240/100513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecb246256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ecb245f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ecb2462cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6edb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6edb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6edb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6edb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecb23f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ecb23f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ecb23dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ecb208c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ecb208be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6edb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6edb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6edb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecb208bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (1574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 nou
# | ...
# `---data was truncated (10240/27442) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056123705156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056123704e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561237051cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fa1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fa198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fa1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fa191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561236fe723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561236fe7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561236fcbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561236c7b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561236c7ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6fa191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fa191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fa191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561236c7ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (1575 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e23d6f956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e23d6f6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e23d6f9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1166933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f116698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1166933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f116691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e23d68f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e23d68f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e23d673f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e23d323166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e23d322e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f116691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f116691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f116691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e23d322d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (1576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576eb54456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576eb541505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576eb544cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2620733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f262078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2620733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f262071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576eb4da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576eb4da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576eb4bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576eb16e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576eb16de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f262071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f262071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f262071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576eb16dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (1577 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc0025856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc00255505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc00258cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4af533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4af58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4af533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4af51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc001ee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc001ee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc001d2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cbffe82166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cbffe81e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd4af51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4af51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4af51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbffe81d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (1578 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# | 
# | ...
# `---data was truncated (10240/23255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eb0cff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561eb0cfc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561eb0cffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4d0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4d078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4d0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4d071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eb0c9523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561eb0c95086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561eb0c79f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561eb0929166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561eb0928e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4d071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4d071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4d071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eb0928d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (1579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/101483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613c1c3356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613c1c30505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613c1c33cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa262449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa262449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa262431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613c1bc923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613c1bc9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613c1badf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613c185d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613c185ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa262432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2624330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613c185cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (1580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b8c73a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b8c737505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b8c73acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9088a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9088aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9088a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9088a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b8c6d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b8c6d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b8c6b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b8c364166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b8c363e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9088a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9088a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9088a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b8c363d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (1581 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558978d6356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558978d60505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558978d63cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc82905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc8295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc82905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc828ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558978cf923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558978cf9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558978cddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055897898d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055897898ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbc828eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc828ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc828ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055897898cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (1582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c  -check-prefix=RV32ZBKC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a49c8e256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a49c8df505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a49c8e2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a4481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a448725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a4481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a44803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a49c87823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a49c878086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a49c85cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a49c50c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a49c50be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1a44804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a448050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a448050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a49c50bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (1583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e222b1656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e222b13505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e222b16cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc456905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc45695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc456905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4568ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e222aac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e222aac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e222a90f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e222740166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e22273fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc4568eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4568ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4568ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e22273fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (1584 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = or <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = or <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = or <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = or <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32
# | ...
# `---data was truncated (10240/10897) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b57e5e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555b57e5b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555b57e5ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ffe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ffe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ffe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ffe831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b57df423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555b57df4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555b57dd8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555b57a88166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555b57a87e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ffe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ffe8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ffe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b57a87d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (1585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564d22df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005564d22dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005564d22dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f9aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f9aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f9aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f9aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564d227523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005564d2275086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005564d2259f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005564d1f09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005564d1f08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f9aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f9aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f9aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564d1f08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (1586 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055598766c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555987669505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055598766ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0725b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0725b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0725b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0725b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055598760223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555987602086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559875e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555987296166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555987295e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0725b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0725b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0725b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555987295d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (1587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/14699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566cc83f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005566cc83c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005566cc83fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67bad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67bad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67bad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67bad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566cc7d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005566cc7d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005566cc7b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005566cc469166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005566cc468e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f67bad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67bad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67bad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566cc468d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (1588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578a10d256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578a10cf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578a10d2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f2a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f2a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f2a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f2a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578a106823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578a1068086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578a104cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578a0cfc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578a0cfbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4f2a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f2a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f2a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578a0cfbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (1589 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564029d3f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564029d3c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564029d3fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72b3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72b3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72b3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72b3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564029cd523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564029cd5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564029cb9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564029969166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564029968e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72b3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72b3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72b3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564029968d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (1590 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c786ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c786ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c786aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f160fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f160fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f160fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f160fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c7864423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c78644086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c78628f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c782d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c782d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f160fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f160fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f160fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c782d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (1591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560c00ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005560c00aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005560c00adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f52049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f520a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f52049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f52031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560c004323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005560c0043086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005560c0027f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005560bfcd7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005560bfcd6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f52032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f520330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f520330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560bfcd6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (1592 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f6f02e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f6f02b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f6f02ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aef31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f6efc423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f6efc4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f6efa8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f6ec58166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f6ec57e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3aef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aef31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f6ec57d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (1593 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562666a2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562666a1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562666a20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0720d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0720d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0720d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0720d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626669b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005626669b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056266699af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056266664a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562666649e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0720d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0720d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0720d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562666649d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (1594 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <8 x half>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <4 x float>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055864013956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558640136505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558640139cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6e4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6e4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6e4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6e4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586400cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005586400cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005586400b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055863fd63166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055863fd62e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff6e4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6e4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6e4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055863fd62d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (1595 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llv
# | ...
# `---data was truncated (10240/18669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a479ed456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a479ed1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a479ed4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32b6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32b62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32b6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32b6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a479e6a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a479e6a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a479e4ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a479afe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a479afde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f32b6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32b62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32b62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a479afdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (1596 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1efe7e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e1efe7b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e1efe7ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b47449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b474a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b47449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b47431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1efe1423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e1efe14086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1efdf8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e1efaa8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e1efaa7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b47432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b474330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b474330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1efaa7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (1597 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vf
# | ...
# `---data was truncated (10240/117019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562331a8856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562331a85505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562331a88cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff125249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1252a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff125249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff125231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562331a1e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562331a1e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562331a02f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005623316b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005623316b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff125232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1252330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1252330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623316b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (1598 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af8773056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af8772d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af87730cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18c3d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18c3d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18c3d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18c3ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af876c623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af876c6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af876aaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af8735a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af87359e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f18c3ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18c3cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18c3cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af87359d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (1599 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605ae86656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005605ae863505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005605ae866cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e58049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e580a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e58049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e58031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605ae7fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005605ae7fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005605ae7e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005605ae490166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005605ae48fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e58032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e580330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e580330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605ae48fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (1600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/71947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc3bca756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dc3bca4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dc3bca7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbc3305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbc335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbc3305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbc32ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc3bc3d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dc3bc3d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dc3bc21f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dc3b8d1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dc3b8d0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcbc32eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbc32ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbc32ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc3b8d0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (1601 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557efadc456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557efadc1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557efadc4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe679a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe679aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe679a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe679a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557efad5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557efad5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557efad3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557efa9ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557efa9ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe679a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe679a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe679a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557efa9edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (1602 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565020e5f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565020e5c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565020e5fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3f8105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3f815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3f8105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3f80ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565020df523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565020df5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565020dd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565020a89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565020a88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd3f80eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3f80ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3f80ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565020a88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (1603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613d588456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613d5881505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613d5884cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe121e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe121ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe121e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe121e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613d581a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613d581a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613d57fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613d54ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613d54ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe121e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe121e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe121e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613d54add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (1604 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d39e1756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556d39e14505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556d39e17cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6749933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f674998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6749933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f674991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d39dad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556d39dad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556d39d91f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556d39a41166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556d39a40e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f674991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f674991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f674991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d39a40d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (1605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0c9e5856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0c9e55505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0c9e58cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc6b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc6b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc6b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc6b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0c9dee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c0c9dee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c0c9dd2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c0c9a82166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c0c9a81e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc6b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc6b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc6b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0c9a81d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (1606 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557471da256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557471d9f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557471da2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddfdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddfdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddfdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddfdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557471d3823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557471d38086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557471d1cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005574719cc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005574719cbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fddfdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddfdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddfdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574719cbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (1607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloc
# | ...
# `---data was truncated (10240/27533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647a704e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005647a704b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005647a704ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3692533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f369258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3692533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f369251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647a6fe423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005647a6fe4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005647a6fc8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005647a6c78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005647a6c77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f369251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f369251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f369251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647a6c77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (1608 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed0bc6756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed0bc64505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed0bc67cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1184049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11840a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1184049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1184031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed0bbfd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed0bbfd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed0bbe1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed0b891166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed0b890e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1184032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11840330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11840330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed0b890d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (1609 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645ee0c956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645ee0c6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645ee0c9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4121c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4121ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4121c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4121c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645ee05f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645ee05f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645ee043f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645edcf3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645edcf2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4121c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4121c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4121c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645edcf2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (1610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/34633) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8819cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c8819c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c8819cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5889705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f588975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5889705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58896ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c88196123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c881961086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c881945f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c8815f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c8815f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f58896eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58896ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58896ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8815f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (1611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b59bc556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b59bc2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b59bc5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72b6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72b6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72b6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72b6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b59b5b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b59b5b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b59b3ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b597ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b597eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72b6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72b6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72b6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b597eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (1612 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564098bd256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564098bcf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564098bd2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1471733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f147178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1471733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f147171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564098b6823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564098b68086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564098b4cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640987fc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640987fbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f147171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f147171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f147171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640987fbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (1613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055730517156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055730516e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557305171cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60cd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60cd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60cd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60cd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055730510723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557305107086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005573050ebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557304d9b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557304d9ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f60cd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60cd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60cd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557304d9ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (1614 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d81d6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d81d65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d81d68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82ec533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82ec58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82ec533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82ec51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d81cfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d81cfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d81ce2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d81992166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d81991e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82ec51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82ec51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82ec51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d81991d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (1615 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/26756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055907a80856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055907a805505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055907a808cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc988d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc988d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc988d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc988d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055907a79e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055907a79e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055907a782f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055907a432166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055907a431e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc988d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc988d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc988d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055907a431d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (1616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606d372e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606d372b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606d372ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb910d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb910d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb910d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb910d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606d36c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606d36c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606d36a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606d3358166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606d3357e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb910d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb910d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb910d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606d3357d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (1617 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562847c8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562847c87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562847c8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9539d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9539d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9539d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9539d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562847c2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562847c20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562847c04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005628478b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005628478b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9539d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9539d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9539d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628478b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (1618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0e2c0b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b0e2c08505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b0e2c0bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07ef849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07ef8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07ef849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07ef831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0e2ba123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0e2ba1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0e2b85f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b0e2835166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b0e2834e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f07ef832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07ef8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07ef8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0e2834d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (1619 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %p0.addr = alloca <4 x float>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <4 x float> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <4 x float>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055de48c9656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de48c93505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de48c96cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad02b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad02b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad02b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad02b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de48c2c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de48c2c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de48c10f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de488c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de488bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fad02b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad02b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad02b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de488bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (1620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c17c65a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c17c657505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c17c65acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc50e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc50ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc50e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc50e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c17c5f023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c17c5f0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c17c5d4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c17c284166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c17c283e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc50e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc50e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc50e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c17c283d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (1621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055962ceed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055962ceea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055962ceedcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45ab905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45ab95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45ab905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45ab8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055962ce8323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055962ce83086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055962ce67f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055962cb17166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055962cb16e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f45ab8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45ab8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45ab8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055962cb16d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (1622 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   st
# | ...
# `---data was truncated (10240/110292) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564dbee8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564dbee87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564dbee8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8a3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8a34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8a3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8a3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564dbee2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564dbee20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564dbee04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564dbeab4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564dbeab3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff8a3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8a34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8a34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564dbeab3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (1623 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i6
# | ...
# `---data was truncated (10240/56171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561dc98e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561dc98e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561dc98e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe37d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe37d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe37d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe37d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dc987b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561dc987b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561dc985ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561dc950f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561dc950ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe37d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe37d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe37d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561dc950ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (1624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd09cb956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd09cb6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd09cb9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbac5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbac5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbac5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbac5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd09c4f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd09c4f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd09c33f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd098e3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd098e2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbac5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbac5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbac5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd098e2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (1625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align 8
# |   sto
# | ...
# `---data was truncated (10240/102864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae7ffc256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae7ffbf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae7ffc2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6180d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6180d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6180d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6180d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae7ff5823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae7ff58086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae7ff3cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae7fbec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae7fbebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6180d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6180d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6180d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae7fbebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (1626 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e9770d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563e9770a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563e9770dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f25733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f2578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f25733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f2571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e976a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563e976a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563e97687f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563e97337166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563e97336e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f2571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f2571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f2571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e97336d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (1627 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ee822c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555ee8229505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555ee822ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7f3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7f3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7f3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7f3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ee81c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555ee81c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555ee81a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555ee7e56166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555ee7e55e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe7f3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7f3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7f3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ee7e55d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (1628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599b419256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005599b418f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005599b4192cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc796849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7968a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc796849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc796831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599b412823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599b4128086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005599b410cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005599b3dbc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005599b3dbbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc796832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7968330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7968330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599b3dbbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (1629 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4b446f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c4b446c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c4b446fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8268d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8268d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8268d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8268d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4b440523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c4b4405086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c4b43e9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c4b4099166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c4b4098e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8268d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8268d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8268d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4b4098d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (1630 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cc486856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558cc4865505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558cc4868cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2005533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f200558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2005533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f200551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cc47fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558cc47fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558cc47e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558cc4492166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558cc4491e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f200551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f200551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f200551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cc4491d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (1631 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/20131) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a10612256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a10611f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a106122cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f562a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f562a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f562a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f562a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1060b823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a1060b8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a10609cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a105d4c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a105d4be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f562a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f562a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f562a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a105d4bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (1632 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564065e6a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564065e67505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564065e6acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8a8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8a82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8a8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8a8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564065e0023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564065e00086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564065de4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564065a94166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564065a93e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd8a8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8a82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8a82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564065a93d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (1633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630eea2e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005630eea2b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005630eea2ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff798933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff79898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff798933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff79891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630ee9c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005630ee9c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005630ee9a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005630ee658166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005630ee657e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff79891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff79891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff79891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630ee657d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (1634 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639d257656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639d2573505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639d2576cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4224733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f422478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4224733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f422471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639d250c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639d250c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639d24f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639d21a0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639d219fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f422471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f422471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f422471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639d219fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (1635 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639f600856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639f6005505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639f6008cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26d0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639f5f9e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639f5f9e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639f5f82f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639f5c32166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639f5c31e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f26d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639f5c31d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (1636 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f74de756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560f74de4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560f74de7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1780449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17804a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1780449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1780431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f74d7d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560f74d7d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560f74d61f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560f74a11166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560f74a10e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1780432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17804330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17804330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f74a10d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (1637 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x 
# | ...
# `---data was truncated (10240/11632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055759037f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055759037c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055759037fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbad7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbad718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbad7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbad711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055759031523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557590315086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005575902f9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055758ffa9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055758ffa8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbad711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbad711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbad711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055758ffa8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (1638 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629923ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005629923ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005629923edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5f3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5f3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5f3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5f3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056299238323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562992383086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562992367f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562992017166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562992016e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5f3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5f3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5f3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562992016d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (1639 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649e375356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649e3750505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649e3753cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8251533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f825158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8251533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f825151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649e36e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005649e36e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005649e36cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005649e337d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005649e337ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f825151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f825151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f825151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649e337cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (1640 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055825513356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558255130505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558255133cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b42d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b42d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b42d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b42d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582550c923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582550c9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582550adf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558254d5d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558254d5ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5b42d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b42d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b42d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558254d5cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (1641 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558eef37656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558eef373505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558eef376cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6108e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6108e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6108e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6108e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eef30c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558eef30c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558eef2f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558eeefa0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558eeef9fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6108e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6108e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6108e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558eeef9fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (1642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555af356c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555af3569505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555af356ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6542133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f654218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6542133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f654211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555af350223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555af3502086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555af34e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555af3196166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555af3195e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f654211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f654211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f654211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555af3195d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (1643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e7f0c456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e7f0c1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e7f0c4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9549b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9549b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9549b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9549b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e7f05a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e7f05a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e7f03ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e7ecee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e7ecede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9549b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9549b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9549b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e7ecedd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (1644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b2e60556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559b2e602505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559b2e605cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13c5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13c578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13c5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13c571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b2e59b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559b2e59b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559b2e57ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559b2e22f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559b2e22ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13c571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13c571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13c571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b2e22ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (1645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7080e256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a7080df505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a7080e2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b97133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b9718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b97133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b9711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a70807823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a708078086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a70805cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a707d0c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a707d0be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1b9711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b9711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b9711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a707d0bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (1646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056315f1fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056315f1fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056315f1fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc555733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc55578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc555733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc55571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056315f19323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056315f193086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056315f177f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056315ee27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056315ee26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc55571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc55571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc55571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056315ee26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (1647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056436217256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056436216f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564362172cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8adb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8adb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8adb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8adaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056436210823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564362108086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005643620ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564361d9c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564361d9be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc8adaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8adaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8adaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564361d9bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (1648 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a51846756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a518464505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a518467cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9305c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9305ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9305c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9305c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5183fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a5183fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a5183e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a518091166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a518090e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9305c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9305c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9305c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a518090d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (1649 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_l
# | ...
# `---data was truncated (10240/13585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615ee52156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615ee51e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615ee521cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a41133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a4118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a41133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a4111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615ee4b723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615ee4b7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615ee49bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615ee14b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615ee14ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a4111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a4111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a4111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615ee14ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (1650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 
# | ...
# `---data was truncated (10240/27063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab8049c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab80499505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab8049ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c97933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c9798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c97933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c9791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab8043223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab80432086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab80416f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab800c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab800c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c9791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c9791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c9791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab800c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (1651 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055868318956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558683186505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558683189cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc62f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc62f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc62f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc62f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055868311f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055868311f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558683103f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558682db3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558682db2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc62f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc62f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc62f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558682db2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (1652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.add
# | ...
# `---data was truncated (10240/86739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056386a59856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056386a595505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056386a598cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3b8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3b818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3b8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3b811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056386a52e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056386a52e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056386a512f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056386a1c2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056386a1c1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3b811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3b811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3b811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056386a1c1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (1653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3d623a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c3d6237505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c3d623acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f283dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f283dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f283dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f283dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3d61d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3d61d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3d61b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c3d5e64166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c3d5e63e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f283dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f283dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f283dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3d5e63d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (1654 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645a525b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645a5258505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645a525bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe24f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe24f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe24f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe24f0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645a51f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645a51f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645a51d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645a4e85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645a4e84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe24f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe24f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe24f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645a4e84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (1655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a7975056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a7974d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a79750cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05a9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05a9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05a9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05a9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a796e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a796e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a796caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a7937a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a79379e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f05a9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05a9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05a9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a79379d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (1656 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1
# | ...
# `---data was truncated (10240/26476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055962de8656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055962de83505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055962de86cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59a2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59a2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59a2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59a2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055962de1c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055962de1c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055962de00f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055962dab0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055962daafe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f59a2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59a2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59a2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055962daafd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (1657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056420a35956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056420a356505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056420a359cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb1c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb1c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb1c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb1c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056420a2ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056420a2ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056420a2d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564209f83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564209f82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb1c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb1c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb1c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564209f82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (1658 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwi
# | ...
# `---data was truncated (10240/235604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffa29e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ffa29e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ffa29e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f394941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39494725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f394941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3949403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffa297923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ffa2979086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ffa295df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ffa260d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ffa260ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3949404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39494050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39494050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffa260cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (1659 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055766084d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055766084a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055766084dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1388a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1388aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1388a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1388a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576607e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576607e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576607c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557660477166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557660476e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1388a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1388a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1388a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557660476d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (1660 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/110284) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ecc41756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ecc414505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ecc417cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc14ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ecc3ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ecc3ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ecc391f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ecc041166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ecc040e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007facc14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc14ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ecc040d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (1661 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/77054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055742ac0956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055742ac06505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055742ac09cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67d7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67d718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67d7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67d711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055742ab9f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055742ab9f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055742ab83f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055742a833166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055742a832e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f67d711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67d711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67d711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055742a832d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (1662 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056063521b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560635218505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056063521bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd169249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1692a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd169249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd169231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606351b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606351b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560635195f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560634e45166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560634e44e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd169232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1692330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1692330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560634e44d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (1663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056384b70e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056384b70b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056384b70ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fd2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fd218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fd2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fd211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056384b6a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056384b6a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056384b688f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056384b338166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056384b337e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6fd211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fd211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fd211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056384b337d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (1664 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/12433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c3bd2e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c3bd2b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c3bd2ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda0ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda0cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda0ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda0ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c3bcc423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c3bcc4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c3bca8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c3b958166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c3b957e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda0ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda0ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda0ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c3b957d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (1665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale 
# | ...
# `---data was truncated (10240/215486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc2f2d156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc2f2ce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc2f2d1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f41c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f41ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f41c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f41c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc2f26723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc2f267086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc2f24bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc2eefb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc2eefae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f41c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f41c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f41c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc2eefad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (1666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056405c9e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056405c9e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056405c9e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2808b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2808b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2808b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2808b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056405c97b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056405c97b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056405c95ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056405c60f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056405c60ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2808b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2808b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2808b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056405c60ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (1667 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644bb24056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005644bb23d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005644bb240cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe941849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9418a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe941849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe941831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644bb1d623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005644bb1d6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005644bb1baf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005644bae6a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005644bae69e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe941832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9418330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9418330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644bae69d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (1668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c735ebd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c735eba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c735ebdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ea8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ea898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ea8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ea891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c735e5323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c735e53086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c735e37f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c735ae7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c735ae6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3ea891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ea891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ea891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c735ae6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (1669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2
# | ...
# `---data was truncated (10240/94673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595456b956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005595456b6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005595456b9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee0c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee0c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee0c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee0c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055954564f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055954564f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559545633f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005595452e3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005595452e2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fee0c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee0c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee0c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595452e2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (1670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056391257856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563912575505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563912578cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7d6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7d6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7d6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7d6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056391250e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056391250e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639124f2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639121a2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639121a1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7d6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7d6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7d6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639121a1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (1671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/135337) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645faad656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645faad3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645faad6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ed4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ed4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ed4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ed4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645faa6c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645faa6c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645faa50f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645fa700166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645fa6ffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ed4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ed4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ed4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645fa6ffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (1672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620d257b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005620d2578505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005620d257bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f102b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f102b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f102b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f102b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620d251123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005620d2511086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005620d24f5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005620d21a5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005620d21a4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f102b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f102b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f102b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620d21a4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (1673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/67006) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055676848d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055676848a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055676848dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9c3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9c3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9c3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9c3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055676842323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556768423086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556768407f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005567680b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005567680b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff9c3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9c3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9c3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567680b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (1674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i6
# | ...
# `---data was truncated (10240/35605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe54dbb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fe54db8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fe54dbbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd852933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd85298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd852933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd85291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe54d5123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fe54d51086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fe54d35f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fe549e5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fe549e4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd85291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd85291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd85291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe549e4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (1675 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee421f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee421f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee421f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e89249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e892a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e89249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e89231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee4218d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee4218d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee42171f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee41e21166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee41e20e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e89232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e892330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e892330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee41e20d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (1676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/148020) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6af9fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e6af9fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e6af9fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2afe61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2afe6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2afe61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2afe603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6af99323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e6af993086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e6af977f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e6af627166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e6af626e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2afe604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2afe6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2afe6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6af626d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (1677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9f3d7856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b9f3d75505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b9f3d78cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff73449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff73449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff73431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9f3d0e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b9f3d0e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b9f3cf2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9f39a2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9f39a1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff73432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff734330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9f39a1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (1678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/210435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055772e27356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055772e270505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055772e273cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8df3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8df38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8df3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8df3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772e20923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055772e209086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055772e1edf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055772de9d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055772de9ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8df3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8df38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8df38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055772de9cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (1679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654e970256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005654e96ff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005654e9702cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa50f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa50f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa50f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa50f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654e969823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005654e9698086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005654e967cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005654e932c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005654e932be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa50f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa50f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa50f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654e932bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (1680 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b9d5ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b9d5eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b9d5eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe22a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe22aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe22a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe22a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b9d58423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b9d584086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b9d568f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b9d218166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b9d217e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe22a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe22a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe22a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b9d217d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (1681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605135dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005605135da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005605135ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb4ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb4cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb4ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb4ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056051357323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560513573086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560513557f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560513207166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560513206e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb4ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb4ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb4ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560513206d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (1682 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558279bb856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558279bb5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558279bb8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf84333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf8438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf84333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf8431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558279b4e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558279b4e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558279b32f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582797e2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582797e1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbf8431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf8431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf8431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582797e1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (1683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579bd23356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579bd230505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579bd233cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa12a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa12a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa12a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa12a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579bd1c923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579bd1c9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579bd1adf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579bce5d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579bce5ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa12a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa12a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa12a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579bce5cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (1684 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a90bef456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a90bef1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a90bef4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7195a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7195aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7195a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7195a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a90be8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a90be8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a90be6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a90bb1e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a90bb1de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7195a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7195a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7195a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a90bb1dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (1685 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055795b16b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055795b168505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055795b16bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c1e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c1e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c1e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c1e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055795b10123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055795b101086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055795b0e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055795ad95166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055795ad94e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8c1e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c1e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c1e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055795ad94d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (1686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f273c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f273c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f273c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f7d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f7d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f7d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f7d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f2735d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f2735d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f27341f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f26ff1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f26ff0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f7d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f7d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f7d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f26ff0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (1687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccae7ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccae7a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccae7accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d21449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d214a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d21449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d21431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccae74223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccae742086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccae726f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ccae3d6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ccae3d5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6d21432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d214330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d214330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccae3d5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (1688 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp ule <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp sle <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp ule <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639c215956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639c2156505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639c2159cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e28d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e28d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e28d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e28ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639c20ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639c20ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639c20d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639c1d83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639c1d82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e28ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e28cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e28cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639c1d82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (1689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056206250456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562062501505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562062504cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca07533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca0758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca07533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca0751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056206249a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056206249a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056206247ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056206212e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056206212de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca0751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca0751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca0751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056206212dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (1690 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560748aa356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560748aa0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560748aa3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec17849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec17849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec17831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560748a3923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560748a39086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560748a1df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607486cd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607486cce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec17832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec178330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607486ccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (1691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dc903656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562dc9033505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562dc9036cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a38f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a38f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a38f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a38f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dc8fcc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562dc8fcc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562dc8fb0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562dc8c60166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562dc8c5fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7a38f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a38f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a38f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dc8c5fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (1692 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b53f71f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b53f71c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b53f71fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b3c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b3c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b3c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b3c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b53f6b523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b53f6b5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b53f699f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b53f349166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b53f348e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3b3c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b3c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b3c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b53f348d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (1693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/170497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564674a6a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564674a67505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564674a6acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc110d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc110d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc110d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc110d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564674a0023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564674a00086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646749e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564674694166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564674693e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc110d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc110d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc110d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564674693d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (1694 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646c761c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646c7619505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646c761ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4654e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4654e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4654e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4654e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646c75b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646c75b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646c7596f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646c7246166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646c7245e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4654e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4654e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4654e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646c7245d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (1695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625e9ee956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625e9ee6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625e9ee9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd92933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd9298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd92933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd9291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625e9e7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005625e9e7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005625e9e63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005625e9b13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005625e9b12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd9291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd9291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd9291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625e9b12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (1696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bdda3d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bdda3a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bdda3dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f0dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f0dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f0dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f0dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bdd9d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bdd9d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bdd9b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bdd667166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bdd666e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f0dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f0dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f0dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bdd666d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (1697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3aa1d056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a3aa1cd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a3aa1d0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bdb81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bdb8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bdb81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bdb803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3aa16623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a3aa166086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a3aa14af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a3a9dfa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a3a9df9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1bdb804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bdb8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bdb8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3a9df9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (1698 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aaf4d2f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aaf4d2c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aaf4d2fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aaf4cc523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aaf4cc5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aaf4ca9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aaf4959166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aaf4958e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42e211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aaf4958d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (1699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/78328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589a9a3556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589a9a32505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589a9a35cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bb8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bb80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bb8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bb8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589a99cb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589a99cb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589a99aff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589a965f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589a965ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4bb8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bb80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bb80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589a965ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (1700 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055815b7f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055815b7f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055815b7f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a5d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a5d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a5d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a5d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055815b78923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055815b789086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055815b76df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055815b41d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055815b41ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a5d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a5d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a5d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055815b41cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (1701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056554a36e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056554a36b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056554a36ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86e4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86e48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86e4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86e4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056554a30423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056554a304086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056554a2e8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565549f98166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565549f97e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f86e4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86e48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86e48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565549f97d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (1702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6e89b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6e89b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6e89b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe03d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe03d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe03d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe03d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6e894a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6e894a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6e892ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6e85de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6e85dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe03d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe03d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe03d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6e85ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (1703 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e7b14556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e7b142505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e7b145cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1386249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13862a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1386249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1386231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e7b0db23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e7b0db086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e7b0bff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e7ad6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e7ad6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1386232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13862330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13862330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e7ad6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (1704 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cc694356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cc6940505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cc6943cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a8e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a8e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a8e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a8e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cc68d923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cc68d9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cc68bdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cc656d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cc656ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a8e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a8e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a8e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cc656cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (1705 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d334d3556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d334d32505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d334d35cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17e2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17e26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17e2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17e2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d334ccb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d334ccb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d334caff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d33495f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d33495ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f17e2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17e26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17e26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d33495ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (1706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align
# | ...
# `---data was truncated (10240/18311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfc1ea156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bfc1e9e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bfc1ea1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0feb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0feb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0feb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0feb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfc1e3723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bfc1e37086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bfc1e1bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bfc1acb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bfc1acae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb0feb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0feb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0feb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfc1acad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (1707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b4206456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b42061505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b42064cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3a2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3a2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3a2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3a2e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b41ffa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b41ffa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b41fdef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b41c8e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b41c8de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd3a2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3a2e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3a2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b41c8dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (1708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b33590f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b33590c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b33590fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc38c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc38c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc38c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc38c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3358a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b3358a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b335889f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b335539166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b335538e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc38c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc38c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc38c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b335538d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (1709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614e55f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005614e55f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005614e55f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd093049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0930a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd093049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd093031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614e558d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005614e558d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005614e5571f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005614e5221166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005614e5220e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd093032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0930330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0930330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614e5220d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (1710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056432b44456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056432b441505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056432b444cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1617333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f161738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1617333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f161731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056432b3da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056432b3da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056432b3bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056432b06e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056432b06de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f161731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f161731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f161731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056432b06dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (1711 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %
# | ...
# `---data was truncated (10240/20326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e13004656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e130043505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e130046cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a94b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a94b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a94b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a94aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e12ffdc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e12ffdc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e12ffc0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e12fc70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e12fc6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a94aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a94aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a94aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e12fc6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (1712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b186d056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b186cd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b186d0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cf7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cf738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cf7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cf731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b1866623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b18666086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b1864af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b182fa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b182f9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3cf731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cf731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cf731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b182f9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (1713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3ce75256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e3ce74f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e3ce752cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1305333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f130538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1305333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f130531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3ce6e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e3ce6e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3ce6ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e3ce37c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e3ce37be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f130531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f130531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f130531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3ce37bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (1714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c  -check-prefix=RV32ZBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @orc_b_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @ctz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cpop_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctpop.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.orc.b.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctpop.i32(i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643240bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005643240b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005643240bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f82649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f82649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f82631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056432405223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564324052086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564324036f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564323ce6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564323ce5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f82632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f826330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564323ce5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (1715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636fcbca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636fcbc7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636fcbcacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6308e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6308ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6308e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6308e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636fcb6023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005636fcb60086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005636fcb44f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005636fc7f4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005636fc7f3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6308e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6308e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6308e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636fc7f3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (1716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2c716d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2c716a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2c716dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa724d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa724d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa724d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa724d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2c710323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2c7103086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2c70e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2c6d97166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2c6d96e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa724d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa724d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa724d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2c6d96d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (1717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b23c5b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b23c58505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b23c5bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5534d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5534d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5534d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5534d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b23bf123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b23bf1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b23bd5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b23885166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b23884e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5534d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5534d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5534d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b23884d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (1718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/64349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c78484756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c784844505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c784847cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ce0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ce0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ce0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ce0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7847dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c7847dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c7847c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c784471166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c784470e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ce0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ce0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ce0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c784470d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (1719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0e9a2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f0e9a1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f0e9a20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabe3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabe318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabe3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabe311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0e99b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0e99b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0e999af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f0e964a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f0e9649e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fabe311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabe311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabe311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0e9649d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (1720 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ab258556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557ab2582505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557ab2585cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86af533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86af58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86af533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86af51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ab251b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557ab251b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557ab24fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557ab21af166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557ab21aee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f86af51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86af51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86af51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ab21aed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (1721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055602136056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055602135d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556021360cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f773701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77370725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f773701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7737003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560212f623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005560212f6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005560212daf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556020f8a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556020f89e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7737004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77370050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77370050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556020f89d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (1722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573f9c8e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005573f9c8b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005573f9c8ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f695a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f695a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f695a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f695a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573f9c2423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005573f9c24086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005573f9c08f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005573f98b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005573f98b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f695a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f695a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f695a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573f98b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (1723 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613fdb1c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613fdb19505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613fdb1ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4921e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4921e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4921e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4921e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613fdab223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613fdab2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613fda96f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613fd746166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613fd745e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4921e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4921e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4921e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613fd745d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (1724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 nou
# | ...
# `---data was truncated (10240/78890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b13e9dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b13e9da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b13e9ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb68881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6888725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb68881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb688803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b13e97323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b13e973086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b13e957f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b13e607166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b13e606e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb688804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6888050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6888050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b13e606d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (1725 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3117d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e3117d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e3117d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc7d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc7d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc7d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc7d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e31176d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e31176d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e311751f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e311401166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e311400e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc7d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc7d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc7d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e311400d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm64_vcopy.c (1726 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_336 = alloca <16 x i8>, align 16
# |   %__s0_336 = alloca <16 x i8>, align 16
# |   %__s2_336 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_336, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_336, align 16
# |   %2 = load <16 x i8>, ptr %__s2_336, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_336, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_336, align 16
# |   %13 = load <16 x i8>, ptr %__ret_336, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_328 = alloca <16 x i8>, align 16
# |   %__s0_328 = alloca <16 x i8>, align 16
# |   %__s2_328 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_328, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_328, align 16
# |   %2 = load <16 x i8>, ptr %__s2_328, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_328, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_328, align 16
# |   %13 = load <16 x i8>, ptr %__ret_328, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_346 = alloca <8 x i16>, align 16
# |   %__s0_346 = alloca <8 x i16>, align 16
# |   %__s2_346 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_346, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_346, align 16
# |   %2 = load <8 x i16>, ptr %__s2_346, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_346, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_346, align 16
# |   %13 = load <8 x i16>, ptr %__ret_346, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_334 = alloca <8 x i16>, align 16
# |   %__s0_334 = alloca <8 x i16>, align 16
# |   %__s2_334 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_334, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_334, align 16
# |   %2 = load <8 x i16>, ptr %__s2_334, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_334, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_334, align 16
# |   %13 = load <8 x i16>, ptr %__ret_334, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <4 x i32>, align 16
# |   %a2.addr = alloca <4 x i32>, align 16
# |   %__ret_340 = alloca <4 x i32>, align 16
# |   %__s0_340 = alloca <4 x i32>, align 16
# |   %__s2_340 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca i32, align 4
# |   %__ret1 = alloca i32, align 4
# |   %__s02 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp3 = alloca <4 x i32>, align 16
# |   %tmp4 = alloca <4 x i32>, align 16
# |   %tmp5 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a1, ptr %a1.addr, align 16
# |   store <4 x i32> %a2, ptr %a2.addr, align 16
# |   %0 = load <4 x i32>, ptr %a1.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_340, align 16
# |   %1 = load <4 x i32>, ptr %a2.addr, align 16
# |   store <4 x i32> %1, ptr %__s2_340, align 16
# |   %2 = load <4 x i32>, ptr %__s2_340, align 16
# |   store <4 x i32> %2, ptr %__s02, align 16
# |   %3 = load <4 x i32>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <4 x i32> %3, i32 3
# |   store i32 %vgetq_lane, ptr %ref.tmp, align 4
# |   %4 = load i32, ptr %ref.tmp, align 4
# |   store i32 %4, ptr %__ret1, align 4
# |   %5 = load i32, ptr %__ret1, align 4
# |   store i32 %5, ptr %tmp, align 4
# |   %6 = load i32, ptr %tmp, align 4
# |   store i32 %6, ptr %__s0, align 4
# |   %7 = load <4 x i32>
# | ...
# `---data was truncated (10240/22011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef8351a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ef83517505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ef8351acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4e941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4e94725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4e941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4e9403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef834b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ef834b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ef83494f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ef83144166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ef83143e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff4e9404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4e94050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4e94050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef83143d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (1727 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055936b10556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055936b102505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055936b105cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc40ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc40ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc40ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc40ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055936b09b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055936b09b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055936b07ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055936ad2f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055936ad2ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc40ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc40ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc40ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055936ad2ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (1728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/26984) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055875497656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558754973505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558754976cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc85821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8582725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc85821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc858203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055875490c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055875490c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005587548f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005587545a0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055875459fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc858204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8582050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8582050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055875459fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (1729 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b84076756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b840764505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b840767cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f231c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f231c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f231c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f231c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8406fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b8406fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b8406e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b840391166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b840390e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f231c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f231c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f231c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b840390d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (1730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa252a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa252a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa252a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa99b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa99b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa99b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa99b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa2523a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa2523a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa2521ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa24ece166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa24ecde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa99b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa99b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa99b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa24ecdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (1731 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c56d1956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c56d16505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c56d19cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ed6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ed62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ed6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ed6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c56caf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c56caf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c56c93f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c56943166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c56942e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ed6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ed62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ed62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c56942d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (1732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaa
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c5951956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c59516505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c59519cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83f8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83f8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83f8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83f8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c594af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c594af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c59493f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c59143166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c59142e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f83f8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83f8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83f8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c59142d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (1733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/26710) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555627c2256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555627c1f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555627c22cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac36d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac36d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac36d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac36d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555627bb823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555627bb8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555627b9cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055562784c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055562784be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac36d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac36d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac36d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055562784bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (1734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c65df3856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c65df35505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c65df38cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f544a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f544a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f544a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f544a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c65dece23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c65dece086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c65deb2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c65db62166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c65db61e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f544a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f544a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f544a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c65db61d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (1735 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b63fcd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b63fca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b63fcdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd992b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd992b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd992b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd992b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b63f6323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b63f63086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b63f47f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b63bf7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b63bf6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd992b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd992b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd992b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b63bf6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (1736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565ec38556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565ec382505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565ec385cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fe8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fe80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fe8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fe8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565ec31b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565ec31b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565ec2fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565ebfaf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565ebfaee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3fe8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fe80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fe80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565ebfaed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (1737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eecf5356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564eecf50505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564eecf53cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dda133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dda18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dda133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dda11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eecee923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564eecee9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564eececdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564eecb7d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564eecb7ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3dda11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dda11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dda11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eecb7cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (1738 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f1654956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f16546505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f16549cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0792049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0792049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0792031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f164df23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f164df086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f164c3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f16173166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f16172e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0792032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07920330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f16172d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (1739 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b9528b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b95288505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b9528bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32ab733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32ab78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32ab733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32ab71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b9522123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b95221086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b95205f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b94eb5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b94eb4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f32ab71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32ab71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32ab71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b94eb4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (1740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561c3ae156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561c3ade505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561c3ae1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cf1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cf1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cf1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cf1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561c3a7723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561c3a77086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561c3a5bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005561c370b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005561c370ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4cf1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cf1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cf1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561c370ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (1741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055defbb0a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055defbb07505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055defbb0acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0999049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09990a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0999049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0999031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055defbaa023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055defbaa0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055defba84f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055defb734166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055defb733e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0999032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09990330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09990330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055defb733d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (1742 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561aa572256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561aa571f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561aa5722cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f899f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f899f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f899f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f899f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aa56b823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561aa56b8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561aa569cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561aa534c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561aa534be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f899f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f899f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f899f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aa534bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (1743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561710d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561710d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561710d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4063e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4063ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4063e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4063e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055617106b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055617106b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055617104ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556170cff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556170cfee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4063e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4063e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4063e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556170cfed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (1744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4
# | ...
# `---data was truncated (10240/17583) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055658253156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055658252e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556582531cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff044249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0442a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff044249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff044231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565824c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565824c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565824abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055658215b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055658215ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff044232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0442330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0442330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055658215ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (1745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, pt
# | ...
# `---data was truncated (10240/32402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dc019756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556dc0194505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556dc0197cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17b7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17b7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17b7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17b7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dc012d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556dc012d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556dc0111f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556dbfdc1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556dbfdc0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f17b7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17b7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17b7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dbfdc0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (1746 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d69d04556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d69d042505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d69d045cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa714c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa714ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa714c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa714c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d69cfdb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d69cfdb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d69cfbff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d69cc6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d69cc6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa714c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa714c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa714c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d69cc6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (1747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f14986d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f14986a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f14986dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cdee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cdeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cdee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cdee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f14980323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f149803086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f1497e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f149497166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f149496e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6cdee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cdee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cdee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f149496d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (1748 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056263b6d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056263b6d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056263b6d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f1d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f1d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f1d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f1d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056263b66b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056263b66b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056263b64ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056263b2ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056263b2fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4f1d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f1d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f1d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056263b2fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (1749 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/68065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e465b7b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e465b78505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e465b7bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3424c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3424ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3424c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3424c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e465b1123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e465b11086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e465af5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4657a5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4657a4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3424c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3424c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3424c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4657a4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (1750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = ca
# | ...
# `---data was truncated (10240/67474) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654e549b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005654e5498505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005654e549bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f648ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f648ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f648ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f648ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654e543123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005654e5431086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005654e5415f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005654e50c5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005654e50c4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f648ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f648ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f648ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654e50c4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (1751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc95d8456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc95d81505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc95d84cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d4b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d4b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d4b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d4b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc95d1a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc95d1a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc95cfef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc959ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc959ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7d4b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d4b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d4b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc959add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (1752 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf042a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bf0429f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bf042a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6074533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f607458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6074533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f607451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf0423823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bf04238086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bf0421cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bf03ecc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bf03ecbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f607451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f607451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f607451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf03ecbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (1753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af9345256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af9344f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af93452cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9db4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9db498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9db4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9db491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af933e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af933e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af933ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af9307c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af9307be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9db491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9db491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9db491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af9307bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (1754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>
# | ...
# `---data was truncated (10240/43625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556373e5d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556373e5a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556373e5dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7814049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78140a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7814049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7814031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556373df323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556373df3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556373dd7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556373a87166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556373a86e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7814032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78140330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78140330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556373a86d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (1755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0b9d656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b0b9d3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b0b9d6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0061533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f006158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0061533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f006151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b0b96c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b0b96c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b0b950f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b0b600166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b0b5ffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f006151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f006151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f006151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b0b5ffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (1756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056016ec1d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056016ec1a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056016ec1dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffad8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffad84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffad8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffad8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056016ebb323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056016ebb3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056016eb97f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056016e847166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056016e846e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffad8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffad84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffad84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056016e846d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (1757 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, pt
# | ...
# `---data was truncated (10240/174721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649329a856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649329a5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649329a8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b6c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b6c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b6c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b6c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056493293e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056493293e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564932922f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005649325d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005649325d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0b6c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b6c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b6c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649325d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (1758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i
# | ...
# `---data was truncated (10240/40929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bfaa7956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bfaa76505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bfaa79cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7800e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7800ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7800e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7800e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bfaa0f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bfaa0f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bfa9f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bfa6a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bfa6a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7800e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7800e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7800e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bfa6a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (1759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2_m(<vscale x 2 x i1> %mask,
# | ...
# `---data was truncated (10240/13544) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c2987456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561c29871505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561c29874cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f74b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f74b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f74b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f74b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c2980a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561c2980a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561c297eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561c2949e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561c2949de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f74b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f74b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f74b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c2949dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (1760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566d079a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005566d0797505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005566d079acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8617533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f861758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8617533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f861751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566d073023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005566d0730086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005566d0714f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005566d03c4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005566d03c3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f861751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f861751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f861751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566d03c3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (1761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599a63cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005599a63c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005599a63cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc656c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc656ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc656c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc656c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599a636223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599a6362086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005599a6346f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005599a5ff6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005599a5ff5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc656c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc656c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc656c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599a5ff5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (1762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055638019456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556380191505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556380194cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb850c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb850ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb850c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb850c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055638012a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055638012a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055638010ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055637fdbe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055637fdbde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb850c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb850c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb850c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055637fdbdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (1763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8b2dbb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e8b2db8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e8b2dbbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb70d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb70d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb70d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb70d403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8b2d5123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e8b2d51086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8b2d35f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e8b29e5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e8b29e4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb70d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb70d4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb70d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8b29e4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (1764 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639c3df356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639c3df0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639c3df3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f04d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f04d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f04d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f04d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639c3d8923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639c3d89086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639c3d6df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639c3a1d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639c3a1ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f04d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f04d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f04d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639c3a1cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (1765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c0f2e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556c0f2e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556c0f2e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b3d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b3d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b3d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b3d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c0f27923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556c0f279086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556c0f25df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556c0ef0d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556c0ef0ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b3d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b3d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b3d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c0ef0cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (1766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/65723) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c05eba556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c05eba2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c05eba5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5843533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f584358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5843533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f584351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c05eb3b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c05eb3b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c05eb1ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c05e7cf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c05e7cee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f584351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f584351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f584351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c05e7ced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (1767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560196dd756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560196dd4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560196dd7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35dda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560196d6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560196d6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560196d51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560196a01166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560196a00e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f35dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35dda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560196a00d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (1768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ae98c456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ae98c1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ae98c4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fd6d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fd6d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fd6d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fd6ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ae985a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ae985a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ae983ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ae94ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ae94ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9fd6ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fd6cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fd6cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ae94edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (1769 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/153905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055950000656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559500003505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559500006cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7485133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f748518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7485133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f748511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594fff9c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594fff9c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005594fff80f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005594ffc30166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005594ffc2fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f748511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f748511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f748511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594ffc2fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (1770 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/88444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df423c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055df423c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055df423c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa42a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa42a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa42a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa42a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df4235b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055df4235b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055df4233ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055df41fef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055df41feee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa42a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa42a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa42a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df41feed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (1771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0
# | ...
# `---data was truncated (10240/29136) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cc15c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cc15c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cc15c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e52e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e52ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e52e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e52e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cc155b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cc155b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cc153ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cc11ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cc11eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e52e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e52e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e52e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cc11eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (1772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056243802056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056243801d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562438020cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4de533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4de58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4de533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4de51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562437fb623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562437fb6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562437f9af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562437c4a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562437c49e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb4de51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4de51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4de51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562437c49d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (1773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a026b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a026b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a026b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe1e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe1e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe1e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe1e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a0264a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a0264a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a0262ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a022de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a022dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe1e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe1e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe1e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a022ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (1774 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af3e32856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af3e325505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af3e328cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab3f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab3f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab3f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab3f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af3e2be23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af3e2be086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af3e2a2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af3df52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af3df51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab3f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab3f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab3f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af3df51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (1775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6ef49456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a6ef491505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a6ef494cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92d5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92d56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92d5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92d5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6ef42a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a6ef42a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a6ef40ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a6ef0be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a6ef0bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f92d5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92d56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92d56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6ef0bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (1776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652ec27e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652ec27b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652ec27ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47d2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47d238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47d2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47d231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652ec21423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005652ec214086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005652ec1f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005652ebea8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005652ebea7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47d231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47d231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47d231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652ebea7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (1777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055656411056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055656410d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556564110cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1af0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1af0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1af0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1af0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565640a623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565640a6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055656408af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556563d3a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556563d39e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1af0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1af0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1af0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556563d39d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (1778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/24990) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056510355356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565103550505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565103553cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9f8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9f898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9f8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9f891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651034e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651034e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651034cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056510317d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056510317ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe9f891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9f891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9f891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056510317cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (1779 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16
# | ...
# `---data was truncated (10240/338692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568eb18256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005568eb17f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005568eb182cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72bd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568eb11823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005568eb118086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005568eb0fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005568eadac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005568eadabe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568eadabd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (1780 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563c560856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563c5605505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563c5608cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3d621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3d62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3d621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3d6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563c559e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005563c559e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005563c5582f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005563c5232166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005563c5231e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3d6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3d62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3d62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563c5231d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (1781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8
# | ...
# `---data was truncated (10240/215036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a287b156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557a287ae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557a287b1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fee105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fee15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fee105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fee0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a2874723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557a28747086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557a2872bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557a283db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557a283dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0fee0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fee0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fee0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a283dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (1782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056447bf4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056447bf43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056447bf46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8003933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f800398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8003933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f800391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056447bedc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056447bedc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056447bec0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056447bb70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056447bb6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f800391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f800391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f800391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056447bb6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (1783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align
# | ...
# `---data was truncated (10240/102872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cf382356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cf3820505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cf3823cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5befb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5befb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5befb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5befb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cf37b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cf37b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cf379df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cf344d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cf344ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5befb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5befb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5befb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cf344cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (1784 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0cba9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d0cba8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d0cba90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bdde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bdde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bdde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bdde03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0cba2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d0cba26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d0cba0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d0cb6ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d0cb6b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3bdde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bdde050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bdde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0cb6b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (1785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.
# | ...
# `---data was truncated (10240/18641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad38d9456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad38d91505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad38d94cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f204a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f204a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f204a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f204a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad38d2a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad38d2a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad38d0ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad389be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad389bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f204a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f204a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f204a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad389bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (1786 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fb531c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556fb5319505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556fb531ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f23533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f2358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f23533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f2351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fb52b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556fb52b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556fb5296f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556fb4f46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556fb4f45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f2351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f2351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f2351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fb4f45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (1787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562030be256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562030bdf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562030be2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d81d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d81d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d81d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d81d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562030b7823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562030b78086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562030b5cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056203080c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056203080be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d81d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d81d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d81d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056203080bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (1788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b6287656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b62873505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b62876cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feea5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feea518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feea5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feea511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b6280c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b6280c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b627f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b624a0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b6249fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feea511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feea511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feea511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b6249fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (1789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <v
# | ...
# `---data was truncated (10240/98125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560536f5956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560536f56505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560536f59cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96e0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96e058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96e0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96e051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560536eef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560536eef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560536ed3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560536b83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560536b82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f96e051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96e051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96e051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560536b82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (1790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6ea75b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6ea758505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6ea75bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e70333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e7038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e70333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e7031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6ea6f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6ea6f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6ea6d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6ea385166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6ea384e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e7031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e7031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e7031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6ea384d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (1791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr
# | ...
# `---data was truncated (10240/29319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a7c36656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a7c363505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a7c366cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff99e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff99e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff99e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff99e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a7c2fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a7c2fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a7c2e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a7bf90166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a7bf8fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff99e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff99e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff99e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a7bf8fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (1792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b017cf956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b017cf6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b017cf9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d6e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d6e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d6e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d6e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b017c8f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b017c8f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b017c73f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b017923166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b017922e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d6e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d6e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d6e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b017922d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (1793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e47582956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e475826505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e475829cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc206333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc20638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc206333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc20631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4757bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4757bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4757a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e475453166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e475452e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc20631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc20631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc20631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e475452d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (1794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddf9ab656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ddf9ab3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ddf9ab6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaf3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaf34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaf3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaf3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddf9a4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ddf9a4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ddf9a30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ddf96e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ddf96dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffaf3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaf34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaf34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddf96dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (1795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee705e856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee705e5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee705e8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d58733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d5878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d58733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d5871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee7057e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee7057e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee70562f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee70212166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee70211e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d5871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d5871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d5871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee70211d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (1796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b59e9e056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b59e9dd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b59e9e0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76edd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76edd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76edd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76edd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b59e97623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b59e976086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b59e95af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b59e60a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b59e609e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f76edd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76edd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76edd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b59e609d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (1797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/29371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cee6d7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cee6d72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cee6d75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ef8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ef8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ef8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ef8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cee6d0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cee6d0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cee6ceff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cee699f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cee699ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ef8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ef8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ef8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cee699ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (1798 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603927a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603927a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603927a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f097161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09716725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f097161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0971603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056039273923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560392739086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056039271df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005603923cd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005603923cce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0971604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09716050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09716050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603923ccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (1799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> 
# | ...
# `---data was truncated (10240/63117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055c7a87db56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c7a87d8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c7a87dbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3339249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33392a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3339249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3339231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7a877123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c7a8771086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c7a8755f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c7a8405166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c7a8404e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3339232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33392330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33392330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7a8404d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (1800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/70979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632b598456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005632b5981505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005632b5984cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25a5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25a5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25a5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25a5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632b591a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005632b591a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005632b58fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005632b55ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005632b55ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f25a5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25a5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25a5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632b55add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (1801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfd6e2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfd6e1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfd6e20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0055c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0055ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0055c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0055c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd6db623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfd6db6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfd6d9af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfd6a4a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfd6a49e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0055c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0055c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0055c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd6a49d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (1802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626b20a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005626b209d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005626b20a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ae8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ae8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ae8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ae8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626b203623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005626b2036086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005626b201af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005626b1cca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005626b1cc9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ae8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ae8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ae8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626b1cc9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (1803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d45b9e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d45b9e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d45b9e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1970c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1970ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1970c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1970c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d45b97c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d45b97c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d45b960f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d45b610166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d45b60fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1970c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1970c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1970c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d45b60fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (1804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ceec6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561ceec63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561ceec66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd64a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd64aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd64a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd64a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ceebfc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561ceebfc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561ceebe0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561cee890166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561cee88fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd64a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd64a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd64a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cee88fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (1805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4937f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d4937f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d4937f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff183b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff183b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff183b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff183b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d49378923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d493789086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d49376df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d49341d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d49341ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff183b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff183b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff183b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d49341cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (1806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559afd65856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559afd655505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559afd658cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f162bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f162bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f162bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f162bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559afd5ee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559afd5ee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559afd5d2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559afd282166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559afd281e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f162bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f162bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f162bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559afd281d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (1807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef
# | ...
# `---data was truncated (10240/14333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe19dec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fe19de9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fe19deccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe92f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe92f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe92f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe92f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe19d8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fe19d82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fe19d66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fe19a16166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fe19a15e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe92f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe92f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe92f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe19a15d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (1808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 nounde
# | ...
# `---data was truncated (10240/26592) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056459fe6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056459fe6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056459fe6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab75733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab7578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab75733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab7571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056459fe0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056459fe03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056459fde7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056459fa97166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056459fa96e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab7571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab7571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab7571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056459fa96d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (1809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588a31e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005588a31de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005588a31e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e31f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e31f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e31f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e31f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588a317723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005588a3177086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005588a315bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005588a2e0b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005588a2e0ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1e31f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e31f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e31f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588a2e0ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (1810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e52095956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e520956505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e520959cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0874849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08748a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0874849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0874831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5208ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e5208ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e5208d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e520583166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e520582e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0874832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08748330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08748330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e520582d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (1811 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055947911956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559479116505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559479119cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55a001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55a00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55a001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55a0003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594790af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594790af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559479093f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559478d43166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559478d42e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f55a0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55a00050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55a00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559478d42d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (1812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @l
# | ...
# `---data was truncated (10240/62760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd6fe1f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bd6fe1c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bd6fe1fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2a2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2a2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2a2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2a2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd6fdb523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bd6fdb5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bd6fd99f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bd6fa49166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bd6fa48e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc2a2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2a2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2a2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd6fa48d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (1813 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577509ea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005577509e7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005577509eacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f203861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20386725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f203861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2038603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055775098023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557750980086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557750964f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557750614166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557750613e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2038604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20386050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20386050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557750613d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-fma.c (1814 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %sub.i = fsub <4 x float> %3, %mul.i
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %sub.i = fsub <2 x float> %3, %mul.i
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_68 = alloca <2 x float>, align 8
# |   %__s0_68 = alloca <2 x float>, align 8
# |   %__s1_68 = alloca <2 x float>, align 8
# |   %__s2_68 = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp1 = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0_68, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_68, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_68, align 8
# |   %3 = load <2 x float>, ptr %__s0_68, align 8
# |   %4 = load <2 x float>, ptr %__s1_68, align 8
# |   %5 = load <2 x float>, ptr %__s2_68, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   %mul = fmul <2 x float> %4, %10
# |   %add = fadd <2 x float> %3, %mul
# |   store <2 x float> %add, ptr %__ret_68, align 8
# |   %11 = load <2 x float>, ptr %__ret_68, align 8
# |   store <2 x float> %11, ptr %tmp1, align 8
# |   %12 = load <2 x float>, ptr %tmp1, align 8
# |   ret <2 x float> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_58 = alloca <4 x float>, align 16
# |   %__s0_58 = alloca <4 x float>, align 16
# |   %__s1_58 = alloca <4 x float>, align 16
# |   %__s2_58 = alloca <2 x float>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp1 = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__s0_58, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_58, align 16
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_58, align 8
# |   %3 = load <4 x float>, ptr %__s0_58, align 16
# |   %4 = load <4 x float>, ptr %__s1_58, align 16
# |   %5 = load <2 x float>, ptr %__s2_58, align 8
# |   store <2 x f
# | ...
# `---data was truncated (10240/44730) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055df00e1e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055df00e1b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055df00e1ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc46fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc46fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc46fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc46fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df00db423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055df00db4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055df00d98f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055df00a48166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055df00a47e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc46fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc46fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc46fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df00a47d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (1815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056464973a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564649737505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056464973acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f560bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f560bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f560bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f560bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646496d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646496d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646496b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564649364166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564649363e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f560bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f560bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f560bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564649363d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (1816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ad336656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ad3363505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ad3366cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd47133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd4718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd47133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd4711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ad32fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ad32fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ad32e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ad2f90166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ad2f8fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd4711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd4711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd4711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ad2f8fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (1817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055752497d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055752497a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055752497dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f449a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f449a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f449a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f449a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055752491323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557524913086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005575248f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005575245a7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005575245a6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f449a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f449a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f449a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575245a6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (1818 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055804b59556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055804b592505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055804b595cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c3a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c3a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c3a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c3a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055804b52b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055804b52b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055804b50ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055804b1bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055804b1bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c3a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c3a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c3a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055804b1bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (1819 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a3786856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a37865505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a37868cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29fcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29fcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29fcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29fcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a377fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a377fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a377e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a37492166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a37491e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f29fcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29fcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29fcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a37491d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (1820 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e88d19056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e88d18d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e88d190cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1526649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1526649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1526631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e88d12623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e88d126086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e88d10af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e88cdba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e88cdb9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1526632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15266330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e88cdb9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (1821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4e96c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4e96bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4e96c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe849f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe849f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe849f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe849f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4e965823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f4e9658086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f4e963cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4e92ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4e92ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe849f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe849f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe849f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4e92ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (1822 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee9a86256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee9a85f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee9a862cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31ddd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31ddd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31ddd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31ddd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee9a7f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee9a7f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee9a7dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee9a48c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee9a48be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f31ddd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31ddd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31ddd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee9a48bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (1823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr %0, i64 %2)
# |   %4 =
# | ...
# `---data was truncated (10240/33471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559ff5e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559ff5e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559ff5e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48b0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48b078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48b0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48b071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559ff57923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559ff579086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559ff55df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559ff20d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559ff20ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f48b071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48b071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48b071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559ff20cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (1824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d4fd8556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560d4fd82505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560d4fd85cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde23333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde2338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde23333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde2331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d4fd1b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560d4fd1b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560d4fcfff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560d4f9af166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560d4f9aee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde2331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde2331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde2331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d4f9aed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (1825 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c034abc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c034ab9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c034abccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce36133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce3618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce36133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce3611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c034a5223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c034a52086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c034a36f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c0346e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c0346e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce3611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce3611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce3611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0346e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (1826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637805f956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637805f6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637805f9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ee8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ee878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ee8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ee871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056378058f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056378058f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563780573f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563780223166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563780222e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3ee871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ee871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ee871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563780222d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (1827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c147a9956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c147a96505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c147a99cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3e0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3e078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3e0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3e071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c147a2f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c147a2f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c147a13f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1476c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1476c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa3e071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3e071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3e071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1476c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (1828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576127ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576127fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576127ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e49a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e49a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e49a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e49a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055761279523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557612795086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557612779f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557612429166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557612428e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e49a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e49a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e49a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557612428d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (1829 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569f86d156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005569f86ce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005569f86d1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8723f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8723f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8723f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8723f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569f866723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005569f8667086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005569f864bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005569f82fb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005569f82fae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8723f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8723f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8723f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569f82fad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (1830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056335a51156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056335a50e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056335a511cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd008e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd008ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd008e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd008e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056335a4a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056335a4a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056335a48bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056335a13b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056335a13ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd008e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd008e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd008e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056335a13ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (1831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056380c46c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056380c469505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056380c46ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc22a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc22a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056380c40223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056380c402086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056380c3e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056380c096166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056380c095e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc22a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056380c095d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (1832 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/12050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f0b9c956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f0b9c6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f0b9c9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a17a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a17a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a17a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a17a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f0b95f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f0b95f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f0b943f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f0b5f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f0b5f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a17a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a17a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a17a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f0b5f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (1833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560106d9156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560106d8e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560106d91cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ca9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ca90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ca9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ca9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560106d2723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560106d27086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560106d0bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601069bb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601069bae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ca9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ca90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ca90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601069bad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (1834 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, a
# | ...
# `---data was truncated (10240/81515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586df6b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005586df6b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005586df6b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2c3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2c3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2c3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2c3c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586df64d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005586df64d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005586df631f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586df2e1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586df2e0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe2c3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2c3c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2c3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586df2e0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (1835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a3a29856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563a3a295505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563a3a298cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78d8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78d8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78d8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78d8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a3a22e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563a3a22e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563a3a212f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563a39ec2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563a39ec1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78d8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78d8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78d8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a39ec1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (1836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055970ab3556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055970ab32505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055970ab35cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96d2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96d278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96d2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96d271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055970aacb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055970aacb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055970aaaff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055970a75f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055970a75ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f96d271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96d271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96d271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055970a75ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (1837 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_3_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d1ea48e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d1ea48b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d1ea48ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe727533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe72758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe727533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe72751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1ea42423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d1ea424086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d1ea408f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d1ea0b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d1ea0b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe72751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe72751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe72751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1ea0b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (1838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559170f4556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559170f42505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559170f45cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53de41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53de4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53de41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53de403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559170edb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559170edb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559170ebff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559170b6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559170b6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f53de404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53de4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53de4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559170b6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (1839 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056547246b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565472468505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056547246bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd05f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd05f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd05f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd05f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056547240123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565472401086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005654723e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565472095166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565472094e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd05f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd05f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd05f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565472094d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (1840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9caee956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b9caee6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b9caee9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b7f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b7f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b7f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b7f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9cae7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b9cae7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b9cae63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9cab13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9cab12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5b7f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b7f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b7f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9cab12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (1841 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue
# | ...
# `---data was truncated (10240/81764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d92575c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d925759505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d92575ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39a3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39a318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39a3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39a311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9256f223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9256f2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9256d6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d925386166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d925385e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f39a311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39a311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39a311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d925385d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (1842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfeb34156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfeb33e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfeb341cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fda305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fda35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fda305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fda2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfeb2d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfeb2d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfeb2bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfeaf6b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfeaf6ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0fda2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fda2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fda2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfeaf6ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (1843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x h
# | ...
# `---data was truncated (10240/619135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561399b3956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561399b36505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561399b39cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e75533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e7558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e75533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e7551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561399acf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561399acf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561399ab3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561399763166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561399762e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e7551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e7551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e7551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561399762d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (1844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/126428) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2f0f7156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2f0f6e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2f0f71cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5e0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5e0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5e0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5e0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2f0f0723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f2f0f07086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f2f0eebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f2f0b9b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f2f0b9ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff5e0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5e0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5e0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2f0b9ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (1845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055707d52756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055707d524505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055707d527cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5420649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54206a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5420649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5420631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055707d4bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055707d4bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055707d4a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055707d151166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055707d150e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5420632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54206330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54206330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055707d150d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (1846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ec6f1d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ec6f1a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ec6f1dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9fcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9fcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9fcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9fcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ec6eb323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ec6eb3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ec6e97f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ec6b47166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ec6b46e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe9fcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9fcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9fcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ec6b46d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (1847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, a
# | ...
# `---data was truncated (10240/98149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d94e79056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d94e78d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d94e790cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03a3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03a378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03a3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03a371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d94e72623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d94e726086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d94e70af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d94e3ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d94e3b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03a371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03a371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03a371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d94e3b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (1848 of 27911)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1
# | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649febd156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649febce505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649febd1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe9e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe9e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe9e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe9e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649feb6723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005649feb67086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005649feb4bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005649fe7fb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005649fe7fae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe9e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe9e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe9e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649fe7fad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (1849 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i)
# |   %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8>
# |   store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i)
# |   %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i)
# |   %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8>
# |   store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i)
# |   %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i)
# |   %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8>
# |   store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i)
# |   %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i)
# |   %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8>
# |   store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i)
# |   %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i)
# |   %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8>
# |   store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i)
# |   %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i)
# |   %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8>
# |   store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x
# | ...
# `---data was truncated (10240/16447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a78b00456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a78b001505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a78b004cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6194c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6194ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6194c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6194c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a78af9a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a78af9a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a78af7ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a78ac2e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a78ac2de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6194c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6194c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6194c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a78ac2dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (1850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605af3de56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005605af3db505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005605af3decab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c98133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c9818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c98133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c9811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605af37423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005605af374086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005605af358f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005605af008166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005605af007e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7c9811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c9811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c9811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605af007d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (1851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de9b23f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de9b23c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de9b23fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24fd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24fd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24fd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24fd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de9b1d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de9b1d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de9b1b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de9ae69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de9ae68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f24fd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24fd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24fd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de9ae68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (1852 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627e393156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005627e392e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005627e3931cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc077733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc07778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc077733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc07771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627e38c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627e38c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005627e38abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627e355b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627e355ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc07771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc07771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc07771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627e355ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (1853 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf2716556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf27162505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf27165cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d01333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d0138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d01333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d0131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf270fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf270fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf270dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf26d8f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf26d8ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d0131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d0131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d0131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf26d8ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (1854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4d7f4e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4d7f4b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4d7f4ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9773f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9773f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9773f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9773f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4d7ee423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4d7ee4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4d7ec8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4d7b78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4d7b77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9773f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9773f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9773f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4d7b77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (1855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.v
# | ...
# `---data was truncated (10240/58683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c23978356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c239780505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c239783cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14f1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14f1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14f1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14f1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c23971923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c239719086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c2396fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c2393ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c2393ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f14f1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14f1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14f1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2393acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (1856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fc3f1e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555fc3f1b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555fc3f1ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fc4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fc4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fc4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fc4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fc3eb423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555fc3eb4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555fc3e98f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555fc3b48166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555fc3b47e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1fc4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fc4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fc4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fc3b47d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (1857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055959eea956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055959eea6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055959eea9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a55733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a5578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a55733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a5571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055959ee3f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055959ee3f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055959ee23f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055959ead3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055959ead2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0a5571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a5571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a5571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055959ead2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (1858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.
# | ...
# `---data was truncated (10240/78156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055853a22c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055853a229505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055853a22ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28fa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28fa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28fa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28fa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055853a1c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055853a1c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055853a1a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558539e56166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558539e55e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f28fa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28fa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28fa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558539e55d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (1859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9ebc1d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e9ebc1a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e9ebc1dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63e0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63e078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63e0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63e071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9ebbb323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e9ebbb3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9ebb97f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e9eb847166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e9eb846e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f63e071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63e071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63e071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9eb846d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (1860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056017d65956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056017d656505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056017d659cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f120d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f120d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f120d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f120d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056017d5ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056017d5ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056017d5d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056017d283166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056017d282e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f120d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f120d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f120d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056017d282d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (1861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   s
# | ...
# `---data was truncated (10240/280209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb6539d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb6539a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb6539dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0b2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0b20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0b2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0b2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb6533323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb65333086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb65317f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb64fc7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb64fc6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff0b2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0b20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0b20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb64fc6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (1862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557596a1556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557596a12505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557596a15cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3febd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3febd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3febd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3febd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575969ab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005575969ab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055759698ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055759663f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055759663ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3febd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3febd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3febd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055759663ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (1863 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <4 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <4 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <4 x i16> %vbsl5.i to <4 x half>
# |   store <4 x half> %7, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbsl.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <8 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <8 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <8 x i16> %vbsl5.i to <8 x half>
# |   store <8 x half> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x half> %vzip.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x half> %vzip1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x half> %vzip.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x half> %vzip1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   store <4 x half> %vuzp.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   store <4 x half> %vuzp1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   store <8 x half> %vuzp.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   store <8 x half> %vuzp1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef 
# | ...
# `---data was truncated (10240/31986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055fb9f95256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb9f94f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb9f952cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0038449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00384a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0038449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0038431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb9f8e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb9f8e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb9f8ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb9f57c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb9f57be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0038432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00384330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00384330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb9f57bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (1864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581c035056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005581c034d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005581c0350cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3704c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3704ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3704c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3704c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581c02e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581c02e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581c02caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581bff7a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581bff79e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3704c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3704c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3704c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581bff79d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (1865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561082ebd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561082eba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561082ebdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fcbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fcbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fcbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fcbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561082e5323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561082e53086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561082e37f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561082ae7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561082ae6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9fcbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fcbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fcbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561082ae6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (1866 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a939d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a939d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a939d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd50533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd50533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a9396a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a9396a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a9394ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a935fe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a935fde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd5051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a935fdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (1867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e23eb556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e23eb2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e23eb5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41b2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41b22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41b2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41b2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e23e4b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e23e4b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e23e2ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e23adf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e23adee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f41b2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41b22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41b22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e23aded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (1868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.
# | ...
# `---data was truncated (10240/24951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1984fb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d1984f8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d1984fbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7421b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7421b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7421b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7421b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d19849123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d198491086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d198475f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d198125166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d198124e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7421b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7421b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7421b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d198124d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (1869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b18c16c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b18c169505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b18c16ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5d0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5d018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5d0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5d011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b18c10223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b18c102086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b18c0e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b18bd96166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b18bd95e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc5d011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5d011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5d011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b18bd95d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (1870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560eab0b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560eab0b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560eab0b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff671705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff67175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff671705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6716ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560eab04c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560eab04c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560eab030f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560eaace0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560eaacdfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff6716eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6716ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6716ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560eaacdfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (1871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0cda6456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f0cda61505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f0cda64cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cc8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cc8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cc8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cc8e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0cd9fa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0cd9fa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0cd9def39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f0cd68e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f0cd68de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2cc8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cc8e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cc8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0cd68dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (1872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/51751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6d78a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6d78a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6d78a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb726c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb726ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb726c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb726c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6d783f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6d783f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6d7823f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6d74d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6d74d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb726c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb726c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb726c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6d74d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (1873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592cf7c056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005592cf7bd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005592cf7c0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06f5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06f5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06f5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06f5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592cf75623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005592cf756086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005592cf73af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005592cf3ea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005592cf3e9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f06f5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06f5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06f5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592cf3e9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (1874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/28559) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565a43b156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565a43ae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565a43b1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa99a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa99a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa99a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa99a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565a434723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565a4347086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565a432bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565a3fdb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565a3fdae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa99a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa99a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa99a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565a3fdad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (1875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c8b4a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c8b4a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c8b4a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb53849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb538a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb53849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb53831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c8b43f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c8b43f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c8b423f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c8b0d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c8b0d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb53832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb538330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb538330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c8b0d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (1876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6b679556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c6b6792505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c6b6795cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2a3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2a3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2a3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2a3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6b672b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c6b672b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c6b670ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c6b63bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c6b63bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa2a3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2a3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2a3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6b63bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (1877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loca
# | ...
# `---data was truncated (10240/18587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056017c79256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056017c78f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056017c792cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b14e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b14ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b14e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b14e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056017c72823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056017c728086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056017c70cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056017c3bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056017c3bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b14e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b14e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b14e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056017c3bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (1878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0ae21c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a0ae219505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a0ae21ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c1f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c1f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c1f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c1f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0ae1b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a0ae1b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a0ae196f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a0ade46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a0ade45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c1f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c1f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c1f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0ade45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (1879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646d37dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646d37d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646d37dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67ea249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67ea2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67ea249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67ea231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646d377223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646d3772086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646d3756f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646d3406166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646d3405e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f67ea232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67ea2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67ea2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646d3405d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (1880 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c  -check-prefix=RV64ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64es(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64esm(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055673106756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556731064505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556731067cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb422449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4224a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb422449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb422431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556730ffd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556730ffd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556730fe1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556730c91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556730c90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb422432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4224330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4224330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556730c90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (1881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad9539b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad95398505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad9539bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbad1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbad1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbad1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbad1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad9533123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad95331086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad95315f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad94fc5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad94fc4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbad1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbad1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbad1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad94fc4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (1882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d070b956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d070b6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d070b9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73db31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d0704f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d0704f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d07033f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d06ce3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d06ce2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f73db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73db31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d06ce2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (1883 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/48385) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056034ac3a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056034ac37505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056034ac3acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3916b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3916b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3916b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3916b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056034abd023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056034abd0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056034abb4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056034a864166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056034a863e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3916b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3916b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3916b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056034a863d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (1884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621d178f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005621d178c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005621d178fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f14b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f14b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f14b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f14b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621d172523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005621d1725086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005621d1709f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005621d13b9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005621d13b8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0f14b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f14b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f14b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621d13b8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (1885 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpkhi_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005569938a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055699389d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005569938a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4729d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4729d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4729d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4729d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055699383623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556993836086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055699381af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005569934ca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005569934c9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4729d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4729d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4729d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569934c9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (1886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612f59b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005612f59b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005612f59b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f44933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f4498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f44933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f4491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612f594c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005612f594c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005612f5930f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005612f55e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005612f55dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f4491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f4491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f4491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612f55dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (1887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646f2aec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646f2ae9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646f2aeccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32a831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646f2a8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646f2a82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646f2a66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646f2716166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646f2715e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f32a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32a831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646f2715d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (1888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5261bd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a5261ba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a5261bdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff11e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff11e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff11e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff11e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a52615323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a526153086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a526137f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a525de7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a525de6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff11e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff11e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff11e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a525de6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (1889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/58460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff19e7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ff19e74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ff19e77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f490f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f490f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f490f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f490f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff19e0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ff19e0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ff19df1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ff19aa1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ff19aa0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f490f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f490f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f490f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff19aa0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (1890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620774c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005620774c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005620774c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd8dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd8dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd8dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd8dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056207745d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056207745d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562077441f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005620770f1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005620770f0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd8dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd8dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd8dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620770f0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (1891 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to double
# |   %7 = bitcast <8 x i8> %4 to double
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %extract = extractelement <2 x double> %8, i32 0
# |   %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   %10 = bitcast double %9 to <1 x double>
# |   store <1 x double> %10, ptr %ref.tmp, align 8
# |   %11 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %11, ptr %__ret, align 8
# |   %12 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %12, ptr %tmp, align 8
# |   %13 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %13
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__s0, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1, align 16
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> <i32 1, i32 1>
# |   %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %9, ptr %ref.tmp, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %10, ptr %__ret, align 16
# |   %11 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %11, ptr %tmp, align 16
# |   %12 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load float, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %5, i32 1
# |   %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store float %6, ptr %ref.tmp, align 4
# |   %7 = load float, ptr %ref.tmp, align 4
# |   store float %7, ptr %__ret, align 4
# |   %8 = load float, ptr %__ret, align 4
# |   store float %8, ptr %tmp, align 4
# |   %9 = load float, ptr %tmp, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000559ee1d1556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ee1d12505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ee1d15cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7136a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7136a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7136a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7136a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ee1cab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ee1cab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ee1c8ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ee193f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ee193ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7136a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7136a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7136a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ee193ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (1892 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfc4db956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfc4db6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfc4db9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03fb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03fb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03fb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03fb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfc4d4f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfc4d4f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfc4d33f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfc49e3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfc49e2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03fb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03fb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03fb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfc49e2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (1893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601be3b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005601be3b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601be3b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f717c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f717c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f717c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f717c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601be34a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005601be34a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005601be32ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601bdfde166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601bdfdde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f717c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f717c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f717c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601bdfddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (1894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056095a72956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056095a726505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056095a729cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcf4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcf478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcf4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcf471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056095a6bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056095a6bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056095a6a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056095a353166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056095a352e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbcf471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcf471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcf471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056095a352d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (1895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056509323756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565093234505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565093237cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f883e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f883e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f883e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f883e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650931cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005650931cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005650931b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565092e61166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565092e60e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f883e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f883e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f883e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565092e60d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (1896 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a128d356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556a128d0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556a128d3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff8b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff8b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff8b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff8b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a1286923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556a12869086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556a1284df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556a124fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556a124fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff8b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff8b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff8b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a124fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (1897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b27d39a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b27d397505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b27d39acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f4821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f482725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f4821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f48203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b27d33023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b27d330086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b27d314f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b27cfc4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b27cfc3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f48204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f482050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f482050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b27cfc3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (1898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/14493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056522e08d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056522e08a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056522e08dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0d0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0d06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0d0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0d0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056522e02323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056522e023086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056522e007f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056522dcb7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056522dcb6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd0d0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0d06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0d06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056522dcb6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (1899 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563d18c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563d18c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563d18c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f226ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f226ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f226ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f226ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563d185c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005563d185c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005563d1840f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005563d14f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005563d14efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f226ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f226ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f226ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563d14efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (1900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582edc8f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005582edc8c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005582edc8fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88b5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88b52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88b5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88b5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582edc2523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582edc25086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582edc09f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582ed8b9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582ed8b8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f88b5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88b52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88b52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582ed8b8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (1901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccbf8e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccbf8de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccbf8e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8dd5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8dd5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8dd5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8dd5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccbf87723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccbf877086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccbf85bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ccbf50b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ccbf50ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8dd5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8dd5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8dd5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccbf50ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (1902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 
# | ...
# `---data was truncated (10240/43617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b033bbe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b033bbb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b033bbecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f186b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f186b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f186b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f186b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b033b5423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b033b54086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b033b38f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b0337e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b0337e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f186b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f186b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f186b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0337e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (1903 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564decca756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564decca4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564decca7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb00c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb00c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb00c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb00c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564decc3d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564decc3d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564decc21f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564dec8d1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564dec8d0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb00c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb00c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb00c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564dec8d0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (1904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale
# | ...
# `---data was truncated (10240/156471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581cd45256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005581cd44f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005581cd452cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47a9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47a9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47a9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47a9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581cd3e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581cd3e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581cd3ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581cd07c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581cd07be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47a9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47a9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47a9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581cd07bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (1905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587bd05b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587bd058505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587bd05bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f005eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f005eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f005eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f005eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587bcff123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005587bcff1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005587bcfd5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005587bcc85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005587bcc84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f005eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f005eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f005eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587bcc84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (1906 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d    -target-feature +v -target-feature +zfh -target-feature +zvfh    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 8)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t(<vscale x 16 x i8> %dest, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 8)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556be56c156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556be56be505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556be56c1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f160ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f160eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f160ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f160ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556be565723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556be5657086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556be563bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556be52eb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556be52eae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f160ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f160ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f160ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556be52ead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (1907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f93084d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f93084a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f93084dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85e8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85e8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85e8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85e8e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9307e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f9307e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f9307c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f930477166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f930476e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f85e8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85e8e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85e8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f930476d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (1908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7ccf5156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f7ccf4e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f7ccf51cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd54e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd54ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd54e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd54e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7ccee723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f7ccee7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f7ccecbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7ccb7b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7ccb7ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd54e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd54e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd54e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7ccb7ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (1909 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = sitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = uitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = sitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = uitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptosi <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptosi <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptoui <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptoui <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm
# | ...
# `---data was truncated (10240/37578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056245342356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562453420505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562453423cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3b5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3b578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3b5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3b571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624533b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005624533b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056245339df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056245304d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056245304ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb3b571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3b571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3b571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056245304cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (1910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a529fce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a529fcb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a529fcecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd566b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd566b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd566b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd566b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a529f6423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a529f64086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a529f48f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a529bf8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a529bf7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd566b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd566b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd566b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a529bf7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (1911 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm
# | ...
# `---data was truncated (10240/53200) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ab135e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557ab135b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557ab135ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdeee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdeeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdeee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdeee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ab12f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557ab12f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557ab12d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557ab0f88166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557ab0f87e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efdeee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdeee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdeee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ab0f87d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (1912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2e101456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b2e1011505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b2e1014cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c7e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c7e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c7e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c7e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2e0faa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b2e0faa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b2e0f8ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b2e0c3e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b2e0c3de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c7e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c7e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c7e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2e0c3dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (1913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %v
# | ...
# `---data was truncated (10240/86747) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055557f14c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055557f149505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055557f14ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62cbe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62cbe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62cbe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62cbe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055557f0e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055557f0e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055557f0c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055557ed76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055557ed75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62cbe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62cbe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62cbe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055557ed75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (1914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d78c1556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d78c12505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d78c15cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61cb41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61cb4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61cb41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61cb403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d78bab23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d78bab086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d78b8ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d7883f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d7883ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61cb404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61cb4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61cb4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d7883ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (1915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f6f1db56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f6f1d8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f6f1dbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2722533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f272258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2722533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f272251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f6f17123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f6f171086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f6f155f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f6ee05166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f6ee04e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f272251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f272251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f272251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f6ee04d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (1916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8a7c7c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e8a7c79505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e8a7c7ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84d6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84d6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84d6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84d6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8a7c1223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e8a7c12086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8a7bf6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e8a78a6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e8a78a5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84d6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84d6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84d6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8a78a5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (1917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e474b9256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e474b8f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e474b92cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd44fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd44faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd44fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd44fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e474b2823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e474b28086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e474b0cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4747bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4747bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd44fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd44fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd44fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4747bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (1918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 
# | ...
# `---data was truncated (10240/14429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f0cb1356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f0cb10505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f0cb13cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35ae533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35ae58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35ae533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35ae51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f0caa923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f0caa9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f0ca8df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f0c73d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f0c73ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f35ae51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35ae51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35ae51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f0c73cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (1919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.n
# | ...
# `---data was truncated (10240/33624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8d994256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b8d993f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b8d9942cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f35649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f356a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f35649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f35631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8d98d823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b8d98d8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b8d98bcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b8d956c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b8d956be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f35632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f356330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f356330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8d956bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (1920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/53678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c97f8856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c97f85505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c97f88cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda01f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda01f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda01f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda01f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c97f1e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c97f1e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c97f02f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c97bb2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c97bb1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda01f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda01f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda01f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c97bb1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (1921 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dff562356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dff5620505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dff5623cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0612d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0612d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0612d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0612d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dff55b923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dff55b9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dff559df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dff524d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dff524ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0612d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0612d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0612d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dff524cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/cx-complex-range.c (1922 of 27911)
******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %coerce.real, ptr %retval.realp, align 4
# |   store float %coerce.imag, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__divsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %coerce.real, ptr %.realp1, align 4
# |   store float %coerce.imag, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul_ac = fmul float %a.real, %b.real
# |   %mul_bd = fmul float %a.imag, %b.imag
# |   %mul_ad = fmul float %a.real, %b.imag
# |   %mul_bc = fmul float %a.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %real_mul_phi, ptr %retval.realp, align 4
# |   store float %imag_mul_phi, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__mulsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul_ac = fmul float %.real, %b.real
# |   %mul_bd = fmul float %.imag, %b.imag
# |   %mul_ad = fmul float %.real, %b.imag
# |   %mul_bc = fmul float %.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %real_mul_phi, ptr %.realp2, align 4
# |   store float %imag_mul_phi, ptr %.imagp3, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b = alloca { double, double }, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %2, align 8
# |   %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %3, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load doub
# | ...
# `---data was truncated (10240/29171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000555f5782e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555f5782b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555f5782ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f577c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555f577c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555f577a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555f57458166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555f57457e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87c991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f57457d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (1923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ef8d9e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ef8d9b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ef8d9ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9507c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9507ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9507c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9507c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ef8d3423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ef8d34086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ef8d18f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ef89c8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ef89c7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9507c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9507c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9507c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ef89c7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (1924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv
# | ...
# `---data was truncated (10240/75133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558126adf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558126adc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558126adfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f056a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f056a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f056a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f056a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558126a7523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558126a75086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558126a59f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558126709166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558126708e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f056a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f056a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f056a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558126708d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (1925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a9294756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556a92944505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556a92947cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62a5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62a5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62a5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62a5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a928dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556a928dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556a928c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556a92571166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556a92570e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62a5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62a5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62a5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a92570d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (1926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c  -check-prefix=RV32XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clo_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055565686f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055565686c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055565686fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f158261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15826725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f158261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1582603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055565680523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555656805086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005556567e9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555656499166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555656498e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1582604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15826050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15826050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555656498d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (1927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/205805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645ee49556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645ee492505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645ee495cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5d5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5d5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5d5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5d5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645ee42b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645ee42b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645ee40ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645ee0bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645ee0bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa5d5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5d5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5d5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645ee0bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (1928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d85915d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d85915a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d85915dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbc3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbc32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbc3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbc3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8590f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8590f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8590d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d858d87166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d858d86e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcbc3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbc32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbc32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d858d86d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (1929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a2566f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a2566c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a2566fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe065133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe06518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe065133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe06511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a2560523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a25605086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a255e9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a25299166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a25298e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe06511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe06511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe06511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a25298d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (1930 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp uge <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp uge <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp uge <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8e7c8156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8e7c7e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8e7c81cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa883e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa883e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa883e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa883e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8e7c1723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8e7c17086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8e7bfbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8e78ab166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8e78aae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa883e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa883e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa883e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8e78aad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (1931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.abs.i32(i32 %0, i1 true)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.abs.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp sle i32 %0, %1
# |   %sle = zext i1 %2 to i32
# |   ret i32 %sle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp ule i32 %0, %1
# |   %sleu = zext i1 %2 to i32
# |   ret i32 %sleu
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = sext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exths = sext i16 %1 to i32
# |   ret i32 %exths
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = zext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exthz = zext i16 %1 to i32
# |   ret i32 %exthz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = sext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbs = sext i8 %1 to i32
# |   ret i32 %extbs
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = zext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbz = zext i8 %1 to i32
# |   ret i32 %extbz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xcvalu1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8efcfa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a8efcf7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a8efcfacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1659b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1659b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1659b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1659aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8efc9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a8efc90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a8efc74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a8ef924166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a8ef923e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1659aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1659aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1659aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8ef923d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (1932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/150943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a4d9bd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a4d9ba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a4d9bdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe85c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe85c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe85c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe85c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a4d95323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a4d953086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a4d937f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a4d5e7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a4d5e6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe85c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe85c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe85c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a4d5e6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (1933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb9d31956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bb9d316505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bb9d319cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f845e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f845e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f845e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f845e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb9d2af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bb9d2af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bb9d293f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bb9cf43166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bb9cf42e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f845e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f845e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f845e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb9cf42d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (1934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab49eac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab49ea9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab49eaccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd752f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd752f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd752f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd752f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab49e4223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab49e42086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab49e26f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab49ad6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab49ad5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd752f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd752f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd752f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab49ad5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (1935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed58cb656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed58cb3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed58cb6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9660e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9660ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9660e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9660e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed58c4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed58c4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed58c30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed588e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed588dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9660e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9660e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9660e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed588dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (1936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a60605f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a60605c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a60605fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaba849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaba8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaba849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaba831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a605ff523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a605ff5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a605fd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a605c89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a605c88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faaba832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaba8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaba8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a605c88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (1937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056383293856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563832935505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563832938cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf0b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf0b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf0b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf0b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638328ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638328ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638328b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563832562166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563832561e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcf0b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf0b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf0b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563832561d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (1938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/11938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601b776c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005601b7769505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601b776ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdea5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdea598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdea5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdea591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601b770223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005601b7702086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005601b76e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601b7396166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601b7395e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdea591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdea591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdea591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601b7395d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (1939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl
# | ...
# `---data was truncated (10240/78896) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056552de1c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056552de19505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056552de1ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1000733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f100078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1000733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f100071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056552ddb223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056552ddb2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056552dd96f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056552da46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056552da45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f100071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f100071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f100071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056552da45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (1940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055833be4d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055833be4a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055833be4dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ce5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ce50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ce5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ce5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055833bde323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055833bde3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055833bdc7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055833ba77166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055833ba76e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ce5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ce50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ce50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055833ba76d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (1941 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056035e8be56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056035e8bb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056035e8becab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d40049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d400a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d40049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d40031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056035e85423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056035e854086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056035e838f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056035e4e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056035e4e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d40032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d400330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d400330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056035e4e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (1942 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba92d8f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba92d8c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba92d8fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0328933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f032898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0328933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f032891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba92d2523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba92d25086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba92d09f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba929b9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba929b8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f032891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f032891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f032891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba929b8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (1943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556e2c7f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005556e2c7c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005556e2c7fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0443b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0443b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0443b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0443b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556e2c1523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005556e2c15086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005556e2bf9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005556e28a9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005556e28a8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0443b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0443b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0443b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556e28a8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (1944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b327abd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b327aba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b327abdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce26933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce2698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce26933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce2691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b327a5323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b327a53086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b327a37f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b3276e7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b3276e6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce2691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce2691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce2691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3276e6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (1945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %v
# | ...
# `---data was truncated (10240/43948) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615f33d656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615f33d3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615f33d6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbaf905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbaf95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbaf905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbaf8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615f336c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615f336c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615f3350f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615f3000166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615f2fffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffbaf8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbaf8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbaf8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615f2fffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (1946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c8966556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c89662505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c89665cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5051b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5051b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5051b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5051b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c895fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c895fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c895dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c8928f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c8928ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5051b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5051b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5051b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c8928ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (1947 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 
# | ...
# `---data was truncated (10240/11881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560a3adc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005560a3ad9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005560a3adccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd866f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd866f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd866f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd866f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560a3a7223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005560a3a72086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005560a3a56f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005560a3706166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005560a3705e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd866f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd866f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd866f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560a3705d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (1948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614c43bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005614c43b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005614c43bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca87733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca8778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca87733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca8771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614c435223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005614c4352086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005614c4336f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005614c3fe6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005614c3fe5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca8771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca8771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca8771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614c3fe5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (1949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055919567256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055919566f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559195672cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c1661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c166725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c1661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c16603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055919560823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559195608086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005591955ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055919529c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055919529be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5c16604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c166050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c166050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055919529bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (1950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/69542) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a30913756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a309134505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a309137cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1ae41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1ae4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1ae41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1ae403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3090cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a3090cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a3090b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a308d61166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a308d60e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff1ae404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1ae4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1ae4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a308d60d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (1951 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056213d58956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056213d586505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056213d589cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7e2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7e2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7e2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7e2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056213d51f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056213d51f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056213d503f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056213d1b3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056213d1b2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb7e2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7e2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7e2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056213d1b2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (1952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056024733956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560247336505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560247339cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4914449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4914449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4914431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602472cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005602472cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005602472b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560246f63166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560246f62e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4914432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49144330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560246f62d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (1953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x 
# | ...
# `---data was truncated (10240/26696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5f8e4456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d5f8e41505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d5f8e44cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa9fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa9fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa9fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa9fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5f8dda23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d5f8dda086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d5f8dbef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d5f8a6e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d5f8a6de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa9fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa9fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa9fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5f8a6dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (1954 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16276156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c16275e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c162761cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff348533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff34858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff348533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff34851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1626f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1626f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1626dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c16238b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c16238ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff34851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff34851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff34851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c16238ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (1955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b24601156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b24600e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b246011cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2185a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2185aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2185a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2185a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b245fa723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b245fa7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b245f8bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b245c3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b245c3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2185a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2185a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2185a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b245c3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (1956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652b456d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652b456a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652b456dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f466e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f466e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f466e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f466e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652b450323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005652b4503086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005652b44e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005652b4197166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005652b4196e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f466e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f466e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f466e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652b4196d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (1957 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi    -target-feature +neon -target-feature +bf16 -mfloat-abi soft    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_812 = alloca <4 x float>, align 8
# |   %__s0_812 = alloca <4 x float>, align 8
# |   %__s1_812 = alloca <8 x bfloat>, align 8
# |   %__s2_812 = alloca <8 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x float>, align 8
# |   %__ret = alloca <4 x float>, align 8
# |   %__s0 = alloca <4 x float>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x float>, align 8
# |   %tmp2 = alloca <4 x float>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   store <4 x float> %0, ptr %__s0_812, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   store <8 x bfloat> %1, ptr %__s1_812, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <8 x bfloat> %2, ptr %__s2_812, align 8
# |   %3 = load <4 x float>, ptr %__s0_812, align 8
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 8
# |   %5 = load <4 x float>, ptr %__s2_812, align 8
# |   store <4 x float> %5, ptr %__s0, align 8
# |   %6 = load <16 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 8
# |   store <4 x float> %8, ptr %__ret, align 8
# |   %9 = load <4 x float>, ptr %__ret, align 8
# |   store <4 x float> %9, ptr %tmp, align 8
# |   %10 = load <4 x float>, ptr %tmp, align 8
# |   store <4 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %16, ptr %__ret_812, align 8
# |   %17 = load <4 x float>, ptr %__ret_812, align 8
# |   store <4 x float> %17, ptr %tmp2, align 8
# |   %18 = load <4 x float>, ptr %tmp2, align 8
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_814 = alloca <2 x float>, al
# | ...
# `---data was truncated (10240/54174) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005640c44a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640c44a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640c44a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe315733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe31578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe315733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe31571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640c443f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640c443f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640c4423f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640c40d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640c40d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe31571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe31571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe31571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640c40d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (1958 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598c1b0356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005598c1b00505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005598c1b03cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c46e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c46ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c46e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c46e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598c1a9923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005598c1a99086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005598c1a7df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005598c172d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005598c172ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5c46e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c46e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c46e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598c172cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (1959 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cdfcc956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cdfcc6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cdfcc9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ff7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ff74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ff7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ff7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cdfc5f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cdfc5f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cdfc43f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cdf8f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cdf8f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ff7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ff74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ff74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cdf8f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (1960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aaadafc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aaadaf9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aaadafccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc449449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4494a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc449449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc449431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aaada9223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aaada92086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aaada76f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aaad726166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aaad725e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc449432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4494330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4494330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aaad725d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (1961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d3e56b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d3e568505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d3e56bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff30f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff30f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff30f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff30f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d3e50123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d3e501086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d3e4e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d3e195166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d3e194e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff30f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff30f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff30f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d3e194d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (1962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i
# | ...
# `---data was truncated (10240/51295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9d3cd256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9d3ccf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9d3cd2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0df6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0df60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0df6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0df6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9d3c6823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f9d3c68086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f9d3c4cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f9d38fc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f9d38fbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0df6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0df60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0df60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9d38fbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/neon-extract.c (1963 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
# |   store <8 x i8> %vext, ptr %ref.tmp, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %4, ptr %__ret, align 8
# |   %5 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %5, ptr %tmp, align 8
# |   %6 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   %5 = bitcast <8 x i8> %3 to <4 x i16>
# |   %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
# |   store <4 x i16> %vext, ptr %ref.tmp, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %6, ptr %__ret, align 8
# |   %7 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %7, ptr %tmp, align 8
# |   %8 = load <4 x i16>, ptr %tmp, align 8
# |   ret <4 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %__s1 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <2 x i32>
# |   %5 = bitcast <8 x i8> %3 to <2 x i32>
# |   %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i32> %vext, ptr %ref.tmp, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %6, ptr %__ret, align 8
# |   %7 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %7, ptr %tmp, align 8
# |   %8 = load <2 x i32>, ptr %tmp, align 8
# |   ret <2 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer
# |   store <1 x i64> %vext, ptr %ref.tmp, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %6, ptr %__ret, align 8
# |   %7 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %7, ptr %tmp, align 8
# |   %8 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca <16 x i8>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
# |   store <16 x i8> %vext, ptr %ref.tmp, align 16
# |   %4 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %4, ptr %__ret, align 16
# |   %5 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %5, ptr %tmp, align 16
# |   %6 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x i16>
# |   %5 = bitcast <16 x i8> %3 to <8 x i16>
# |   %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
# |   store <8 x i16> %vext, ptr %ref.tmp, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %6, ptr %__ret, align 16
# |   %7 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %7, ptr %tmp, align 16
# |   %8 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <4 x i32>
# |   %5 = bitcast <16 x i8> %3 to <4 x i32>
# |   %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
# |   store <4 x i32> %vext, ptr %ref.tmp, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %6, ptr %__ret, align 16
# |   %7 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %7, ptr %tmp, align 16
# |   %8 = load <4 x i32>, ptr %tmp, align 16
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i64> %vext, ptr %ref.tmp, align 16
# |   %6 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %6, ptr %__ret, align 16
# |   %7 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %7, ptr %tmp, align 16
# |   %8 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8>
# | ...
# `---data was truncated (10240/29598) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000555dadfe856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555dadfe5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555dadfe8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb59241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5924725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb59241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb592403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dadf7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555dadf7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555dadf62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555dadc12166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555dadc11e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb592404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5924050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5924050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dadc11d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (1964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcb0d2556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bcb0d22505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bcb0d25cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42a4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42a478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42a4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42a471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcb0cbb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bcb0cbb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bcb0c9ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bcb094f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bcb094ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42a471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42a471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42a471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcb094ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (1965 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eb1f3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561eb1f2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561eb1f31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6afba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6afbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6afba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6afba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eb1ec723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561eb1ec7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561eb1eabf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561eb1b5b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561eb1b5ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6afba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6afba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6afba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eb1b5ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (1966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/70971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3dfc4856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c3dfc45505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c3dfc48cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63c5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63c58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63c5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63c5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3dfbde23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3dfbde086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3dfbc2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c3df872166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c3df871e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f63c5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63c58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63c58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3df871d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (1967 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597bff6756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005597bff64505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005597bff67cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1e0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1e0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1e0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1e0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597bfefd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005597bfefd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005597bfee1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005597bfb91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005597bfb90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb1e0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1e0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1e0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597bfb90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (1968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055565f0e256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055565f0df505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055565f0e2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25e4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25e4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25e4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25e4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055565f07823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055565f078086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055565f05cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055565ed0c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055565ed0be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f25e4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25e4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25e4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055565ed0bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (1969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559eea40e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559eea40b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559eea40ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68fc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68fc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68fc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68fc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559eea3a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559eea3a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559eea388f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559eea038166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559eea037e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f68fc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68fc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68fc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559eea037d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (1970 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f108dff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f108dfc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f108dffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a5d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a5d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a5d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a5d2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f108d9523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f108d95086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f108d79f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f108a29166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f108a28e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7a5d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a5d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a5d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f108a28d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (1971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x bfloa
# | ...
# `---data was truncated (10240/12528) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056539469256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056539468f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565394692cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa92ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa92ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa92ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa92ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056539462823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565394628086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056539460cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653942bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653942bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa92ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa92ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa92ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653942bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (1972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e18a4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563e18a4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563e18a4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab38649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab386a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab38649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab38631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e189e523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563e189e5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563e189c9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563e18679166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563e18678e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab38632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab386330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab386330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e18678d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (1973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559354cf156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559354cee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559354cf1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66b1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66b1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66b1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66b1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559354c8723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559354c87086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559354c6bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055935491b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055935491ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f66b1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66b1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66b1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055935491ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (1974 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i)
# |   store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i)
# |   store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane)
# |   store <4 x float> %vdot2, ptr %ref.tmp, align 16
# |   %7 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %7, ptr %__ret, align 16
# |   %8 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %8, ptr %tmp, align 16
# |   %9 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aa
# | ...
# `---data was truncated (10240/11256) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055a75a54156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a75a53e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a75a541cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2d6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2d68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2d6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2d6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a75a4d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a75a4d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a75a4bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a75a16b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a75a16ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc2d6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2d68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2d68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a75a16ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (1975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561ce1f556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561ce1f2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561ce1f5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7535933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f753598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7535933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f753591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561ce18b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561ce18b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561ce16ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005561cde1f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005561cde1ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f753591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f753591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f753591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561cde1ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (1976 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f671c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f671c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f671c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb52b61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb52b6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb52b61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb52b603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f6715923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f67159086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f6713df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f66ded166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f66dece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb52b604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb52b6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb52b6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f66decd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (1977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056215768e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056215768b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056215768ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc88f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc88f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc88f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc88f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056215762423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562157624086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562157608f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005621572b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005621572b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc88f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc88f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc88f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621572b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (1978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eb766456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561eb7661505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561eb7664cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0eeb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0eeb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0eeb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0eeaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eb75fa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561eb75fa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561eb75def39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561eb728e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561eb728de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff0eeaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0eeaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0eeaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eb728dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (1979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x flo
# | ...
# `---data was truncated (10240/78024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056317404156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056317403e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563174041cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6887705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f688775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6887705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68876ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563173fd723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563173fd7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563173fbbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563173c6b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563173c6ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f68876eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68876ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68876ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563173c6ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (1980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b9a7df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b9a7dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b9a7dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f11649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f116a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f11649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f11631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b9a77523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b9a775086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b9a759f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b9a409166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b9a408e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f11632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f116330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f116330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b9a408d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (1981 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ed731056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ed730d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ed7310cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47cd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47cd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47cd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47cd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ed72a623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ed72a6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ed728af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ed6f3a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ed6f39e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47cd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47cd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47cd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ed6f39d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (1982 of 27911)
******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# |  #0 0x0000555b0387c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555b03879505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555b0387ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff94cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff94cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff94cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff94cc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b0381223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555b03812086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555b037f6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555b034a6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555b034a5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff94cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff94cc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff94cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b034a5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (1983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607bf21656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005607bf213505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005607bf216cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efde3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efde38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efde3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efde3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607bf1ac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005607bf1ac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005607bf190f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607bee40166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607bee3fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efde3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efde38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efde38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607bee3fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (1984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055886241b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558862418505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055886241bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8ed705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8ed75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8ed705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8ed6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588623b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005588623b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558862395f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558862045166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558862044e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff8ed6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8ed6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8ed6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558862044d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (1985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c301fdf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c301fdc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c301fdfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdddfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdddfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdddfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdddfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c301f7523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c301f75086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c301f59f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c301c09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c301c08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdddfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdddfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdddfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c301c08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (1986 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i8 @subscript_int8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i8 @subscript_uint8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i16 @subscript_int16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i16 @subscript_uint16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_int32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_uint32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 2 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 1 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double> %a.coerce, i64 0)
# |   store <4 x double> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x double>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005582f70ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005582f70a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005582f70accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa52849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa528a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa52849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa52831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582f704223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582f7042086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582f7026f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582f6cd6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582f6cd5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa52832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa528330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa528330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582f6cd5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (1987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/151253) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff5ce5056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ff5ce4d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ff5ce50cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2957533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f295758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2957533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f295751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff5cde623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ff5cde6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ff5cdcaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ff5ca7a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ff5ca79e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f295751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f295751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f295751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff5ca79d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (1988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a83788a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a837887505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a83788acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1589133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f158918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1589133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f158911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a83782023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a837820086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a837804f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a8374b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a8374b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f158911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f158911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f158911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8374b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (1989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558195aaf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558195aac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558195aafcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dd9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dd995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dd9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dd98ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558195a4523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558195a45086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558195a29f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581956d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581956d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5dd98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dd98ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dd98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581956d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (1990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f659dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f659da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f659ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ce5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ce5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ce5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ce5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f6597323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f65973086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f65957f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f65607166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f65606e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ce5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ce5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ce5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f65606d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (1991 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6e1a2856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6e1a25505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6e1a28cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f5a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f5a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f5a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f5a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6e19be23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6e19be086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6e19a2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6e1652166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6e1651e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f5a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f5a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f5a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6e1651d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (1992 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <v
# | ...
# `---data was truncated (10240/12083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce5475e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce5475b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce5475ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe2d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe2d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe2d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe2d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce546f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce546f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce546d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce54388166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce54387e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe2d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe2d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe2d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce54387d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (1993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b506ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562b506fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562b506ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb7b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb7b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb7b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb7b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b5069523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562b50695086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562b50679f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562b50329166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562b50328e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb7b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb7b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb7b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b50328d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (1994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557015e7b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557015e78505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557015e7bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75a3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75a36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75a3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75a3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557015e1123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557015e11086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557015df5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557015aa5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557015aa4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f75a3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75a36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75a36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557015aa4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (1995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc8823156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fc8822e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fc88231cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00e6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00e6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00e6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00e6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc881c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fc881c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fc881abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fc87e5b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fc87e5ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f00e6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00e6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00e6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc87e5ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (1996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639a72ba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639a72b7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639a72bacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f715021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71502725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f715021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7150203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639a725023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639a7250086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639a7234f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639a6ee4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639a6ee3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7150204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71502050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71502050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639a6ee3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (1997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056387232b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563872328505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056387232bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22acd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22acd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22acd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22acd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638722c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638722c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638722a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563871f55166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563871f54e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22acd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22acd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22acd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563871f54d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (1998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613c32bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613c32b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613c32bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0e3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0e3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0e3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0e3aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613c325223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613c3252086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613c3236f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613c2ee6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613c2ee5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa0e3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0e3aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0e3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613c2ee5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (1999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056467ecdb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056467ecd8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056467ecdbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f239ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f239ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f239ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f239ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056467ec7123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056467ec71086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056467ec55f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056467e905166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056467e904e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f239ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f239ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f239ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056467e904d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (2000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cbc38456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cbc381505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cbc384cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fc5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fc5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fc5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fc5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cbc31a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cbc31a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cbc2fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cbbfae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cbbfade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3fc5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fc5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fc5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cbbfadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (2001 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i
# | ...
# `---data was truncated (10240/41934) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f396f556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f396f2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f396f5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f722de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f722dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f722de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f722de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f3968b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f3968b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f3966ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f3931f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f3931ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f722de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f722de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f722de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f3931ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (2002 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/26976) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056253bd6456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056253bd61505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056253bd64cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9115c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9115ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9115c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9115c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056253bcfa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056253bcfa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056253bcdef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056253b98e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056253b98de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9115c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9115c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9115c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056253b98dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (2003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16
# | ...
# `---data was truncated (10240/93458) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056538899356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565388990505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565388993cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f3e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f3e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f3e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f3e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056538892923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565388929086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056538890df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653885bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653885bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1f3e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f3e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f3e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653885bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (2004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbbd1a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bbbd19d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bbbd1a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c21333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c2138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c21333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c2131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbbd13623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bbbd136086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bbbd11af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bbbcdca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bbbcdc9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c2131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c2131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c2131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbbcdc9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (2005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564254fde56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564254fdb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564254fdecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc63fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc63faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc63fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc63fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564254f7423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564254f74086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564254f58f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564254c08166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564254c07e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc63fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc63fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc63fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564254c07d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (2006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/18303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f757e4956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f757e46505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f757e49cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5823133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f582318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5823133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f582311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f757ddf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f757ddf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f757dc3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f757a73166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f757a72e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f582311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f582311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f582311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f757a72d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (2007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee1731456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee17311505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee17314cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4fd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4fd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4fd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4fd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee172aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee172aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee1728ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee16f3e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee16f3de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff4fd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4fd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4fd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee16f3dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (2008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbe0d8356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fbe0d80505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fbe0d83cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3408d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3408d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3408d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3408d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbe0d1923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fbe0d19086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fbe0cfdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fbe09ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fbe09ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3408d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3408d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3408d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbe09acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2009 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d2f10856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557d2f105505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557d2f108cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd99e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd99e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd99e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd99e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d2f09e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557d2f09e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557d2f082f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557d2ed32166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557d2ed31e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd99e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd99e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd99e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d2ed31d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (2010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cd197056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557cd196d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557cd1970cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33ddb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33ddb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33ddb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33ddb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cd190623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557cd1906086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557cd18eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557cd159a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557cd1599e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f33ddb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33ddb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33ddb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cd1599d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (2011 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, <vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, <vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/200802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563adf92056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563adf91d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563adf920cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7d7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7d7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7d7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7d7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563adf8b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563adf8b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563adf89af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563adf54a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563adf549e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe7d7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7d7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7d7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563adf549d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (2012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595b90c856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005595b90c5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005595b90c8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ec4f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ec4f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ec4f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ec4eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595b905e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005595b905e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005595b9042f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005595b8cf2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005595b8cf1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ec4eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ec4eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ec4eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595b8cf1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (2013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 
# | ...
# `---data was truncated (10240/97506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637fb2d956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637fb2d6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637fb2d9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe068a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe068aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe068a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe068a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637fb26f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005637fb26f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005637fb253f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005637faf03166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005637faf02e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe068a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe068a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe068a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637faf02d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (2014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625f0eea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625f0ee7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625f0eeacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2163649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21636a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2163649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2163631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625f0e8023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005625f0e80086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005625f0e64f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005625f0b14166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005625f0b13e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2163632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21636330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21636330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625f0b13d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (2015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636681df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636681dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636681dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f44849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f448a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f44849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f44831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056366817523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563668175086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563668159f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563667e09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563667e08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f44832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f448330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f448330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563667e08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (2016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055960917b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559609178505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055960917bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f616441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61644725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f616441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6164403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055960911123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559609111086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005596090f5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559608da5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559608da4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6164404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61644050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61644050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559608da4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (2017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f69150b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f691508505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f69150bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d00649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d006a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d00649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d00631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6914a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f6914a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f691485f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f691135166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f691134e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6d00632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d006330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d006330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f691134d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (2018 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f34eb7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f34eb74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f34eb77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff674333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff67438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff674333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff67431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f34eb0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f34eb0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f34eaf1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f34e7a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f34e7a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff67431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff67431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff67431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f34e7a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (2019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a92f8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a92f84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a92f87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24e6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24e638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24e6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24e631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a92f1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a92f1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a92f01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a92bb1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a92bb0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f24e631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24e631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24e631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a92bb0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (2020 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055570bb5c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055570bb59505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055570bb5ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7395733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f739578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7395733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f739571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055570baf223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055570baf2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055570bad6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055570b786166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055570b785e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f739571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f739571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f739571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055570b785d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (2021 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   
# | ...
# `---data was truncated (10240/135119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562656a0d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562656a0a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562656a0dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4ad533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4ad58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4ad533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4ad51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626569a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005626569a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562656987f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562656637166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562656636e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4ad51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4ad51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4ad51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562656636d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (2022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/151245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fc274256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560fc273f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560fc2742cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23e4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23e4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23e4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23e4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fc26d823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560fc26d8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560fc26bcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560fc236c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560fc236be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f23e4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23e4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23e4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fc236bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (2023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa1b28856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa1b285505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa1b288cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28d3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28d378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28d3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28d371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa1b21e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa1b21e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa1b202f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa1aeb2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa1aeb1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f28d371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28d371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28d371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa1aeb1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (2024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv
# | ...
# `---data was truncated (10240/165238) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c62a8456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c62a81505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c62a84cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f996ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f996ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f996ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f996ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c62a1a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c62a1a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c629fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c626ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c626ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f996ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f996ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f996ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c626add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (2025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556aac88056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556aac87d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556aac880cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c29533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c2958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c29533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c2951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556aac81623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556aac816086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556aac7faf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556aac4aa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556aac4a9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c2951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c2951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c2951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556aac4a9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (2026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dead9eb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dead9e8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dead9ebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7805d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7805d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7805d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7805d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dead98123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dead981086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dead965f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dead615166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dead614e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7805d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7805d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7805d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dead614d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (2027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565521be756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565521be4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565521be7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b09f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b09f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b09f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b09f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565521b7d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565521b7d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565521b61f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565521811166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565521810e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5b09f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b09f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b09f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565521810d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (2028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562c6d6e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562c6d6b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562c6d6ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4c3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4c338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4c3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4c331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562c6d0423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562c6d04086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562c6ce8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562c6998166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562c6997e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4c331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4c331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4c331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562c6997d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (2029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vtdiscard() #0 {
# | entry:
# |   call void @llvm.riscv.sf.vtdiscard()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtdiscard() #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d0cb8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d0cb84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d0cb87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea95333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea9538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea95333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea9531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d0cb1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d0cb1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d0cb01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d0c7b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d0c7b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fea9531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea9531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea9531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d0c7b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (2030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6a9e6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f6a9e6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f6a9e6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20c4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20c48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20c4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20c4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6a9e0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f6a9e03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f6a9de7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f6a9a97166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f6a9a96e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f20c4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20c48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20c48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6a9a96d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (2031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056388686b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563886868505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056388686bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4bd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4bd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4bd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4bd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056388680123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563886801086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638867e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563886495166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563886494e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff4bd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4bd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4bd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563886494d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (2032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594b7dbe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005594b7dbb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005594b7dbecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec45133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec4518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec45133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec4511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594b7d5423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594b7d54086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005594b7d38f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005594b79e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005594b79e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec4511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec4511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec4511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594b79e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (2033 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056546e3e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056546e3e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056546e3e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6528a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6528aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6528a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6528a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056546e37c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056546e37c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056546e360f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056546e010166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056546e00fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6528a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6528a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6528a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056546e00fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (2034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a21f2ab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a21f2a8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a21f2abcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb383449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb383449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb383431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a21f24123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a21f241086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a21f225f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a21eed5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a21eed4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb383432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3834330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a21eed4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (2035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea2b40056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea2b3fd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea2b400cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1834533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f183458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1834533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f183451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea2b39623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea2b396086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea2b37af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea2b02a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea2b029e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f183451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f183451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f183451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea2b029d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (2036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055890949456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558909491505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558909494cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7d2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7d238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7d2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7d231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055890942a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055890942a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055890940ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589090be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589090bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb7d231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7d231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7d231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589090bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (2037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vs
# | ...
# `---data was truncated (10240/32206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640385f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640385f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640385f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d3b61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d3b6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d3b61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d3b603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056403858d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056403858d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564038571f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564038221166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564038220e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d3b604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d3b6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d3b6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564038220d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (2038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x float> @add_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x float>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %b.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store <8 x float> %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load <8 x float>, ptr %b.addr, align 8
# |   %add = fadd <8 x float> %0, %1
# |   store <8 x float> %add, ptr %retval, align 8
# |   %2 = load <8 x float>, ptr %retval,
# | ...
# `---data was truncated (10240/145303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000556e0ba6c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556e0ba69505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556e0ba6ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f666ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f666eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f666ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f666ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e0ba0223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556e0ba02086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556e0b9e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556e0b696166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556e0b695e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f666ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f666ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f666ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e0b695d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (2039 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2af99356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d2af990505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d2af993cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83fde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83fdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83fde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83fde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2af92923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d2af929086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d2af90df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2af5bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2af5bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f83fde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83fde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83fde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2af5bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (2040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056517898256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056517897f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565178982cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd008333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd00838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd008333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd00831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056517891823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565178918086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651788fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005651785ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005651785abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd00831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd00831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd00831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651785abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (2041 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp sge <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp uge <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp sge <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f6455456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563f64551505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563f64554cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e62133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e6218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e62133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e6211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f644ea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563f644ea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563f644cef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563f6417e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563f6417de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5e6211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e6211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e6211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f6417dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (2042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570a51db56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005570a51d8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005570a51dbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2457533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f245758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2457533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f245751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570a517123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570a5171086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570a5155f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570a4e05166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570a4e04e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f245751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f245751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f245751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570a4e04d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (2043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650673f856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005650673f5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005650673f8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe357f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe357f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe357f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe357f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056506738e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056506738e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565067372f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565067022166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565067021e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe357f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe357f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe357f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565067021d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (2044 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae5e04356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae5e040505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae5e043cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ac401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ac40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ac401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ac4003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae5dfd923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae5dfd9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae5dfbdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae5dc6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae5dc6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ac4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ac40050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ac40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae5dc6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (2045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d70cceb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d70cce8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d70ccebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e74449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e744a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e74449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e74431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d70cc8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d70cc81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d70cc65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d70c915166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d70c914e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9e74432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e744330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e744330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d70c914d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (2046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   s
# | ...
# `---data was truncated (10240/69534) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557946e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005557946e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005557946e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2249649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22496a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2249649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2249631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055579467a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055579467a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055579465ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055579430e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055579430de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2249632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22496330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22496330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055579430dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (2047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e1004c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e10049505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e1004ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04fe21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04fe2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04fe21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04fe203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e0ffe223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e0ffe2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e0ffc6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e0fc76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e0fc75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f04fe204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04fe2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04fe2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e0fc75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (2048 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %
# | ...
# `---data was truncated (10240/11173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b3d37d356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b3d37d0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b3d37d3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7db2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7db258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7db2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7db251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3d376923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b3d3769086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b3d374df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b3d33fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b3d33fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7db251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7db251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7db251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3d33fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (2049 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 
# | ...
# `---data was truncated (10240/28683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a5b1f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a5b1f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a5b1f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1afb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1afb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1afb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1afb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a5b18d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a5b18d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a5b171f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a5ae21166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a5ae20e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1afb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1afb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1afb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a5ae20d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (2050 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vr
# | ...
# `---data was truncated (10240/96265) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598e878356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005598e8780505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005598e8783cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f934ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f934aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f934ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f934ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598e871923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005598e8719086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005598e86fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005598e83ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005598e83ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f934ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f934ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f934ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598e83acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (2051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599c3a3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005599c3a2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005599c3a31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8073649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80736a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8073649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8073631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599c39c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599c39c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005599c39abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005599c365b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005599c365ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8073632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80736330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80736330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599c365ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (2052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632f0efa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005632f0ef7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005632f0efacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd616049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd616049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd616031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632f0e9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005632f0e90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005632f0e74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005632f0b24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005632f0b23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd616032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6160330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632f0b23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (2053 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a78dbd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a78dba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a78dbdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcea8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcea84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcea8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcea8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a78d5323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a78d53086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a78d37f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a789e7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a789e6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcea8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcea84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcea84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a789e6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (2054 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/41094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5dbd3056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e5dbd2d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e5dbd30cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7745249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77452a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7745249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7745231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5dbcc623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e5dbcc6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e5dbcaaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e5db95a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e5db959e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7745232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77452330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77452330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5db959d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (2055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %o
# | ...
# `---data was truncated (10240/65883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4fbe6556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4fbe62505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4fbe65cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b04333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b0438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b04333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b0431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4fbdfb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4fbdfb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4fbddff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4fba8f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4fba8ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0b0431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b0431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b0431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4fba8ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (2056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed61cb756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed61cb4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed61cb7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c50049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c500a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c50049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c50031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed61c4d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed61c4d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed61c31f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed618e1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed618e0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c50032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c500330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c500330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed618e0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (2057 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, a
# | ...
# `---data was truncated (10240/13410) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bf18d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563bf18d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563bf18d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe08c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe08c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe08c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe08c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bf186e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563bf186e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563bf1852f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563bf1502166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563bf1501e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe08c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe08c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe08c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bf1501d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (2058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556476caf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556476cac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556476cafcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0c6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0c678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0c6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0c671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556476c4523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556476c45086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556476c29f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005564768d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005564768d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff0c671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0c671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0c671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564768d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (2059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9e28af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9e28ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9e28afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f586b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f586b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f586b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f586b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9e284523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f9e2845086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f9e2829f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f9e24d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f9e24d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f586b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f586b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f586b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9e24d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (2060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055810d4c956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055810d4c6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055810d4c9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca07105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca0715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca07105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca070ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055810d45f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055810d45f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055810d443f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055810d0f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055810d0f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca070eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca070ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca070ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055810d0f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-neon-vld.c (2061 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float16x4x3_t, ptr %retval, align 8
# |   ret %struct.float16x4x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float16x4x4_t, ptr %retval, align 8
# |   ret %struct.float16x4x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float32x2x2_t, ptr %retval, align 8
# |   ret %struct.float32x2x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float32x2x3_t, ptr %retval, align 8
# |   ret %struct.float32x2x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float32x2x4_t, ptr %retval, align 8
# |   ret %struct.float32x2x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0)
# |   store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.poly16x4x2_t, ptr %retval, align 8
# |   ret %struct.poly16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16
# | ...
# `---data was truncated (10240/109928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a52297e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a52297b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a52297ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9066f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9066f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9066f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9066f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a52291423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a522914086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a5228f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a5225a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a5225a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9066f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9066f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9066f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5225a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (2062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) 
# | ...
# `---data was truncated (10240/68437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625fda2e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625fda2b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625fda2ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaf4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaf42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaf4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaf4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625fd9c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005625fd9c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005625fd9a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005625fd658166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005625fd657e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdaf4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaf42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaf42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625fd657d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (2063 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c19123456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c191231505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c191234cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f122f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f122f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f122f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f122f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1911ca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1911ca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1911aef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c190e5e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c190e5de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f122f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f122f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f122f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c190e5dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (2064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557df6ed456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557df6ed1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557df6ed4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bc0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bc0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bc0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bc0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557df6e6a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557df6e6a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557df6e4ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557df6afe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557df6afde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9bc0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bc0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bc0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557df6afdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (2065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d31965556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d319652505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d319655cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac3181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac318725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac3181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac31803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3195eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d3195eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d3195cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d31927f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d31927ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac31804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac318050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac318050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d31927ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (2066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561678af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561678ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561678afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f182e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f182e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f182e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f182e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055616784523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556167845086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556167829f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005561674d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005561674d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f182e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f182e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f182e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561674d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (2067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576d75af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576d75ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576d75afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7f0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7f0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7f0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7f0eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576d754523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576d7545086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576d7529f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576d71d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576d71d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa7f0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7f0eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7f0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576d71d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (2068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale 
# | ...
# `---data was truncated (10240/56179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055827519b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558275198505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055827519bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ed0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ed0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ed0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ed0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055827513123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558275131086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558275115f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558274dc5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558274dc4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ed0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ed0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ed0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558274dc4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (2069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633dc53356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633dc530505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633dc533cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb588f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb588f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb588f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb588f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633dc4c923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005633dc4c9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005633dc4adf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005633dc15d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005633dc15ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb588f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb588f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb588f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633dc15cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (2070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632ea8f856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005632ea8f5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005632ea8f8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8223449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82234a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8223449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8223431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632ea88e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005632ea88e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005632ea872f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005632ea522166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005632ea521e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8223432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82234330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82234330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632ea521d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (2071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/15203) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580519eb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005580519e8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005580519ebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dad849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dad8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dad849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dad831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055805198123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558051981086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558051965f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558051615166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558051614e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4dad832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dad8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dad8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558051614d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (2072 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b86d5456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558b86d51505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558b86d54cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6e9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6e9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6e9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6e9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b86cea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558b86cea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558b86ccef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558b8697e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558b8697de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe6e9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6e9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6e9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b8697dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0ada2756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d0ada24505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d0ada27cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7222533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f722258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7222533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f722251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0ad9bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d0ad9bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d0ad9a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d0ad651166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d0ad650e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f722251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f722251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f722251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0ad650d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (2074 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557826f6556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557826f62505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557826f65cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa218333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa21838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa218333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa21831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557826efb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557826efb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557826edff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557826b8f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557826b8ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa21831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa21831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa21831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557826b8ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (2075 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599ab77056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005599ab76d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005599ab770cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9acdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9acdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9acdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9acdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599ab70623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599ab706086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005599ab6eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005599ab39a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005599ab399e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9acdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9acdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9acdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599ab399d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (2076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559053f7356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559053f70505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559053f73cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa61b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa61b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa61b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa61b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559053f0923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559053f09086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559053eedf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559053b9d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559053b9ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa61b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa61b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa61b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559053b9cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (2077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575adb6356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005575adb60505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005575adb63cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaff51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575adaf923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005575adaf9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005575adaddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005575ad78d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005575ad78ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feaff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaff51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575ad78cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (2078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load p
# | ...
# `---data was truncated (10240/28353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056490171d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056490171a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056490171dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54fe933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54fe98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54fe933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54fe91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649016b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005649016b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564901697f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564901347166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564901346e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f54fe91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54fe91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54fe91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564901346d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (2079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055635ffe456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055635ffe1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055635ffe4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4e3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4e318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4e3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4e311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055635ff7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055635ff7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055635ff5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055635fc0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055635fc0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa4e311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4e311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4e311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055635fc0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (2080 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056494797256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056494796f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564947972cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f232ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f232cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f232ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f232ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056494790823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564947908086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005649478ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056494759c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056494759be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f232ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f232ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f232ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056494759bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (2081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557282ec256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557282ebf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557282ec2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69b6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69b6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69b6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69b6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557282e5823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557282e58086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557282e3cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557282aec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557282aebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f69b6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69b6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69b6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557282aebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (2082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fddb1ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fddb1a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fddb1accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e7c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e7c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e7c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e7c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fddb14223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fddb142086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fddb126f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fddadd6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fddadd5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e7c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e7c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e7c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fddadd5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (2083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8d918956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a8d9186505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a8d9189cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f836d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f836d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f836d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f836d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8d911f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a8d911f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a8d9103f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a8d8db3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a8d8db2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f836d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f836d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f836d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8d8db2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (2084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642c1e8f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005642c1e8c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005642c1e8fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32f6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32f6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32f6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32f6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642c1e2523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005642c1e25086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005642c1e09f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005642c1ab9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005642c1ab8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f32f6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32f6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32f6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642c1ab8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (2085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ebee2356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ebee20505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ebee23cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cc9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cc998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cc9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cc991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ebedb923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ebedb9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ebed9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ebea4d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ebea4ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1cc991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cc991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cc991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ebea4cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (2086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055632f76d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055632f76a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055632f76dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b0b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b0b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b0b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b0b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055632f70323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055632f703086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055632f6e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055632f397166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055632f396e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0b0b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b0b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b0b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055632f396d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (2087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6f8f0956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e6f8f06505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e6f8f09cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdeb3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdeb3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdeb3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdeb3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6f8e9f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e6f8e9f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e6f8e83f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e6f8b33166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e6f8b32e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdeb3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdeb3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdeb3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6f8b32d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (2088 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558283ffd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558283ffa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558283ffdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6613d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6613d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6613d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6613ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558283f9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558283f93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558283f77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558283c27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558283c26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6613ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6613cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6613cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558283c26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (2089 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# |  #0 0x0000563cbc19056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563cbc18d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563cbc190cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8377049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83770a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8377049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8377031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cbc12623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563cbc126086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563cbc10af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563cbbdba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563cbbdb9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8377032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83770330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83770330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cbbdb9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (2090 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601fc3ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005601fc3fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601fc3ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa4721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa472725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa4721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa47203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601fc39523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005601fc395086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005601fc379f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601fc029166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601fc028e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa47204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa472050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa472050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601fc028d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (2091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare 
# | ...
# `---data was truncated (10240/20139) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625689dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625689d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625689dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe6e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe6e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe6e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe6e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056256897223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562568972086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562568956f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562568606166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562568605e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe6e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe6e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe6e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562568605d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (2092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7ab68b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f7ab688505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f7ab68bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa99d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa99d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa99d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa99d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7ab62123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f7ab621086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f7ab605f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7ab2b5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7ab2b4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa99d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa99d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa99d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7ab2b4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (2093 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de06d1b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de06d18505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de06d1bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fe6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fe68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fe6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fe6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de06cb123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de06cb1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de06c95f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de06945166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de06944e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4fe6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fe68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fe68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de06944d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (2094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> po
# | ...
# `---data was truncated (10240/50898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2e53e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2e53e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2e53e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a8ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a8aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a8ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a8ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2e537b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2e537b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2e535ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2e500f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2e500ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4a8ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a8ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a8ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2e500ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (2095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp sle i32 %2, %3
# |   %sle.i = zext i1 %4 to i32
# |   ret i32 %sle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp ule i32 %2, %3
# |   %sleu.i = zext i1 %4 to i32
# |   ret i32 %sleu.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = sext i16 %1 to i32
# |   %exths.i = sext i16 %1 to i32
# |   ret i32 %exths.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = zext i16 %1 to i32
# |   %exthz.i = zext i16 %1 to i32
# |   ret i32 %exthz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = sext i8 %1 to i32
# |   %extbs.i = sext i8 %1 to i32
# |   ret i32 %extbs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = zext i8 %1 to i32
# |   %extbz.i = zext i8 %1 to i32
# |   ret i32 %extbz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   st
# | ...
# `---data was truncated (10240/15696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7129bf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a7129bc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a7129bfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc2a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc2a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc2a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc2a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a71295523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a712955086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a712939f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a7125e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a7125e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc2a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc2a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc2a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7125e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (2096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056383b01756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056383b014505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056383b017cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4666049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4666049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4666031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056383afad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056383afad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056383af91f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056383ac41166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056383ac40e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4666032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46660330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056383ac40d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (2097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a507e4256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a507e3f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a507e42cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a2f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a2f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a2f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a2f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a507dd823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a507dd8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a507dbcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a507a6c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a507a6be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3a2f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a2f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a2f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a507a6bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (2098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587624ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587624eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587624eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd83201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8320725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd83201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd832003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055876248423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558762484086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558762468f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558762118166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558762117e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd832004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8320050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8320050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558762117d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (2099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align
# | ...
# `---data was truncated (10240/19041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572cd53956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005572cd536505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005572cd539cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f742a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f742a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f742a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f742a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572cd4cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005572cd4cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005572cd4b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005572cd163166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005572cd162e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f742a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f742a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f742a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572cd162d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (2100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056521386256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056521385f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565213862cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd80c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd80c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd80c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd80c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652137f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005652137f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005652137dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056521348c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056521348be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd80c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd80c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd80c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056521348bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (2101 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc    -triple aarch64 -target-feature +neon -target-feature +bf16    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0_824.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8
# |   store <4 x i16> %1, ptr %__s0.i, align 8
# |   %2 = load <8 x i8>, ptr %__s0.i, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   %4 = zext <4 x i16> %3 to <4 x i32>
# |   %vshll_n.i = shl <4 x i32> %4, splat (i32 16)
# |   store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16
# |   %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %6, ptr %tmp.i, align 16
# |   %7 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret_824.i, align 16
# |   %9 = load <4 x float>, ptr %__ret_824.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   store <4 x bfloat> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8
# |   store <4 x bfloat> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %4, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %inactive.addr = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <4 x float>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = fptrunc <4 x float> %6 to <4 x bfloat>
# |   %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %8, ptr %ref.tmp.i, align 16
# |   %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca bfloat, align 2
# |   %ref.tmp.i = alloca bfloat, align 2
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   store bfloat %2, ptr %ref.tmp.i, align 2
# |   %3 = load bfloat, ptr %ref.tmp.i, align 2
# |   store bfloat %3, ptr %__ret.i, align 2
# |   %4 = load bfloat, ptr %__ret.i, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load 
# | ...
# `---data was truncated (10240/10974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d572f4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d572f40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d572f43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff575133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff57518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff575133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff57511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d572ed923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d572ed9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d572ebdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d572b6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d572b6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff57511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff57511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff57511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d572b6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (2102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eeecdba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eeecdb7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eeecdbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb238049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2380a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb238049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb238031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eeecd5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eeecd50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eeecd34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eeec9e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eeec9e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb238032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2380330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2380330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eeec9e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (2103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055760ba9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055760ba99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055760ba9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd01333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd0138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd01333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd0131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055760ba3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055760ba32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055760ba16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055760b6c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055760b6c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd0131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd0131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd0131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055760b6c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (2104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613e2bdd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613e2bda505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613e2bddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f439361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43936725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f439361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4393603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613e2b7323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613e2b73086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613e2b57f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613e2807166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613e2806e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4393604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43936050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43936050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613e2806d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (2105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e33b3b256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e33b3af505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e33b3b2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9096733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f909678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9096733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f909671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e33b34823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e33b348086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e33b32cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e33afdc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e33afdbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f909671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f909671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f909671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e33afdbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (2106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f069cfe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f069cfb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f069cfecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f838ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f838ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f838ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f838ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f069c9423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f069c94086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f069c78f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f069928166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f069927e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f838ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f838ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f838ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f069927d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (2107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/427575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fc7ad256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564fc7acf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564fc7ad2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0763e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0763e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0763e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0763e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fc7a6823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564fc7a68086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564fc7a4cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564fc76fc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564fc76fbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0763e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0763e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0763e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fc76fbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (2108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec15b4856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ec15b45505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ec15b48cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2998333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f299838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2998333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f299831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec15ade23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ec15ade086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ec15ac2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ec15772166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ec15771e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f299831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f299831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f299831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec15771d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-cde-gpr.c (2109 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 {
# | entry:
# |   %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567)
# |   %1 = extractvalue { i32, i32 } %0, 1
# |   %2 = zext i32 %1 to i64
# |   %3 = shl i64 %2, 32
# |   %4 = extractvalue { i32, i32 } %0, 0
# |   %5 = zext i32 %4 to i64
# |   %6 = or i64 %3, %5
# |   ret i64 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33)
# |   %2 = extractvalue { i32, i32 } %1, 1
# |   %3 = zext i32 %2 to i64
# |   %4 = shl i64 %3, 32
# |   %5 = extractvalue { i32, i32 } %1, 0
# |   %6 = zext i32 %5 to i64
# |   %7 = or i64 %4, %6
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3)
# |   %3 = extractvalue { i32, i32 } %2, 1
# |   %4 = zext i32 %3 to i64
# |   %5 = shl i64 %4, 32
# |   %6 = extractvalue { i32, i32 } %2, 0
# |   %7 = zext i32 %6 to i64
# |   %8 = or i64 %5, %7
# |   ret i64 %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = load i32, ptr %m.addr, align 4
# |   %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d113d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d113d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d113d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd8cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd8cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd8cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd8cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d1136a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d1136a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d1134ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d10ffe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d10ffde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd8cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd8cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd8cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d10ffdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (2110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056158985c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561589859505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056158985ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9881333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f988138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9881333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f988131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615897f223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615897f2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615897d6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561589486166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561589485e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f988131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f988131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f988131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561589485d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (2111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2582ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a2582ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a2582aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8db7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8db778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8db7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8db771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a25824423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a258244086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a258228f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a257ed8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a257ed7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8db771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8db771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8db771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a257ed7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (2112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640d7e8b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640d7e88505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640d7e8bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6362c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6362ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6362c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6362c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640d7e2123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640d7e21086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640d7e05f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640d7ab5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640d7ab4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6362c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6362c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6362c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640d7ab4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (2113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f00e1fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f00e1f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f00e1facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb010249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0102a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb010249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb010231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f00e19023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f00e190086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f00e174f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f00de24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f00de23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb010232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0102330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0102330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f00de23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (2114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f3329f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f3329c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f3329fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9d8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9d84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9d8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9d8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f3323523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f33235086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f33219f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f32ec9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f32ec8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe9d8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9d84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9d84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f32ec8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (2115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c33e5a856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c33e5a5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c33e5a8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc53449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc534a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc53449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc53431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c33e53e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c33e53e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c33e522f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c33e1d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c33e1d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc53432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc534330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc534330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c33e1d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (2116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e95135856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e951355505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e951358cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faca3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faca3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faca3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faca3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9512ee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e9512ee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9512d2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e950f82166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e950f81e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faca3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faca3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faca3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e950f81d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (2117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055887098056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055887097d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558870980cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa83ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa83ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa83ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa83ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055887091623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558870916086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005588708faf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005588705aa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005588705a9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa83ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa83ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa83ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588705a9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (2118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d472b556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d472b2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d472b5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8662049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86620a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8662049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8662031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d4724b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d4724b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d4722ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d46edf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d46edee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8662032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86620330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86620330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d46eded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (2119 of 27911)
******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc |     not grep _foo2
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @bar() #0 {
# | entry:
# |   call void @foo2()
# |   ret void
# | }
# | 
# | declare void @foo2() #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# |  #0 0x0000555a84cda56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555a84cd7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555a84cdacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a99a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a99aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a99a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a99a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a84c7023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555a84c70086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555a84c54f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555a84904166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555a84903e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6a99a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a99a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a99a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a84903d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: llc
# executed command: not grep _foo2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (2120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056013d98656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056013d983505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056013d986cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc434133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc43418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc434133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc43411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056013d91c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056013d91c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056013d900f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056013d5b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056013d5afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc43411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc43411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc43411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056013d5afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (2121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653a5e8056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005653a5e7d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005653a5e80cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23f961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23f96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23f961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23f9603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653a5e1623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005653a5e16086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005653a5dfaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653a5aaa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653a5aa9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f23f9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23f96050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23f96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653a5aa9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (2122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f8f00c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563f8f009505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563f8f00ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc0ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc0ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc0ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc0ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f8efa223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563f8efa2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563f8ef86f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563f8ec36166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563f8ec35e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc0ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc0ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc0ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f8ec35d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (2123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb89a7456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb89a71505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb89a74cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb144d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb144d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb144d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb144d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb89a0a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb89a0a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb899eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb8969e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb8969de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb144d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb144d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb144d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb8969dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (2124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fa354c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558fa3549505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558fa354ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc549e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc549ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc549e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc549e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fa34e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558fa34e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558fa34c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558fa3176166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558fa3175e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc549e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc549e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc549e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fa3175d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (2125 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou
# | ...
# `---data was truncated (10240/28396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055fe6375e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fe6375b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fe6375ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3528b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3528b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3528b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3528b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe636f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fe636f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fe636d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fe63388166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fe63387e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3528b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3528b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3528b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe63387d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (2126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/32709) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c9b79a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c9b797505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c9b79acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8648449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86484a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8648449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8648431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c9b73023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c9b730086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c9b714f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c9b3c4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c9b3c3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8648432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86484330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86484330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c9b3c3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (2127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/39578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cac98456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558cac981505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558cac984cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f7b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f7b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f7b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f7b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cac91a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558cac91a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558cac8fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558cac5ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558cac5ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f7b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f7b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f7b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cac5add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (2128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638883a356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638883a0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638883a3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1b4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1b4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1b4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1b4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056388833923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563888339086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056388831df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563887fcd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563887fcce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa1b4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1b4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1b4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563887fccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (2129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606c48f556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606c48f2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606c48f5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff65dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff65dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff65dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff65dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606c488b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606c488b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606c486ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606c451f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606c451ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff65dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff65dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff65dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606c451ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (2130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f51d8c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f51d8c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f51d8c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72db049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72db0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72db049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72db031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f51d85b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f51d85b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f51d83ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f51d4ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f51d4eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72db032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72db0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72db0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f51d4eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (2131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e40b0eb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e40b0e8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e40b0ebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd88a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd88aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd88a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd88a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e40b08123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e40b081086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e40b065f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e40ad15166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e40ad14e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd88a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd88a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd88a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e40ad14d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (2132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d00629956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d006296505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d006299cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8265905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f826595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8265905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82658ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d00622f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d00622f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d006213f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d005ec3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d005ec2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82658eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82658ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82658ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d005ec2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (2133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d8ab4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d8ab40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d8ab43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04fd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d8aad923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d8aad9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d8aabdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d8a76d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d8a76ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f04fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04fd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d8a76cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (2134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define d
# | ...
# `---data was truncated (10240/25350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd4cb0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd4caff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd4cb02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ac7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ac775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ac7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ac76ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd4ca9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd4ca98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd4ca7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd4c72c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd4c72be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ac76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ac76ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ac76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd4c72bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (2135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f0948256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f0947f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f09482cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47a0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47a06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47a0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47a0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f0941823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f09418086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f093fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f090ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f090abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47a0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47a06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47a06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f090abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (2136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ca185456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563ca1851505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563ca1854cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bba61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bba6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bba61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bba603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ca17ea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563ca17ea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563ca17cef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563ca147e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563ca147de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7bba604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bba6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bba6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ca147dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (2137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b32da9d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b32da9a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b32da9dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b32da3323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b32da33086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b32da17f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b32d6c7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b32d6c6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42e6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b32d6c6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (2138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cfd1a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559cfd19f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559cfd1a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2f4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2f458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2f4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2f451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cfd13823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559cfd138086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559cfd11cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559cfcdcc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559cfcdcbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff2f451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2f451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2f451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cfcdcbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (2139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df0781856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055df07815505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055df07818cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6927133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f692718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6927133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f692711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df077ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055df077ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055df07792f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055df07442166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055df07441e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f692711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f692711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f692711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df07441d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (2140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %
# | ...
# `---data was truncated (10240/47698) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e28e0ca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e28e0c7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e28e0cacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9845a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9845aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9845a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9845a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e28e06023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e28e060086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e28e044f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e28dcf4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e28dcf3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9845a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9845a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9845a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e28dcf3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (2141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576ee15956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576ee156505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576ee159cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2750533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f275058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2750533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f275051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576ee0ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576ee0ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576ee0d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576edd83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576edd82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f275051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f275051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f275051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576edd82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (2142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4102fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c4102fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c4102fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bc4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bc48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bc4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bc4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c41029423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c410294086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c410278f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c40ff28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c40ff27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3bc4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bc48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bc48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c40ff27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (2143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, 
# | ...
# `---data was truncated (10240/288103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ad3fba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ad3fb7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ad3fbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb3841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb384725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb3841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb38403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ad3f5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ad3f50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ad3f34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ad3be4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ad3be3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb38404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb384050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb384050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ad3be3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (2144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb1456f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb1456c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb1456fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6c8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6c84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6c8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6c8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb1450523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb14505086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb144e9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb14199166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb14198e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa6c8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6c84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6c84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb14198d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (2145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf14a8b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf14a88505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf14a8bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f97133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f9718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f97133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f9711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf14a2123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf14a21086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf14a05f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf146b5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf146b4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4f9711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f9711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f9711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf146b4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (2146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd4a40b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd4a408505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd4a40bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4da049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4da0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4da049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4da031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd4a3a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd4a3a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd4a385f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd4a035166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd4a034e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc4da032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4da0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4da0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd4a034d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/builtin-align.c (2147 of 27911)
******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR    -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR    -enable-var-scope '-D$PTRTYPE=i8'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | @aligned_true = global i8 1, align 1
# | @aligned_false = global i8 0, align 1
# | @down_1 = global i32 992, align 4
# | @down_2 = global i32 256, align 4
# | @up_1 = global i32 1024, align 4
# | @up_2 = global i32 256, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @get_type() #0 {
# | entry:
# |   ret ptr null
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %src_addr = ptrtoint ptr %0 to i64
# |   %set_bits = and i64 %src_addr, %mask
# |   %is_aligned = icmp eq i64 %set_bits, 0
# |   ret i1 %is_aligned
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055f6ccb2e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f6ccb2b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f6ccb2ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9639905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f963995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9639905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96398ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6ccac423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f6ccac4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f6ccaa8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f6cc758166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f6cc757e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f96398eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96398ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96398ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6cc757d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (2148 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s0, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 
# | ...
# `---data was truncated (10240/18482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561fac25556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561fac252505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561fac255cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42bea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42beaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42bea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42bea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fac1eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561fac1eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561fac1cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561fabe7f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561fabe7ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42bea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42bea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42bea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fabe7ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (2149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x 
# | ...
# `---data was truncated (10240/12463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f0630156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f062fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f06301cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c25733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c2578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c25733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c2571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f0629723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f06297086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f0627bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f05f2b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f05f2ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c2571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c2571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c2571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f05f2ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (2150 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %value.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576)
# |   %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1
# |   store <2 x i64> %3, ptr %0, align 8
# |   %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = load <4 x i32>, ptr %value.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2)
# |   store <4 x i32> %3, ptr %0, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4
# | 
# | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576e2d6556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576e2d62505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576e2d65cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22a3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22a338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22a3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22a331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576e2cfb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576e2cfb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576e2cdff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576e298f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576e298ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22a331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22a331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22a331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576e298ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (2151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583e050356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005583e0500505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005583e0503cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feea7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feea798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feea7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feea791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583e049923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005583e0499086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005583e047df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005583e012d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005583e012ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feea791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feea791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feea791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583e012cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (2152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2e59ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2e59a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2e59accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a78133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a7818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a78133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a7811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2e594223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e2e5942086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e2e5926f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2e55d6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2e55d5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0a7811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a7811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a7811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2e55d5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (2153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2630c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c2630c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c2630c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3105449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31054a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3105449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3105431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c26305923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c263059086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c26303df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c262ced166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c262cece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3105432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31054330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31054330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c262cecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (2154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a421cc156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a421cbe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a421cc1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ee7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ee738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ee7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ee731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a421c5723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a421c57086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a421c3bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a4218eb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a4218eae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ee731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ee731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ee731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4218ead71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (2155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562f720156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562f71fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562f7201cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ff7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ff7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ff7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ff7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562f719723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562f7197086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562f717bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562f6e2b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562f6e2ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3ff7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ff7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ff7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562f6e2ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (2156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/26764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e27a73f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e27a73c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e27a73fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77bbf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77bbf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77bbf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77bbeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e27a6d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e27a6d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e27a6b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e27a369166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e27a368e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f77bbeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77bbeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77bbeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e27a368d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (2157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfee91d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfee91a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfee91dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e89c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e89ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e89c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e89c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfee8b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfee8b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfee897f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfee547166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfee546e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9e89c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e89c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e89c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfee546d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (2158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x
# | ...
# `---data was truncated (10240/58661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fe1aa556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557fe1aa2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557fe1aa5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f394eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f394eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f394eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f394eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fe1a3b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557fe1a3b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557fe1a1ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557fe16cf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557fe16cee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f394eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f394eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f394eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fe16ced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (2159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noin
# | ...
# `---data was truncated (10240/25042) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579fe12656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579fe123505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579fe126cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff57f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff57f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff57f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff57f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579fe0bc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579fe0bc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579fe0a0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579fdd50166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579fdd4fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff57f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff57f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff57f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579fdd4fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (2160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/65072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa1a87e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa1a87b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa1a87ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff586449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff586449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff586431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa1a81423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa1a814086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa1a7f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa1a4a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa1a4a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff586432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5864330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa1a4a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (2161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5865b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f5865b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f5865b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1259d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1259d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1259d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1259d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f58654c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f58654c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f586530f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5861e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5861dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1259d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1259d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1259d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5861dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (2162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f628d6756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f628d64505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f628d67cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f552af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f552af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f552af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f552aeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f628cfd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f628cfd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f628ce1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f628991166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f628990e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f552aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f552aeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f552aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f628990d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (2163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b5b54d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b5b54a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b5b54dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97ef849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97ef8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97ef849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97ef831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b5b4e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b5b4e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b5b4c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b5b177166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b5b176e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f97ef832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97ef8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97ef8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b5b176d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (2164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_v
# | ...
# `---data was truncated (10240/29273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653db17d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005653db17a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005653db17dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc3a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc3a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc3a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc3a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653db11323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005653db113086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005653db0f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653dada7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653dada6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc3a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc3a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc3a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653dada6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (2165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fae181356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fae1810505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fae1813cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8737d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8737d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8737d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8737d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fae17a923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fae17a9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fae178df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fae143d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fae143ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8737d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8737d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8737d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fae143cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (2166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579c99b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579c99b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579c99b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd956533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd95658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd956533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd95651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579c994c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579c994c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579c9930f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579c95e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579c95dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd95651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd95651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd95651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579c95dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (2167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0ed60856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f0ed605505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f0ed608cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a48b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a48b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a48b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a48b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0ed59e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0ed59e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0ed582f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f0ed232166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f0ed231e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3a48b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a48b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a48b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0ed231d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (2168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643eb7bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005643eb7b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005643eb7bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8224f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8224f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8224f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8224eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643eb75223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005643eb752086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005643eb736f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005643eb3e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005643eb3e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8224eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8224eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8224eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643eb3e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (2169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561544fd756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561544fd4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561544fd7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2f9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2f9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2f9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2f9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561544f6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561544f6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561544f51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561544c01166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561544c00e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd2f9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2f9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2f9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561544c00d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (2170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442042456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564420421505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564420424cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f817bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f817bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f817bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f817bced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644203ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005644203ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056442039ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056442004e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056442004de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f817bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f817bcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f817bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056442004dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (2171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055780321756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557803214505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557803217cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1886049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1886049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1886031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578031ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578031ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557803191f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557802e41166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557802e40e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1886032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18860330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557802e40d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (2172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/31868) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056344e35356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056344e350505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056344e353cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ad449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ad4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ad449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ad431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056344e2e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056344e2e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056344e2cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056344df7d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056344df7ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f18ad432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ad4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ad4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056344df7cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (2173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llv
# | ...
# `---data was truncated (10240/20513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c35fee356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c35fee0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c35fee3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcefb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcefb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcefb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcefb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c35fe7923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c35fe79086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c35fe5df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c35fb0d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c35fb0ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcefb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcefb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcefb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c35fb0cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (2174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8aa44656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8aa443505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8aa446cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa47c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa47ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa47c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa47c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8aa3dc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8aa3dc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8aa3c0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8aa070166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8aa06fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa47c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa47c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa47c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8aa06fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (2175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d687bd056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d687bcd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d687bd0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f719921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71992725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f719921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7199203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d687b6623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d687b66086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d687b4af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d6877fa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d6877f9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7199204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71992050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71992050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6877f9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (2176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c3856e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c3856b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c3856ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb28449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb284a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb28449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb28431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c3850423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c38504086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c384e8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c38198166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c38197e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb28432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb284330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb284330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c38197d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (2177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556eecd7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556eecd74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556eecd77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd18b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd18b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd18b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd18b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556eecd0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556eecd0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556eeccf1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556eec9a1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556eec9a0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd18b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd18b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd18b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eec9a0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (2178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642dd49756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005642dd494505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005642dd497cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc04733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc0478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc04733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc0471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642dd42d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005642dd42d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005642dd411f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005642dd0c1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005642dd0c0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc0471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc0471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc0471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642dd0c0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (2179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vs
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056414f32756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056414f324505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056414f327cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faabba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faabbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faabba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faabba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056414f2bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056414f2bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056414f2a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056414ef51166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056414ef50e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faabba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faabba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faabba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056414ef50d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (2180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056394f23456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056394f231505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056394f234cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f865ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f865ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f865ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f865ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056394f1ca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056394f1ca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056394f1aef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056394ee5e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056394ee5de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f865ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f865ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f865ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056394ee5dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (2181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562b09ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562b09ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562b09edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f44c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f44c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f44c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f44c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562b098323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562b0983086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562b0967f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562b0617166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562b0616e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f44c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f44c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f44c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562b0616d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (2182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x
# | ...
# `---data was truncated (10240/29267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de79ba456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de79ba1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de79ba4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a46933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a4698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a46933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a4691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de79b3a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de79b3a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de79b1ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de797ce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de797cde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a4691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a4691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a4691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de797cdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (2183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bcbb5056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555bcbb4d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555bcbb50cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ea7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ea74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ea7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ea7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bcbae623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555bcbae6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555bcbacaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555bcb77a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555bcb779e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ea7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ea74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ea74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bcb779d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (2184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056420c28856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056420c285505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056420c288cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc328c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc328ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc328c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc328c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056420c21e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056420c21e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056420c202f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056420beb2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056420beb1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc328c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc328c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc328c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056420beb1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (2185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, a
# | ...
# `---data was truncated (10240/29450) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f0ed9956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555f0ed96505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555f0ed99cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f477621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47762725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f477621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4776203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f0ed2f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555f0ed2f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555f0ed13f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555f0e9c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555f0e9c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4776204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47762050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47762050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f0e9c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (2186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %
# | ...
# `---data was truncated (10240/67150) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562456ae756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562456ae4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562456ae7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a48133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a4818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a48133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a4811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562456a7d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562456a7d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562456a61f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562456711166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562456710e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6a4811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a4811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a4811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562456710d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (2187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed4e80f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed4e80c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed4e80fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72f8a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72f8a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72f8a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72f8a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed4e7a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed4e7a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed4e789f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed4e439166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed4e438e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72f8a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72f8a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72f8a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed4e438d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (2188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564491dba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564491db7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564491dbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564491d5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564491d50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564491d34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005644919e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005644919e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87c5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644919e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (2189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2dd1a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c2dd1a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c2dd1a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe76449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe764a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe76449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe76431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2dd13a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c2dd13a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c2dd11ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c2dcdce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c2dcdcde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe76432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe764330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe764330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2dcdcdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (2190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5bc09e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5bc09b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5bc09ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3627e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3627e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3627e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3627e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5bc03423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5bc034086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5bc018f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5bbcc8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5bbcc7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3627e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3627e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3627e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5bbcc7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (2191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e25bc256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e25bbf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e25bc2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efee7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efee7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efee7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efee7e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e25b5823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e25b58086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e25b3cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e257ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e257ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efee7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efee7e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efee7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e257ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (2192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c25066256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c25065f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c250662cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74ce533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74ce58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74ce533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74ce51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2505f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c2505f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c2505dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c25028c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c25028be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f74ce51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74ce51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74ce51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c25028bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (2193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/116949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c5e0c056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557c5e0bd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557c5e0c0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8691933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f869198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8691933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f869191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c5e05623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557c5e056086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557c5e03af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557c5dcea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557c5dce9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f869191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f869191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f869191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c5dce9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (2194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650493a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005650493a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005650493a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7b9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7b9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7b9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7b9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056504933f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056504933f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565049323f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565048fd3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565048fd2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff7b9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7b9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7b9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565048fd2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (2195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe105f956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fe105f6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fe105f9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f489fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f489faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f489fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f489fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe1058f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fe1058f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fe10573f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fe10223166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fe10222e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f489fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f489fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f489fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe10222d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (2196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb6ed0756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb6ed04505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb6ed07cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d10e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d10ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d10e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d10e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb6ec9d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb6ec9d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb6ec81f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb6e931166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb6e930e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d10e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d10e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d10e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb6e930d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (2197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f11395056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f11394d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f113950cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1214f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1214f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1214f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1214f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1138e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f1138e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f1138caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f11357a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f113579e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1214f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1214f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1214f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f113579d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (2198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fbc9d956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559fbc9d6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559fbc9d9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ec3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ec3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ec3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ec3c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fbc96f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559fbc96f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559fbc953f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559fbc603166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559fbc602e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ec3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ec3c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ec3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fbc602d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (2199 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = sub <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fsub <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = sub <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fsub <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000556cbd80756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556cbd804505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556cbd807cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feba8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feba88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feba8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feba8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cbd79d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556cbd79d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556cbd781f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556cbd431166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556cbd430e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feba8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feba88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feba88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cbd430d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (2200 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c86a4d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c86a4a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c86a4dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a06449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a06449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a06431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c869e323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c869e3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c869c7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c86677166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c86676e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a06432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c86676d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (2201 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# |  #0 0x000056010e74756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056010e744505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056010e747cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cddc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cddca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cddc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cddc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056010e6dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056010e6dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056010e6c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056010e371166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056010e370e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3cddc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cddc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cddc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056010e370d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (2202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a88d6556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558a88d62505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558a88d65cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16d5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16d5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16d5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16d5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a88cfb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558a88cfb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558a88cdff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558a8898f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558a8898ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f16d5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16d5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16d5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a8898ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (2203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055766955c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557669559505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055766955ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f751c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f751c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f751c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f751c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576694f223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576694f2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576694d6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557669186166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557669185e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f751c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f751c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f751c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557669185d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (2204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bd73a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bd73a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bd73a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd557a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd557aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd557a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd557a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bd733a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bd733a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bd731ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bd6fce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bd6fcde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd557a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd557a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd557a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bd6fcdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (2205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563df5d7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563df5d72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563df5d75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f997ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f997ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f997ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f997ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563df5d0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563df5d0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563df5ceff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563df599f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563df599ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f997ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f997ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f997ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563df599ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (2206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056488ce2d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056488ce2a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056488ce2dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84c581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84c58725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84c581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84c5803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056488cdc323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056488cdc3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056488cda7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056488ca57166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056488ca56e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84c5804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84c58050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84c58050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056488ca56d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (2207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b685b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b685b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b685b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4110649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41106a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4110649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4110631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b6854a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b6854a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b6852ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b681de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b681dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4110632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41106330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41106330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b681ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (2208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e525a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e525a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e525a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc18ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc18ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc18ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc18ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e5253f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e5253f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e52523f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e521d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e521d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc18ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc18ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc18ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e521d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (2209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64
# | ...
# `---data was truncated (10240/32186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f965a556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f965a2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f965a5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82b7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82b7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82b7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82b7eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f9653b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f9653b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f9651ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f961cf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f961cee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82b7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82b7eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82b7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f961ced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (2210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/54488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566fd27456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005566fd271505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005566fd274cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba80649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba80649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba80631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566fd20a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005566fd20a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005566fd1eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005566fce9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005566fce9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fba80632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba806330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566fce9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (2211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4f6ffe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4f6ffb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4f6ffecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe3e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe3e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe3e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe3e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4f6f9423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4f6f94086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4f6f78f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4f6c28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4f6c27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe3e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe3e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe3e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4f6c27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (2212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582e98ca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005582e98c7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005582e98cacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0532649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05326a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0532649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0532631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582e986023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582e9860086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582e9844f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582e94f4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582e94f3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0532632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05326330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05326330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582e94f3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (2213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16
# | ...
# `---data was truncated (10240/33616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558937a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558937a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558937a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc642733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc64278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc642733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc64271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055589373f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055589373f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555893723f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558933d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558933d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc64271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc64271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc64271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558933d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (2214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055808cc9b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055808cc98505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055808cc9bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c4fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c4fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c4fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c4fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055808cc3123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055808cc31086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055808cc15f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055808c8c5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055808c8c4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c4fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c4fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c4fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055808c8c4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (2215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4010a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e40109f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4010a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd32d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd32d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd32d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd32d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e40103823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e401038086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e40101cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e400ccc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e400ccbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd32d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd32d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd32d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e400ccbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (2216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b154c4c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b154c49505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b154c4ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f335df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f335df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f335df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f335df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b154be223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b154be2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b154bc6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b154876166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b154875e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f335df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f335df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f335df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b154875d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (2217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c923a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c923a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c923a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe88a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe88a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe88a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe88a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c9233c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c9233c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c92320f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c91fd0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c91fcfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe88a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe88a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe88a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c91fcfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (2218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfe11ef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dfe11ec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dfe11efcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe188f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe188f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe188f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe188f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfe118523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dfe1185086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dfe1169f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dfe0e19166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dfe0e18e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe188f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe188f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe188f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfe0e18d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (2219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632d5fa356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005632d5fa0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005632d5fa3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47ca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47ca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47ca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47ca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632d5f3923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005632d5f39086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005632d5f1df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005632d5bcd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005632d5bcce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47ca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47ca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47ca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632d5bccd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (2220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d47835d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d47835a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d47835dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c71333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c7138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c71333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c7131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4782f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d4782f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d4782d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d477f87166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d477f86e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8c7131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c7131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c7131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d477f86d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (2221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559545c8356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559545c80505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559545c83cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f0ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f0ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f0ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f0aaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559545c1923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559545c19086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559545bfdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005595458ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005595458ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f0aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f0aaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f0aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595458acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (2222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056544778056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056544777d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565447780cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00c3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00c3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00c3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00c3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056544771623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565447716086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005654476faf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005654473aa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005654473a9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f00c3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00c3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00c3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654473a9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (2223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/66322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559ae21e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559ae21b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559ae21ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2da5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2da538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2da5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2da531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559ae1b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559ae1b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559ae198f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559ade48166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559ade47e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2da531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2da531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2da531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559ade47d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (2224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056415ea7156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056415ea6e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056415ea71cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63a1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63a138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63a1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63a131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056415ea0723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056415ea07086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056415e9ebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056415e69b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056415e69ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f63a131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63a131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63a131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056415e69ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/builtins-arm.c (2225 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-unknown-unknown-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @f0() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   %b.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load ptr, ptr %b.addr, align 4
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf0(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtr.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf1(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtru.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd0(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtr.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd1(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtru.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 0, ptr %res, align 4
# |   store volatile i32 1, ptr %res, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_barrier() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   call void @llvm.arm.dsb(i32 2)
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch(i32 noundef %i) #0 {
# | entry:
# |   %i.addr = alloca i32, align 4
# |   store i32 %i, ptr %i.addr, align 4
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp() #0 {
# | entry:
# |   call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp2() #0 {
# | entry:
# |   call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc2() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr2(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_lo
# | ...
# `---data was truncated (10240/15632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056488c97656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056488c973505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056488c976cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f878ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f878eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f878ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f878ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056488c90c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056488c90c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056488c8f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056488c5a0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056488c59fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f878ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f878ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f878ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056488c59fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (2226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f4f6de56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563f4f6db505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563f4f6decab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f32849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f328a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f32849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f32831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f4f67423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563f4f674086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563f4f658f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563f4f308166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563f4f307e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4f32832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f328330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f328330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f4f307d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (2227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d80d91856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d80d915505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d80d918cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cc0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cc04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cc0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cc0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d80d8ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d80d8ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d80d892f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d80d542166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d80d541e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7cc0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cc04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cc04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d80d541d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (2228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acec05b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055acec058505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055acec05bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f522e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f522e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f522e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f522e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acebff123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055acebff1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055acebfd5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055acebc85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055acebc84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f522e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f522e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f522e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acebc84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (2229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | ...
# `---data was truncated (10240/78234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055620391156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055620390e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556203911cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3856c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3856ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3856c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3856c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562038a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562038a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055620388bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055620353b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055620353ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3856c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3856c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3856c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055620353ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (2230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca
# | ...
# `---data was truncated (10240/12137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055626cf9d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055626cf9a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055626cf9dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d73d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d73d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d73d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d73d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055626cf3323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055626cf33086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055626cf17f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055626cbc7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055626cbc6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d73d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d73d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d73d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055626cbc6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (2231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565da0c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565da0c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565da0c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07eb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07eb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07eb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07eb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565da05923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565da059086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565da03df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565d9ced166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565d9cece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f07eb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07eb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07eb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565d9cecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (2232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v
# | ...
# `---data was truncated (10240/18520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce0b2e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce0b2de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce0b2e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa158533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa15858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa158533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa15851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce0b27723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce0b277086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce0b25bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce0af0b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce0af0ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa15851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa15851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa15851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce0af0ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (2233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cce6ec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559cce6e9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559cce6eccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4463533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f446358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4463533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f446351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cce68223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559cce682086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559cce666f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559cce316166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559cce315e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f446351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f446351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f446351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cce315d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (2234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a05247656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a052473505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a052476cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27c7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27c78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27c7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27c7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a05240c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a05240c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a0523f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a0520a0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a05209fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f27c7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27c78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27c78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a05209fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (2235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555782ce456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555782ce1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555782ce4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91ea933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91ea98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91ea933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91ea91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555782c7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555782c7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555782c5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055578290e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055578290de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f91ea91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91ea91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91ea91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055578290dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (2236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.
# | ...
# `---data was truncated (10240/17879) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056117f36256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056117f35f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056117f362cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce0c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce0c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce0c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce0c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056117f2f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056117f2f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056117f2dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056117ef8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056117ef8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce0c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce0c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce0c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056117ef8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (2237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/47706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056094082d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056094082a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056094082dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6673449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6673449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6673431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609407c323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005609407c3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005609407a7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560940457166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560940456e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6673432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66734330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560940456d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (2238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b26d8656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560b26d83505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560b26d86cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3e4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3e4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3e4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3e4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b26d1c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560b26d1c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560b26d00f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560b269b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560b269afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa3e4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3e4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3e4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b269afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (2239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstrid
# | ...
# `---data was truncated (10240/17118) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558b2fae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558b2fab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558b2faecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f594ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f594ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f594ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f594ba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558b2f4423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005558b2f44086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005558b2f28f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558b2bd8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558b2bd7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f594ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f594ba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f594ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558b2bd7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (2240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vsc
# | ...
# `---data was truncated (10240/41425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb1553056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb1552d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb15530cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6826449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6826449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6826431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb154c623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb154c6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb154aaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb1515a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb15159e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6826432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68264330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb15159d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (2241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619d488a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005619d4887505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005619d488acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe676649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6766a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe676649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe676631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619d482023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005619d4820086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005619d4804f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005619d44b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005619d44b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe676632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6766330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6766330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619d44b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (2242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605b267b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005605b2678505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005605b267bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f141b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f141b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f141b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f141b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605b261123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005605b2611086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005605b25f5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005605b22a5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005605b22a4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f141b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f141b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f141b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605b22a4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (2243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612421d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005612421d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005612421d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8827b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8827b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8827b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8827b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056124216e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056124216e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561242152f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561241e02166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561241e01e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8827b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8827b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8827b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561241e01d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (2244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b56c4c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b56c4c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b56c4c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd05b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd05b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd05b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd05b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b56c45b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b56c45b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b56c43ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b56c0ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b56c0eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd05b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd05b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd05b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b56c0eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (2245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv
# | ...
# `---data was truncated (10240/47720) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560077b2756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560077b24505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560077b27cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7032049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70320a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7032049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7032031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560077abd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560077abd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560077aa1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560077751166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560077750e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7032032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70320330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70320330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560077750d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (2246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595bfbdd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005595bfbda505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005595bfbddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08b2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08b2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08b2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08b2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595bfb7323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005595bfb73086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005595bfb57f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005595bf807166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005595bf806e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f08b2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08b2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08b2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595bf806d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (2247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055717b57b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055717b578505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055717b57bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48da133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48da18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48da133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48da11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055717b51123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055717b511086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055717b4f5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055717b1a5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055717b1a4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f48da11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48da11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48da11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055717b1a4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (2248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560407f4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560407f43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560407f46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0453049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04530a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0453049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0453031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560407edc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560407edc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560407ec0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560407b70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560407b6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0453032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04530330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04530330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560407b6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (2249 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = al
# | ...
# `---data was truncated (10240/40137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f78b9656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f78b93505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f78b96cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbff5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbff5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbff5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbff5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f78b2c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f78b2c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f78b10f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f787c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f787bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbff5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbff5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbff5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f787bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (2250 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e419f856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e419f5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e419f8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a70249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a702a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a70249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a70231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e4198e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e4198e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e41972f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e41622166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e41621e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a70232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a702330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a702330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e41621d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (2251 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df632fb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055df632f8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055df632fbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4173e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4173ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4173e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4173e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df6329123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055df63291086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055df63275f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055df62f25166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055df62f24e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4173e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4173e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4173e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df62f24d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (2252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c9060956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557c90606505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557c90609cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ca0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ca08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ca0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ca0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c9059f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557c9059f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557c90583f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557c90233166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557c90232e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ca0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ca08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ca08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c90232d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (2253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611567fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005611567f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005611567fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9c9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9c995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9c9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9c98ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056115679223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561156792086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561156776f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561156426166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561156425e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd9c98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9c98ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9c98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561156425d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (2254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055581037d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055581037a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055581037dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba3e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba3e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba3e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba3e803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055581031323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555810313086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005558102f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055580ffa7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055580ffa6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fba3e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba3e8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba3e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055580ffa6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (2255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/14338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3ed7a756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d3ed7a4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d3ed7a7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13b4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3ed73d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d3ed73d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d3ed721f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d3ed3d1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d3ed3d0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13b4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3ed3d0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (2256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f0b77556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f0b772505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f0b775cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb41249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb412a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb41249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb41231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f0b70b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f0b70b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f0b6eff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f0b39f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f0b39ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feb41232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb412330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb412330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f0b39ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (2257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de9211156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de9210e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de92111cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f450b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f450b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f450b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f450b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de920a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de920a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de9208bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de91d3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de91d3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f450b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f450b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f450b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de91d3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (2258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600ae3a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005600ae3a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005600ae3a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2102133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f210218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2102133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f210211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600ae33f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600ae33f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600ae323f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005600adfd3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005600adfd2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f210211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f210211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f210211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600adfd2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (2259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bf
# | ...
# `---data was truncated (10240/13040) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ece576856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ece5765505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ece5768cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc69849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc698a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc69849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc69831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ece56fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ece56fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ece56e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ece5392166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ece5391e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc69832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc698330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc698330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ece5391d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (2260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb6a05b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bb6a058505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bb6a05bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa89a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa89a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa89a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa89a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb69ff123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bb69ff1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bb69fd5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bb69c85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bb69c84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa89a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa89a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa89a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb69c84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (2261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5d109356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5d1090505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5d1093cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe922f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe922f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe922f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe922f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5d102923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5d1029086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5d100df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5d0cbd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5d0cbce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe922f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe922f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe922f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5d0cbcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (2262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056139242456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561392421505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561392424cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc094305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc09435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc094305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0942ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613923ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613923ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056139239ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056139204e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056139204de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc0942eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0942ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0942ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056139204dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (2263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2ec73f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c2ec73c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c2ec73fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1be5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1be578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1be5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1be571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2ec6d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c2ec6d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c2ec6b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c2ec369166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c2ec368e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1be571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1be571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1be571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2ec368d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (2264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrga
# | ...
# `---data was truncated (10240/28435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d2cd6156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d2cd5e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d2cd61cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fa4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fa48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fa4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fa4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d2ccf723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d2ccf7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d2ccdbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d2c98b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d2c98ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9fa4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fa48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fa48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d2c98ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (2265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0f69b056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f0f69ad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f0f69b0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb97505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb9755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb97505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb974ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0f694623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0f6946086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0f692af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f0f65da166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f0f65d9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb974eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb974ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb974ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0f65d9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (2266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563beb36156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563beb35e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563beb361cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa00ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa00cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa00ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa00ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563beb2f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563beb2f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563beb2dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563beaf8b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563beaf8ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa00ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa00ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa00ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563beaf8ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (2267 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561360e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561360e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561360e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5196f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5196f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5196f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5196f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055613607c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055613607c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556136060f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556135d10166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556135d0fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5196f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5196f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5196f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556135d0fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (2268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056022c98956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056022c986505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056022c989cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f035e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f035e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f035e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f035e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056022c91f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056022c91f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056022c903f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056022c5b3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056022c5b2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f035e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f035e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f035e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056022c5b2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (2269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf4cf5356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf4cf50505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf4cf53cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f982af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f982af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f982af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f982aeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf4cee923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf4cee9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf4cecdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf4cb7d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf4cb7ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f982aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f982aeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f982aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf4cb7cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm64-crc32.c (2270 of 27911)
******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32x(i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d97cfa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557d97cf7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557d97cfacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff1c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff1c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff1c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff1c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d97c9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557d97c90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557d97c74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557d97924166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557d97923e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff1c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff1c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff1c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d97923d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (2271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.a
# | ...
# `---data was truncated (10240/41678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646403ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646403aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646403adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f2c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f2c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f2c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f2c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056464034323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564640343086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564640327f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056463ffd7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056463ffd6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4f2c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f2c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f2c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056463ffd6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (2272 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i)
# |   store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i)
# |   store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i)
# |   store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i)
# |   store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i)
# |   store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i)
# |   store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i)
# |   store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i)
# |   store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i)
# |   store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i)
# |   store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i)
# |   store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i)
# |   st
# | ...
# `---data was truncated (10240/16770) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d79e76b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d79e768505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d79e76bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad44733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad4478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad44733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad4471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d79e70123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d79e701086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d79e6e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d79e395166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d79e394e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fad4471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad4471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad4471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d79e394d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (2273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"Sma
# | ...
# `---data was truncated (10240/10293) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f59dc256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f59dbf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f59dc2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a40a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a40aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a40a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a40a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f59d5823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f59d58086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f59d3cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f599ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f599ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0a40a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a40a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a40a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f599ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (2274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 =
# | ...
# `---data was truncated (10240/39218) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddd5d0456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ddd5d01505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ddd5d04cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa677c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa677ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa677c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa677c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddd5c9a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ddd5c9a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ddd5c7ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ddd592e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ddd592de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa677c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa677c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa677c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddd592dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (2275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e06f86456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e06f861505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e06f864cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd40333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd4038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd40333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd4031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e06f7fa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e06f7fa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e06f7def39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e06f48e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e06f48de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd4031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd4031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd4031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e06f48dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (2276 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf32fb456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bf32fb1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bf32fb4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e95333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e9538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e95333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e9531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf32f4a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bf32f4a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bf32f2ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bf32bde166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bf32bdde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e9531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e9531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e9531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf32bddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (2277 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = and <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = and <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = and <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = and <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr
# | ...
# `---data was truncated (10240/11060) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcca6d656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bcca6d3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bcca6d6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c62e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c62ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c62e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c62e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcca66c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bcca66c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bcca650f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bcca300166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bcca2ffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7c62e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c62e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c62e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcca2ffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (2278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdba59656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bdba593505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bdba596cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e06905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e0695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e06905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e068ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdba52c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bdba52c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bdba510f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bdba1c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bdba1bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e068eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e068ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e068ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdba1bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (2279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff8899556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ff88992505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ff88995cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f247a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f247a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f247a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f247a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff8892b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ff8892b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ff8890ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ff885bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ff885bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f247a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f247a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f247a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff885bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (2280 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616afc6556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005616afc62505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005616afc65cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa505533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa50558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa505533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa50551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616afbfb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005616afbfb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005616afbdff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005616af88f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005616af88ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa50551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa50551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa50551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616af88ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (2281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639bf7cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639bf7c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639bf7cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f663da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f663da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f663da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f663da03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639bf76223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639bf762086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639bf746f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639bf3f6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639bf3f5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f663da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f663da050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f663da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639bf3f5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (2282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571f8ed856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005571f8ed5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005571f8ed8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57cd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57cd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57cd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57cd803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571f8e6e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571f8e6e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571f8e52f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571f8b02166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571f8b01e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f57cd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57cd8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57cd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571f8b01d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (2283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <v
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae7c59256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae7c58f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae7c592cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d9f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d9f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d9f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d9f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae7c52823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae7c528086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae7c50cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae7c1bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae7c1bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d9f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d9f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d9f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae7c1bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (2284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594e80ca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005594e80c7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005594e80cacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bf3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bf315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bf3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bf30ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594e806023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594e8060086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005594e8044f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005594e7cf4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005594e7cf3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2bf30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bf30ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bf30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594e7cf3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (2285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056530279956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565302796505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565302799cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8bc905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8bc95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8bc905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8bc8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056530272f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056530272f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565302713f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653023c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653023c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe8bc8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8bc8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8bc8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653023c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (2286 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3)
# |   %5 = and <8 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3)
# |   %5 = and <4 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3)
# |   %5 = and <2 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3)
# |   %5 = and <16 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = xor i16 %0, -1
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = load <8 x half>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = load <4 x float>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <2 x i64>, ptr %a.addr, align 8
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   %5 = load <2 x i64>, ptr %b.addr, align 8
# |   %6 = bitcast <2 x i64> %5 to <4 x i32>
# |   %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6
# |   %8 = bitcast <4 x i32> %7 to <2 x i64>
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, ali
# | ...
# `---data was truncated (10240/13928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055f7d549b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f7d5498505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f7d549bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd52f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd52f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd52f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd52f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7d543123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f7d5431086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f7d5415f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7d50c5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7d50c4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd52f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd52f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd52f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7d50c4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (2287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c  -check-prefix=RV32ZKSED
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksed1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f68e9156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f68e8e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f68e91cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f398ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f398caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f398ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f398ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f68e2723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f68e27086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f68e0bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f68abb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f68abae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f398ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f398ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f398ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f68abad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (2288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d84e67256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d84e66f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d84e672cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa08f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa08f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa08f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa08f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d84e60823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d84e608086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d84e5ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d84e29c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d84e29be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa08f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa08f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa08f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d84e29bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (2289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654d33b556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005654d33b2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005654d33b5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0576a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0576aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0576a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0576a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654d334b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005654d334b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005654d332ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005654d2fdf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005654d2fdee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0576a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0576a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0576a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654d2fded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (2290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056213037d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056213037a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056213037dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73c8a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73c8a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73c8a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73c8a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056213031323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562130313086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005621302f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056212ffa7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056212ffa6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f73c8a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73c8a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73c8a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056212ffa6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (2291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055898012a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558980127505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055898012acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c67933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c6798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c67933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c6791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589800c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589800c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589800a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055897fd54166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055897fd53e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c6791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c6791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c6791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055897fd53d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (2292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558ed67956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558ed676505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558ed679cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52afe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52afe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52afe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52afe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558ed60f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005558ed60f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005558ed5f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558ed2a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558ed2a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f52afe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52afe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52afe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558ed2a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (2293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c1b3e956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c1b3e6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c1b3e9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe729e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe729ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe729e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe729e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c1b37f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c1b37f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c1b363f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c1b013166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c1b012e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe729e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe729e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe729e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c1b012d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (2294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056070e52d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056070e52a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056070e52dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1dcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1dcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1dcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1dcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056070e4c323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056070e4c3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056070e4a7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056070e157166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056070e156e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd1dcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1dcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1dcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056070e156d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (2295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558237f2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558237f29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558237f2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe875849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe875849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe875831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558237ec223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558237ec2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558237ea6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558237b56166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558237b55e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe875832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8758330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558237b55d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (2296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612d499056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005612d498d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005612d4990cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d4fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d4faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d4fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d4fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612d492623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005612d4926086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005612d490af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005612d45ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005612d45b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d4fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d4fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d4fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612d45b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (2297 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9a12f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b9a12f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b9a12f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92ceb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92ceb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92ceb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92ceaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9a128c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b9a128c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b9a1270f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9a0f20166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9a0f1fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f92ceaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92ceaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92ceaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9a0f1fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (2298 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056122b3c056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056122b3bd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056122b3c0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61a0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056122b35623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056122b356086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056122b33af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056122afea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056122afe9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61a08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056122afe9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (2299 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80)
# |   %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64)
# |   %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4)
# |   %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1
# |   store <2 x i64> %6, ptr %0, align 8
# |   %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559c830556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559c8302505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559c8305cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff316e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff316e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff316e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff316e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559c829b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559c829b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559c827ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559c7f2f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559c7f2ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff316e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff316e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff316e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559c7f2ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (2300 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557aec8d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557aec8d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557aec8d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd08f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd08f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd08f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd08f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557aec86b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557aec86b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557aec84ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557aec4ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557aec4fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd08f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd08f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd08f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557aec4fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (2301 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %ba
# | ...
# `---data was truncated (10240/24100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a83917356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a839170505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a839173cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34b3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34b338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34b3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34b331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a83910923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a839109086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a8390edf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a838d9d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a838d9ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f34b331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34b331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34b331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a838d9cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (2302 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da1824656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055da18243505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055da18246cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf66133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf6618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf66133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf6611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da181dc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055da181dc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055da181c0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055da17e70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055da17e6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbf6611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf6611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf6611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da17e6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (2303 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a89e26c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a89e269505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a89e26ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd367505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd36755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd367505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3674ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a89e20223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a89e202086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a89e1e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a89de96166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a89de95e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd3674eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3674ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3674ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a89de95d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2304 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055feac5d656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055feac5d3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055feac5d6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e10905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e1095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e10905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e108ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feac56c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055feac56c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055feac550f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055feac200166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055feac1ffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e108eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e108ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e108ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055feac1ffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (2305 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f69fda56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559f69fd7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559f69fdacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24be105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24be15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24be105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24be0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f69f7023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559f69f70086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559f69f54f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559f69c04166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559f69c03e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f24be0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24be0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24be0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f69c03d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (2306 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %
# | ...
# `---data was truncated (10240/291999) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cea3e4456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cea3e41505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cea3e44cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcee4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcee4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcee4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcee4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cea3dda23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cea3dda086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cea3dbef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cea3a6e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cea3a6de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcee4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcee4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcee4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cea3a6dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (2307 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %
# | ...
# `---data was truncated (10240/27994) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a3e37d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556a3e37a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556a3e37dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff35c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff35c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff35c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff35c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a3e31323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556a3e313086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556a3e2f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556a3dfa7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556a3dfa6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff35c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff35c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff35c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a3dfa6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (2308 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba6c1ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba6c1ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba6c1aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa202d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa202d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa202d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa202d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba6c14423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba6c144086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba6c128f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba6bdd8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba6bdd7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa202d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa202d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa202d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba6bdd7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (2309 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c2269256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c2268f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c22692cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa419f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa419f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa419f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa419f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c2262823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c22628086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c2260cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c222bc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c222bbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa419f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa419f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa419f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c222bbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (2310 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fffe01756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fffe014505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fffe017cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70bba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70bbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70bba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70bba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fffdfad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fffdfad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fffdf91f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fffdc41166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fffdc40e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f70bba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70bba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70bba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fffdc40d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (2311 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca targe
# | ...
# `---data was truncated (10240/53556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a8346356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558a83460505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558a83463cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bb3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bb3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bb3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bb3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a833f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558a833f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558a833ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558a8308d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558a8308ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3bb3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bb3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bb3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a8308cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (2312 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c3360b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c33608505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c3360bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f466f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f466f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f466f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f466f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c335a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c335a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c33585f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c33235166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c33234e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f466f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f466f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f466f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c33234d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (2313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ceaaa0756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ceaaa04505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ceaaa07cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6877333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f687738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6877333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f687731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ceaa99d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ceaa99d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ceaa981f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ceaa631166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ceaa630e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f687731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f687731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f687731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ceaa630d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (2314 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7ee28b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7ee288505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7ee28bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8564a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8564aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8564a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8564a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7ee22123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7ee221086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7ee205f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7edeb5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7edeb4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8564a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8564a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8564a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7edeb4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (2315 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/63177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e04fc856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e04fc5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e04fc8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16e8705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16e875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16e8705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16e86ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e04f5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e04f5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e04f42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e04bf2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e04bf1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f16e86eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16e86ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16e86ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e04bf1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (2316 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# |  #0 0x00005561c8afd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561c8afa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561c8afdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd285333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd28538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd285333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd28531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561c8a9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561c8a93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561c8a77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005561c8727166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005561c8726e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd28531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd28531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd28531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561c8726d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (2317 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579e804556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579e8042505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579e8045cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa5b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa5b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa5b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa5b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579e7fdb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579e7fdb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579e7fbff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579e7c6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579e7c6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa5b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa5b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa5b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579e7c6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (2318 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg)
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8f8c7e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f8f8c7b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f8f8c7ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe57a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe57a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe57a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe57a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8f8c1423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f8f8c14086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f8f8bf8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f8f88a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f8f88a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe57a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe57a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe57a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8f88a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (2319 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb7ebc456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb7ebc1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb7ebc4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71fe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71fe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71fe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71fe831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb7eb5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb7eb5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb7eb3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb7e7ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb7e7ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f71fe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71fe8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71fe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb7e7edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (2320 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603748f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603748f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603748f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde02a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde02aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde02a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde02a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056037488923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560374889086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056037486df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056037451d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056037451ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde02a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde02a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde02a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056037451cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (2321 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055578acbc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055578acb9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055578acbccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a02a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a02aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a02a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a02a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055578ac5223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055578ac52086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055578ac36f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055578a8e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055578a8e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a02a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a02a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a02a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055578a8e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (2322 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557aa88456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005557aa881505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005557aa884cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd599f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd599f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd599f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd599eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557aa81a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005557aa81a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005557aa7fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005557aa4ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005557aa4ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd599eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd599eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd599eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557aa4add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (2323 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,102
# | ...
# `---data was truncated (10240/10769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f05392956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f053926505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f053929cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57d7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57d7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57d7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57d7c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0538bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0538bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0538a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f053553166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f053552e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f57d7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57d7c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57d7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f053552d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (2324 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638f6dd356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638f6dd0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638f6dd3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa123449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1234a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa123449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa123431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638f6d6923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638f6d69086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638f6d4df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638f69fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638f69fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa123432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1234330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1234330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638f69fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (2325 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1698f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b1698f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b1698f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcee6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcee698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcee6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcee691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b16988d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b16988d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b169871f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b169521166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b169520e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcee691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcee691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcee691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b169520d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (2326 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, 
# | ...
# `---data was truncated (10240/62087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055840039a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558400397505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055840039acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f655be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f655bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f655be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f655be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055840033023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558400330086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558400314f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005583fffc4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005583fffc3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f655be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f655be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f655be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583fffc3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (2327 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564231e1856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564231e15505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564231e18cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48e0705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48e075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48e0705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48e06ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564231dae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564231dae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564231d92f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564231a42166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564231a41e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f48e06eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48e06ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48e06ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564231a41d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (2328 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e12c65b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e12c658505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e12c65bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbce2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbce2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbce2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbce2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e12c5f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e12c5f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e12c5d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e12c285166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e12c284e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbce2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbce2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbce2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e12c284d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (2329 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.
# | ...
# `---data was truncated (10240/15486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2b1a5e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2b1a5b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2b1a5ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3db3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3db34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3db3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3db3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2b19f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f2b19f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f2b19d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f2b1688166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f2b1687e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3db3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3db34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3db34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2b1687d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (2330 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056268222e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056268222b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056268222ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f358f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f358f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f358f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f358f4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626821c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005626821c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005626821a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562681e58166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562681e57e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f358f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f358f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f358f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562681e57d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (2331 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fb573756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557fb5734505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557fb5737cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f014aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f014aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f014aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f014aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fb56cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557fb56cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557fb56b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557fb5361166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557fb5360e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f014aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f014aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f014aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fb5360d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (2332 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dde8e4d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dde8e4a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dde8e4dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae3a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae3a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae3a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae3a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dde8de323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dde8de3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dde8dc7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dde8a77166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dde8a76e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae3a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae3a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae3a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dde8a76d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (2333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607da6af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005607da6ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005607da6afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a26d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a26d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a26d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a26d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607da64523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005607da645086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005607da629f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607da2d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607da2d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1a26d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a26d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a26d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607da2d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (2334 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da79f2456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055da79f21505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055da79f24cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd49b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd49b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd49b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd49b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da79eba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055da79eba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055da79e9ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055da79b4e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055da79b4de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd49b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd49b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd49b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da79b4dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (2335 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abd09b156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055abd09ae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055abd09b1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8995333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f899538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8995333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f899531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abd094723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055abd0947086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055abd092bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055abd05db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055abd05dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f899531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f899531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f899531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abd05dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (2336 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055daae4bf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055daae4bc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055daae4bfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ef8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ef838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ef8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ef831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daae45523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055daae455086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055daae439f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055daae0e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055daae0e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3ef831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ef831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ef831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daae0e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (2337 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056524e07456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056524e071505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056524e074cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f917fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f917fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f917fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f917fa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056524e00a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056524e00a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056524dfeef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056524dc9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056524dc9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f917fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f917fa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f917fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056524dc9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (2338 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8ea63156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a8ea62e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a8ea631cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8e7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8e7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8e7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8e7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8ea5c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a8ea5c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a8ea5abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a8ea25b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a8ea25ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb8e7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8e7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8e7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8ea25ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (2339 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c6ed2b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560c6ed28505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560c6ed2bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe46b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe46b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe46b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe46b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c6ecc123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560c6ecc1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560c6eca5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560c6e955166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560c6e954e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe46b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe46b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe46b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c6e954d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (2340 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x half>
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x float>
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 {
# | entry:
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 {
# | entry:
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000563fa17e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563fa17e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563fa17e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5843a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5843aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5843a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5843a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fa177c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563fa177c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563fa1760f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563fa1410166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563fa140fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5843a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5843a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5843a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fa140fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (2341 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.
# | ...
# `---data was truncated (10240/14900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cee3dbc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cee3db9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cee3dbccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7020e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7020ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7020e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7020e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cee3d5223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cee3d52086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cee3d36f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cee39e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cee39e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7020e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7020e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7020e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cee39e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (2342 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056127793956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561277936505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561277939cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bc6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bc6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bc6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bc6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612778cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005612778cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005612778b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561277563166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561277562e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4bc6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bc6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bc6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561277562d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (2343 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %5 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %5, ptr %__ret, align 8
# |   %6 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %6, ptr %tmp, align 8
# |   %7 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %9 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_39 = alloca <4 x half>, align 8
# |   %__s0_39 = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_39, align 8
# |   %1 = load <4 x half>, ptr %__s0_39, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_39, align 8
# |   %7 = load <4 x half>, ptr %__ret_39, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_20 = alloca <8 x half>, align 16
# |   %__s0_20 = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_20, align 8
# |   %1 = load <4 x half>, ptr %__s0_20, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_20, align 16
# |   %7 = load <8 x half>, ptr %__ret_20, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_432 = alloca <4 x half>, align 8
# |   %__s0_432 = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_432, align 16
# |   %1 = load <8 x half>, ptr %__s0_432, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_432, align 8
# |   %7 = load <4 x half>, ptr %__ret_432, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_408 = alloca <8 x half>, align 16
# |   %__s0_408 = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_408, align 16
# |   %1 = load <8 x half>, ptr %__s0_408, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_408, align 16
# |   %7 = load <8 x half>, ptr %__ret_408, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <4 x half>, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <4 x half> %vec, ptr %vec.addr, align 8
# |   %0 = load <4 x half>, ptr %vec.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x half> %1, i32 3
# |   store half %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <8 x half>, align 16
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <8 x half> %vec, ptr %vec.addr, align 16
# |   %0 = load <8 x half>, ptr %vec.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x half> %1, i32 7
# |   store half %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-s
# | ...
# `---data was truncated (10240/10414) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000563b6f86c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b6f869505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b6f86ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f570ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f570ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f570ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f570ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b6f80223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b6f802086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b6f7e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b6f496166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b6f495e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f570ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f570ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f570ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b6f495d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (2344 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a531ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a531a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a531accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ce2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ce295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ce2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ce28ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a5314223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a53142086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a53126f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a52dd6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a52dd5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ce28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ce28ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ce28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a52dd5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (2345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4825b256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4825af505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4825b2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2fbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2fbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2fbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2fbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f48254823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f482548086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f48252cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4821dc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4821dbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff2fbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2fbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2fbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4821dbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (2346 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9da25956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a9da256505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a9da259cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc07c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc07c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc07c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc07c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9da1ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a9da1ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a9da1d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a9d9e83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a9d9e82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc07c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc07c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc07c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9d9e82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (2347 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   
# | ...
# `---data was truncated (10240/13255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636527ec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636527e9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636527eccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdee0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdee0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdee0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdee0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056365278223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563652782086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563652766f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563652416166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563652415e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdee0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdee0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdee0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563652415d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (2348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056375b74056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056375b73d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056375b740cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb768e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb768ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb768e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb768e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056375b6d623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056375b6d6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056375b6baf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056375b36a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056375b369e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb768e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb768e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb768e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056375b369d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (2349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600a628556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005600a6282505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005600a6285cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3078f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3078f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3078f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3078f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600a621b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600a621b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600a61fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005600a5eaf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005600a5eaee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3078f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3078f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3078f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600a5eaed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (2350 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.add
# | ...
# `---data was truncated (10240/153913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1d0bbf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1d0bbc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1d0bbfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba99b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba99b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba99b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba99b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1d0b5523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1d0b55086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1d0b39f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1d07e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1d07e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fba99b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba99b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba99b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1d07e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (2351 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636f555156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005636f554e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005636f5551cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f420ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f420ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f420ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f420ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636f54e723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005636f54e7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005636f54cbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005636f517b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005636f517ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f420ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f420ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f420ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636f517ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (2352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561024cfd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561024cfa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561024cfdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15d4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15d478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15d4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15d471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561024c9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561024c93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561024c77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561024927166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561024926e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f15d471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15d471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15d471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561024926d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (2353 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocall
# | ...
# `---data was truncated (10240/12425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c075d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561c075d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561c075d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe88e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe88e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe88e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe88e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c0756e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561c0756e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561c07552f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561c07202166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561c07201e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe88e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe88e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe88e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c07201d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (2354 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055568587256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055568586f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555685872cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a6ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a6ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a6ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a6ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055568580823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555685808086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005556857ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055568549c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055568549be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a6ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a6ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a6ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055568549bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (2355 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055706474156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055706473e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557064741cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f994b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f994b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f994b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f994b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570646d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570646d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570646bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055706436b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055706436ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f994b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f994b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f994b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055706436ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (2356 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056125440356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561254400505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561254403cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd90c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd90c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd90c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd90c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056125439923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561254399086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056125437df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056125402d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056125402ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd90c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd90c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd90c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056125402cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (2357 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056055027056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056055026d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560550270cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd35333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd3538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd35333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd3531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056055020623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560550206086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005605501eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056054fe9a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056054fe99e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd3531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd3531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd3531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056054fe99d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (2358 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055771b85d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055771b85a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055771b85dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11f2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11f275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11f2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11f26ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055771b7f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055771b7f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055771b7d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055771b487166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055771b486e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f11f26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11f26ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11f26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055771b486d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (2359 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d5e9d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d5e9d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d5e9d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5c8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5c80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5c8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5c8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d5e96d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d5e96d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d5e951f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d5e601166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d5e600e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa5c8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5c80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5c80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d5e600d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (2360 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4fca1d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b4fca1a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b4fca1dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc02f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc02f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc02f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc02f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4fc9b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b4fc9b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b4fc997f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b4fc647166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b4fc646e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc02f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc02f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc02f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4fc646d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (2361 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d02250556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d022502505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d022505cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4280933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f428098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4280933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f428091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d02249b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d02249b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d02247ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d02212f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d02212ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f428091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f428091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f428091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d02212ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (2362 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618fa57d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005618fa57a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005618fa57dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3c1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3c1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3c1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3c1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618fa51323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005618fa513086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005618fa4f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005618fa1a7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005618fa1a6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff3c1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3c1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3c1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618fa1a6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (2363 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.v
# | ...
# `---data was truncated (10240/53192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bcb6ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561bcb6a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561bcb6accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e8bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e8bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e8bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e8bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bcb64223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561bcb642086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561bcb626f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561bcb2d6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561bcb2d5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e8bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e8bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e8bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bcb2d5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (2364 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/34589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e0579456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556e05791505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556e05794cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc154933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc15498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc154933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc15491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e0572a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556e0572a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556e0570ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556e053be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556e053bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc15491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc15491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc15491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e053bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (2365 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c328b356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c328b0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c328b3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5016f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5016f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5016f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5016f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c3284923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c32849086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c3282df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c324dd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c324dce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5016f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5016f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5016f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c324dcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (2366 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055827c72056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055827c71d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055827c720cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcf9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcf9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcf9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcf9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055827c6b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055827c6b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055827c69af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055827c34a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055827c349e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbcf9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcf9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcf9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055827c349d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (2367 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633e834c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633e8349505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633e834ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77f7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77f76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77f7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77f7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633e82e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005633e82e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005633e82c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005633e7f76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005633e7f75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f77f7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77f76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77f76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633e7f75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (2368 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0,
# | ...
# `---data was truncated (10240/29451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055703c0fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055703c0fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055703c0fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ace81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ace8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ace81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ace803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055703c09323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055703c093086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055703c077f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055703bd27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055703bd26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ace804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ace8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ace8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055703bd26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (2369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccf6c5f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccf6c5c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccf6c5fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0514333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f051438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0514333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f051431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccf6bf523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccf6bf5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccf6bd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ccf6889166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ccf6888e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f051431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f051431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f051431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccf6888d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (2370 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i
# | ...
# `---data was truncated (10240/14644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f47ca6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f47ca63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f47ca66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86fa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86fa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86fa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86fa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f47c9fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f47c9fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f47c9e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f47c690166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f47c68fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f86fa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86fa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86fa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f47c68fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (2371 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558744a0356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558744a00505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558744a03cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe00cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe00cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe00cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe00cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055874499923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558744999086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055874497df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055874462d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055874462ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe00cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe00cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe00cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055874462cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (2372 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056274e68156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056274e67e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056274e681cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9e9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9e9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9e9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9e9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056274e61723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056274e617086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056274e5fbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056274e2ab166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056274e2aae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9e9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9e9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9e9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056274e2aad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (2373 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056061334156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056061333e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560613341cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff28ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff28ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff28ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff28eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606132d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606132d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606132bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560612f6b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560612f6ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff28eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff28eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff28eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560612f6ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (2374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bae4e456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556bae4e1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556bae4e4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb60c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb60ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb60c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb60c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bae47a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556bae47a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556bae45ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556bae10e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556bae10de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb60c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb60c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb60c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bae10dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (2375 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562de7a2556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562de7a22505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562de7a25cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecc861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecc86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecc861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecc8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562de79bb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562de79bb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562de799ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562de764f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562de764ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fecc8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecc86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecc86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562de764ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (2376 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563771d2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563771d29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563771d2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93e5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93e578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93e5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93e571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563771cc223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563771cc2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563771ca6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563771956166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563771955e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f93e571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93e571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93e571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563771955d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-cde-vfp.c (2377 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 {
# | entry:
# |   %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)
# |   %1 = bitcast float %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = load i32, ptr %m.addr, align 4
# |   %5 = bitcast i32 %4 to float
# |   %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5)
# |   %7 = bitcast float %6 to i32
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 {
# | entry:
# |   %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)
# |   %1 = bitcast double %0 to i64
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %m.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = load i64, ptr %m.addr, align 8
# |   %5 = bitcast i64 %4 to double
# |   %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5)
# |   %7 = bitcast double %6 to i64
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccae8a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccae8a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccae8a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f993801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99380725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f993801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9938003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccae83a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccae83a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccae81ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ccae4ce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ccae4cde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9938004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99380050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99380050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccae4cdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (2378 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056041dcc956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056041dcc6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056041dcc9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f006e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f006e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f006e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f006e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056041dc5f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056041dc5f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056041dc43f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056041d8f3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056041d8f2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f006e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f006e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f006e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056041d8f2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (2379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564570f5d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564570f5a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564570f5dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63ad41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63ad4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63ad41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63ad403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564570ef323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564570ef3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564570ed7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564570b87166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564570b86e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f63ad404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63ad4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63ad4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564570b86d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (2380 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055644bc5d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055644bc5a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055644bc5dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5af133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5af18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5af133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5af11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055644bbf323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055644bbf3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055644bbd7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055644b887166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055644b886e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff5af11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5af11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5af11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055644b886d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (2381 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562104ce356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562104ce0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562104ce3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc8c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc8c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc8c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc8c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562104c7923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562104c79086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562104c5df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056210490d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056210490ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc8c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc8c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc8c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056210490cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (2382 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055865e9e256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055865e9df505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055865e9e2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdde6e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdde6e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdde6e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdde6e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055865e97823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055865e978086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055865e95cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055865e60c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055865e60be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdde6e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdde6e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdde6e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055865e60bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (2383 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1
# |   store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %5, ptr %__ret, align 16
# |   %6 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %6, ptr %tmp, align 16
# |   %7 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0
# |   store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %5, ptr %__ret, align 8
# |   %6 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %6, ptr %tmp, align 8
# |   %7 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca 
# | ...
# `---data was truncated (10240/14230) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005604b912456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005604b9121505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005604b9124cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabe1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabe1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabe1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabe1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604b90ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005604b90ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604b909ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005604b8d4e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005604b8d4de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fabe1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabe1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabe1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604b8d4dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (2384 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c2fb2156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559c2fb1e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559c2fb21cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f607b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f607b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f607b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f607b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c2fab723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559c2fab7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559c2fa9bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559c2f74b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559c2f74ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f607b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f607b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f607b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c2f74ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (2385 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc1450d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc1450a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc1450dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f691e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f691e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f691e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f691e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc144a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc144a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc14487f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc14137166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc14136e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f691e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f691e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f691e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc14136d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (2386 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6e1a5b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c6e1a58505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c6e1a5bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5a0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5a0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5a0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5a0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6e19f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c6e19f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c6e19d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c6e1685166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c6e1684e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd5a0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5a0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5a0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6e1684d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (2387 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5c441456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e5c4411505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e5c4414cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff377a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff377aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff377a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff377a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5c43aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e5c43aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e5c438ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e5c403e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e5c403de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff377a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff377a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff377a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5c403dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (2388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bff779056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bff778d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bff7790cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36f5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36f518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36f5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36f511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bff772623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bff7726086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bff770af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bff73ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bff73b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f36f511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36f511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36f511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bff73b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (2389 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, al
# | ...
# `---data was truncated (10240/92370) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622c19ec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005622c19e9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005622c19eccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f603d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f603d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f603d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f603d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622c198223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005622c1982086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005622c1966f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005622c1616166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005622c1615e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f603d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f603d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f603d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622c1615d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (2390 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055795474456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557954741505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557954744cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f239a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f239a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f239a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f239a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579546da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579546da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579546bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055795436e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055795436de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f239a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f239a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f239a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055795436dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (2391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.ris
# | ...
# `---data was truncated (10240/12914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7e46ba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f7e46b7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f7e46bacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bc8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bc80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bc8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bc8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7e465023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f7e4650086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f7e4634f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7e42e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7e42e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2bc8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bc80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bc80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7e42e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (2392 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055815eb3256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055815eb2f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055815eb32cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80ddd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80ddd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80ddd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80ddd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055815eac823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055815eac8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055815eaacf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055815e75c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055815e75be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80ddd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80ddd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80ddd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055815e75bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (2393 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e1135b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555e11358505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555e1135bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61a4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61a478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61a4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61a471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e112f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555e112f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555e112d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555e10f85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555e10f84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61a471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61a471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61a471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e10f84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (2394 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cc4df856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563cc4df5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563cc4df8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cd9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cd998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cd9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cd991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cc4d8e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563cc4d8e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563cc4d72f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563cc4a22166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563cc4a21e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3cd991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cd991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cd991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cc4a21d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (2395 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f841f6a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f841f67505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f841f6acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96eb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96eb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96eb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96eb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f841f0023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f841f00086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f841ee4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f841b94166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f841b93e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f96eb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96eb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96eb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f841b93d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (2396 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603d73ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603d73fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005603d73ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45db61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45db6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45db61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45db603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603d739523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005603d7395086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005603d7379f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005603d7029166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005603d7028e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f45db604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45db6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45db6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603d7028d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (2397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562031f1256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562031f0f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562031f12cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc60c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc60ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc60c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc60c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562031ea823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562031ea8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562031e8cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562031b3c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562031b3be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc60c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc60c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc60c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562031b3bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (2398 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d10d0d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d10d0d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d10d0d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e95505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e9555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e95505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e954ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d10d06e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d10d06e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d10d052f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d10cd02166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d10cd01e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e954eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e954ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e954ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d10cd01d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (2399 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffcd96956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ffcd966505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ffcd969cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f722a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f722a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f722a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f722a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffcd8ff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ffcd8ff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ffcd8e3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ffcd593166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ffcd592e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f722a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f722a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f722a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffcd592d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (2400 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056348c40a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056348c407505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056348c40acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7d1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7d1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7d1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7d1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056348c3a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056348c3a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056348c384f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056348c034166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056348c033e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7d1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7d1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7d1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056348c033d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (2401 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f667ab356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f667ab0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f667ab3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1264849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12648a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1264849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1264831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f667a4923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f667a49086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f667a2df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f6676dd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f6676dce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1264832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12648330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12648330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6676dcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (2402 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055576802056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055576801d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555768020cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74b921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74b92725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74b921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74b9203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555767fb623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555767fb6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555767f9af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555767c4a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555767c49e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f74b9204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74b92050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74b92050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555767c49d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (2403 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a53cca56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558a53cc7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558a53ccacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f327a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f327a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f327a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f327a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a53c6023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558a53c60086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558a53c44f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558a538f4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558a538f3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f327a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f327a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f327a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a538f3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (2404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c48cd356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c48cd0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c48cd3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbddc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbddc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbddc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbddc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c48c6923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c48c69086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c48c4df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c488fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c488fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbddc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbddc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbddc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c488fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (2405 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055566cf7f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055566cf7c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055566cf7fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f395f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f395f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f395f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f395f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055566cf1523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055566cf15086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055566cef9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055566cba9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055566cba8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f395f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f395f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f395f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055566cba8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (2406 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c20054a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c200547505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c20054acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2752649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27526a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2752649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2752631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2004e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c2004e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c2004c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c200174166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c200173e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2752632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27526330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27526330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c200173d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (2407 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b007ef256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b007eef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b007ef2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1ee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1ee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1ee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1ee71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b007e8823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b007e88086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b007e6cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b007b1c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b007b1be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa1ee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1ee71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1ee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b007b1bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (2408 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c0456556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560c04562505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560c04565cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f831101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83110725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f831101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8311003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c044fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560c044fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560c044dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560c0418f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560c0418ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8311004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83110050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83110050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c0418ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (2409 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbddcfd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cbddcfa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cbddcfdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3b7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3b798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3b7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3b791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbddc9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cbddc93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cbddc77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cbdd927166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cbdd926e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3b791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3b791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3b791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbdd926d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (2410 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz
# | ...
# `---data was truncated (10240/58675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab21c1a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab21c17505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab21c1acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd969e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd969ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd969e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd969e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab21bb023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab21bb0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab21b94f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab21844166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab21843e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd969e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd969e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd969e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab21843d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (2411 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b66029756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b660294505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b660297cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27b9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27b998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27b9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27b991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b66022d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b66022d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b660211f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b65fec1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b65fec0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f27b991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27b991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27b991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b65fec0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (2412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565118ae856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565118ae5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565118ae8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0098133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f009818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0098133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f009811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565118a7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565118a7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565118a62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565118712166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565118711e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f009811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f009811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f009811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565118711d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (2413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e1af1356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e1af10505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e1af13cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb29d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb29d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb29d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb29d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e1aea923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e1aea9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e1ae8df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e1ab3d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e1ab3ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb29d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb29d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb29d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e1ab3cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (2414 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba7a76356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba7a760505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba7a763cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f740ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f740ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f740ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f740ec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba7a6f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba7a6f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba7a6ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba7a38d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba7a38ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f740ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f740ec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f740ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba7a38cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (2415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056285083156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056285082e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562850831cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17bbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17bbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17bbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17bbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628507c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005628507c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005628507abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056285045b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056285045ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f17bbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17bbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17bbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056285045ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (2416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d23b6f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d23b6c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d23b6fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d63c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d63ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d63c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d63c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d23b0523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d23b05086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d23ae9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d23799166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d23798e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d63c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d63c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d63c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d23798d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (2417 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr 
# | ...
# `---data was truncated (10240/26240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3c869d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e3c869a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e3c869dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb38a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb38a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb38a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb38a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3c863323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e3c8633086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3c8617f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e3c82c7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e3c82c6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb38a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb38a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb38a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3c82c6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (2418 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2
# | ...
# `---data was truncated (10240/32570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3b8a8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f3b8a87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f3b8a8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb6cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb6cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb6cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb6cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3b8a2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f3b8a20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f3b8a04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f3b86b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f3b86b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb6cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb6cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb6cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3b86b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (2419 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b8a34856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b8a345505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b8a348cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc843249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8432a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc843249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc843231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b8a2de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b8a2de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b8a2c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b89f72166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b89f71e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc843232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8432330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8432330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b89f71d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (2420 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1e1b8256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b1e1b7f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b1e1b82cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd8e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd8e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd8e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd8e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1e1b1823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b1e1b18086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b1e1afcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b1e17ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b1e17abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd8e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd8e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd8e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1e17abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (2421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ca98bb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ca98b8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ca98bbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79b2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79b2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79b2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79b2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ca985123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ca9851086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ca9835f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ca94e5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ca94e4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f79b2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79b2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79b2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ca94e4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (2422 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x
# | ...
# `---data was truncated (10240/24328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5ad91b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5ad918505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5ad91bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca3ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca3caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca3ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca3ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5ad8b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5ad8b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5ad895f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5ad545166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5ad544e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca3ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca3ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca3ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5ad544d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (2423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c42196d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c42196a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c42196dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5c0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5c018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5c0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5c011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c42190323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c421903086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c4218e7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c421597166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c421596e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc5c011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5c011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5c011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c421596d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (2424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634d9e5f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005634d9e5c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005634d9e5fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba82c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba82ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba82c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba82c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634d9df523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005634d9df5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005634d9dd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005634d9a89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005634d9a88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fba82c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba82c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba82c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634d9a88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (2425 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055812909256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055812908f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558129092cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d1a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d1a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d1a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d1a803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055812902823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558129028086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055812900cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558128cbc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558128cbbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7d1a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d1a8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d1a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558128cbbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (2426 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d82737756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d827374505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d827377cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb07eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb07eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb07eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb07eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d82730d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d82730d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8272f1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d826fa1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d826fa0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb07eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb07eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb07eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d826fa0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (2427 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d831e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d831de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d831e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a39249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a392a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a39249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a39231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d8317723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d83177086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d8315bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d82e0b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d82e0ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9a39232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a392330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a392330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d82e0ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (2428 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1661dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d1661da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d1661ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5576133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f557618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5576133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f557611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d16617323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d166173086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d166157f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d165e07166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d165e06e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f557611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f557611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f557611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d165e06d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (2429 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576f5f9a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576f5f97505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576f5f9acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ff2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ff2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ff2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ff2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576f5f3023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576f5f30086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576f5f14f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576f5bc4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576f5bc3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ff2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ff2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ff2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576f5bc3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (2430 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# |  #0 0x0000562ba186856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ba1865505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ba1868cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee47049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee470a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee47049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee47031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ba17fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ba17fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ba17e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ba1492166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ba1491e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fee47032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee470330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee470330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ba1491d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (2431 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %v
# | ...
# `---data was truncated (10240/23064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d9ddb256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559d9ddaf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559d9ddb2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d64e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d64ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d64e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d64e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d9dd4823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559d9dd48086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559d9dd2cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559d9d9dc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559d9d9dbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d64e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d64e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d64e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d9d9dbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (2432 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a8c61a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557a8c617505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557a8c61acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50a0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50a0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50a0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50a0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a8c5b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557a8c5b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557a8c594f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557a8c244166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557a8c243e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f50a0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50a0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50a0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a8c243d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (2433 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0692eb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0692e8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0692ebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08ce533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08ce58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08ce533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08ce51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c06928123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c069281086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c069265f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c068f15166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c068f14e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f08ce51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08ce51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08ce51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c068f14d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (2434 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr
# | ...
# `---data was truncated (10240/14461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056134ecbf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056134ecbc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056134ecbfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02a4505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02a455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02a4505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02a44ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056134ec5523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056134ec55086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056134ec39f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056134e8e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056134e8e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f02a44eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02a44ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02a44ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056134e8e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (2435 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a39863456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a398631505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a398634cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f722a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f722a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f722a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f722a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3985ca23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a3985ca086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a3985aef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a39825e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a39825de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f722a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f722a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f722a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a39825dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (2436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @ll
# | ...
# `---data was truncated (10240/20090) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b7a2c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b7a2c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b7a2c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec87733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec8778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec87733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec8771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b7a25b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b7a25b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b7a23ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b79eef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b79eeee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec8771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec8771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec8771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b79eeed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (2437 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load ptr, ptr %carry.addr, align 4
# |   %4 = load i32, ptr %3, align 4
# |   %5 = shl i32 %4, 29
# |   %6 = load i16, ptr %p.addr, align 2
# |   %7 = zext i16 %6 to i32
# |   %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7)
# |   %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8)
# |   %10 = extractvalue { <4 x i32>, i32 } %9, 1
# |   %11 = lshr i32 %10, 29
# |   %12 = and i32 1, %11
# |   store i32 %12, ptr %3, align 4
# |   %13 = extractvalue { <4 x i32>, i32 } %9, 0
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>,
# | ...
# `---data was truncated (10240/14775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c11b68356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c11b680505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c11b683cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ea0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ea038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ea0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ea031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c11b61923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c11b619086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c11b5fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c11b2ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c11b2ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1ea031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ea031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ea031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c11b2acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (2438 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056188b43656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056188b433505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056188b436cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5ddd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5ddd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5ddd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5ddd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056188b3cc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056188b3cc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056188b3b0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056188b060166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056188b05fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb5ddd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5ddd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5ddd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056188b05fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (2439 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, 
# | ...
# `---data was truncated (10240/60217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e20d27056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e20d26d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e20d270cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3b261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3b26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3b261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3b2603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e20d20623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e20d206086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e20d1eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e20ce9a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e20ce99e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa3b2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3b26050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3b26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e20ce99d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (2440 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d41fc6c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d41fc69505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d41fc6ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa928b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa928b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa928b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa928b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d41fc0223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d41fc02086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d41fbe6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d41f896166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d41f895e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa928b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa928b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa928b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d41f895d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (2441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056459643556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564596432505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564596435cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71f4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71f42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71f4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71f4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645963cb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645963cb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645963aff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056459605f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056459605ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f71f4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71f42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71f42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056459605ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (2442 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align
# | ...
# `---data was truncated (10240/39416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e19dae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e19dab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e19daecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc247b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc247b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc247b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc247b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e19d4423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e19d44086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e19d28f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e199d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e199d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc247b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc247b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc247b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e199d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (2443 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f50ff056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f50fed505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f50ff0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe324533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe32458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe324533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe32451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f50f8623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f50f86086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f50f6af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f50c1a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f50c19e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe32451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe32451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe32451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f50c19d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (2444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a43618756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a436184505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a436187cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b0701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b070725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b0701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b07003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a43611d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a43611d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a436101f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a435db1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a435db0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1b07004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b070050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b070050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a435db0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (2445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056122f5a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056122f5a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056122f5a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff324649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3246a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff324649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff324631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056122f53f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056122f53f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056122f523f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056122f1d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056122f1d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff324632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3246330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3246330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056122f1d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (2446 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bc902e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558bc902b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558bc902ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa53533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa5358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa53533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa5351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bc8fc423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558bc8fc4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558bc8fa8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558bc8c58166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558bc8c57e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa5351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa5351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa5351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bc8c57d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (2447 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0b824a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b0b8247505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b0b824acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe32af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe32af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe32af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe32af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0b81e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0b81e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0b81c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b0b7e74166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b0b7e73e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe32af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe32af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe32af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0b7e73d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (2448 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646ddb9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646ddb99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646ddb9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f911b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f911b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f911b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f911b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646ddb3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646ddb32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646ddb16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646dd7c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646dd7c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f911b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f911b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f911b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646dd7c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (2449 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116957) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b599c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555b599c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555b599c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbefae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbefaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbefae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbefae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b5995c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555b5995c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555b59940f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555b595f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555b595efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbefae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbefae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbefae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b595efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (2450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edfe4fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055edfe4fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055edfe4fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdd6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdd66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdd6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdd6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edfe49423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055edfe494086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055edfe478f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055edfe128166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055edfe127e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbdd6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdd66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdd66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edfe127d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (2451 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b048c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555b048c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555b048c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34ccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34ccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34ccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34ccf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b0485c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555b0485c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555b04840f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555b044f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555b044efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f34ccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34ccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34ccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b044efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (2452 of 27911)
******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm    /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   %fpext = fpext bfloat %0 to float
# |   %fptrunc = fptrunc float %fpext to half
# |   ret half %fptrunc
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %fpext = fpext half %0 to float
# |   %fptrunc = fptrunc float %fpext to bfloat
# |   ret bfloat %fptrunc
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb0755556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb07552505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb07555cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce81d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce81d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce81d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce81d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb074eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb074eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb074cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb0717f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb0717ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce81d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce81d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce81d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb0717ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (2453 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b95174556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b951742505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b951745cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1520b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1520b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1520b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1520b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9516db23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b9516db086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b9516bff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b95136f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b95136ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1520b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1520b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1520b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b95136ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (2454 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c  -check-prefix=RV32ZBKX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkx1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056303294f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056303294c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056303294fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75d6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75d658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75d6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75d651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630328e523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005630328e5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005630328c9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563032579166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563032578e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f75d651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75d651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75d651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563032578d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (2455 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556585a3b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556585a38505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556585a3bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6426133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f642618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6426133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f642611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565859d123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565859d1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565859b5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556585665166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556585664e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f642611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f642611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f642611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556585664d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (2456 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e515fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556e515fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556e515fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3de4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3de438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3de4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3de431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e5159323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556e51593086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556e51577f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556e51227166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556e51226e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3de431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3de431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3de431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e51226d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (2457 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606c542a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606c5427505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606c542acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5b7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5b778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5b7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5b771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606c53c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606c53c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606c53a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606c5054166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606c5053e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5b771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5b771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5b771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606c5053d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (2458 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3344cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a3344c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a3344cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ebad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ebad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ebad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ebad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a33446223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a334462086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a334446f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a3340f6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a3340f5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ebad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ebad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ebad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3340f5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (2459 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564de82e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564de82e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564de82e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f555a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f555a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f555a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f555a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564de827d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564de827d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564de8261f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564de7f11166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564de7f10e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f555a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f555a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f555a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564de7f10d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (2460 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615e9a2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615e9a29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615e9a2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3584b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3584b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3584b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3584b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615e99c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615e99c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615e99a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615e9656166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615e9655e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3584b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3584b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3584b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615e9655d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (2461 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc9b08256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dc9b07f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dc9b082cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8482a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8482aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8482a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8482a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc9b01823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dc9b018086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dc9affcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dc9acac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dc9acabe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8482a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8482a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8482a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc9acabd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (2462 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055914c71656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055914c713505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055914c716cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78cd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78cd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78cd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78cd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055914c6ac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055914c6ac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055914c690f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055914c340166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055914c33fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78cd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78cd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78cd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055914c33fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (2463 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641fde3b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005641fde38505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005641fde3bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7223649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72236a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7223649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7223631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641fddd123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005641fddd1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005641fddb5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005641fda65166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005641fda64e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7223632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72236330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72236330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641fda64d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-poly-add.c (2464 of 27911)
******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi    -target-feature +neon    -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   store <8 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <4 x i16>
# |   store <4 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <1 x i64>
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   store <16 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <16 x i8>, ptr %ref.tmp.i, align 8
# |   store <16 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <16 x i8>, ptr %__ret.i, align 8
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <8 x i16>
# |   store <8 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 8
# |   store <8 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i16>, ptr %__ret.i, align 8
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 8
# |   %__p1.addr.i = alloca <2 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = load <2 x i64>, ptr %b.addr, align 8
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   store <2 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i64>, ptr %ref.tmp.i, align 8
# |   store <2 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i64>, ptr %__ret.i, align 8
# |   ret <2 x i64> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005627d031d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005627d031a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005627d031dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19d9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19d9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19d9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19d9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627d02b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627d02b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005627d0297f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627cff47166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627cff46e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f19d9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19d9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19d9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627cff46d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/12439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647c745056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005647c744d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005647c7450cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd721133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd72118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd721133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd72111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647c73e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005647c73e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005647c73caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005647c707a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005647c7079e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd72111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd72111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd72111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647c7079d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (2466 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdfca9d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fdfca9a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fdfca9dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc454c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc454ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc454c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc454c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdfca3323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fdfca33086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fdfca17f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fdfc6c7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fdfc6c6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc454c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc454c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc454c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdfc6c6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (2467 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608d763756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005608d7634505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005608d7637cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f2d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f2d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f2d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f2d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608d75cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005608d75cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005608d75b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005608d7261166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005608d7260e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5f2d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f2d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f2d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608d7260d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (2468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf78c8456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf78c81505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf78c84cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2915849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29158a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2915849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2915831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf78c1a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf78c1a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf78bfef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf788ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf788ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2915832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29158330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29158330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf788add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (2469 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vlse16_v_
# | ...
# `---data was truncated (10240/35087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626e5dc856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005626e5dc5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005626e5dc8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2973733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f297378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2973733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f297371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626e5d5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005626e5d5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005626e5d42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005626e59f2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005626e59f1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f297371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f297371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f297371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626e59f1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (2470 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d74556756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d745564505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d745567cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d8f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d8f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d8f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d8f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7454fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d7454fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d7454e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d745191166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d745190e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d8f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d8f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d8f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d745190d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (2471 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c851f6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c851f63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c851f66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeafe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeafe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeafe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeafe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c851efc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c851efc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c851ee0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c851b90166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c851b8fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbeafe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeafe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeafe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c851b8fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (2472 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056388578f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056388578c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056388578fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2abb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2abb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2abb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2abb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056388572523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563885725086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563885709f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638853b9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638853b8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2abb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2abb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2abb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638853b8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (2473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vas
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562ee23d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562ee23a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562ee23dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5742049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5742049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5742031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562ee1d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562ee1d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562ee1b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562ede67166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562ede66e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5742032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562ede66d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (2474 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, 
# | ...
# `---data was truncated (10240/30635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583dacde56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005583dacdb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005583dacdecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faccf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faccf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faccf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faccf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583dac7423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005583dac74086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005583dac58f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005583da908166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005583da907e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faccf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faccf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faccf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583da907d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (2475 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f50e7956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f50e76505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f50e79cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3134733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f313478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3134733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f313471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f50e0f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f50e0f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f50df3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f50aa3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f50aa2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f313471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f313471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f313471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f50aa2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (2476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560358a0156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005603589fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560358a01cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cb2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cb2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cb2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cb2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056035899723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560358997086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056035897bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056035862b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056035862ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7cb2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cb2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cb2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056035862ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (2477 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8d9fe456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c8d9fe1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c8d9fe4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d8a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d8a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d8a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d8a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8d9f7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c8d9f7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c8d9f5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c8d9c0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c8d9c0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d8a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d8a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d8a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8d9c0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (2478 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e0cabd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e0caba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e0cabdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb77ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb77ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb77ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb77ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e0ca5323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e0ca53086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e0ca37f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e0c6e7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e0c6e6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb77ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb77ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb77ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e0c6e6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (2479 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ac3f3256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561ac3f2f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561ac3f32cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4842049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4842049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4842031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ac3ec823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561ac3ec8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561ac3eacf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561ac3b5c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561ac3b5be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4842032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ac3b5bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (2480 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556de08cf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556de08cc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556de08cfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb66b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb66b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb66b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb66b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556de086523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556de0865086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556de0849f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556de04f9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556de04f8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb66b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb66b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb66b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556de04f8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (2481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d5f0fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557d5f0f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557d5f0facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5712133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f571218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5712133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f571211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d5f09023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557d5f090086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557d5f074f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557d5ed24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557d5ed23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f571211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f571211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f571211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d5ed23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2482 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/26702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e852a7156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e852a6e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e852a71cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa003f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa003f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa003f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa003f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e852a0723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e852a07086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8529ebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e85269b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e85269ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa003f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa003f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa003f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e85269ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (2483 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8e876356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b8e8760505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b8e8763cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01bd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01bd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01bd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01bd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8e86f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b8e86f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b8e86ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b8e838d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b8e838ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f01bd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01bd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01bd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8e838cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (2484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638b25f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638b25f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638b25f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdffd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdffd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdffd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdffd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638b258c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638b258c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638b2570f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638b2220166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638b221fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdffd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdffd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdffd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638b221fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (2485 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d601d256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d601cf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d601d2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03f7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03f7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03f7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03f7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d6016823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d60168086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d6014cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d5fdfc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d5fdfbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03f7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03f7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03f7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d5fdfbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (2486 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4bf34e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4bf34b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4bf34ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae3ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae3cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae3ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae3ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4bf2e423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4bf2e4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4bf2c8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4bef78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4bef77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae3ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae3ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae3ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4bef77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (2487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4e48e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a4e48e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a4e48e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6973649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69736a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6973649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6973631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4e487923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a4e4879086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a4e485df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a4e450d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a4e450ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6973632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69736330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69736330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4e450cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (2488 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %m
# | ...
# `---data was truncated (10240/41661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639079ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639079eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639079eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22e6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22e6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22e6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22e6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056390798423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563907984086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563907968f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563907618166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563907617e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22e6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22e6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22e6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563907617d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (2489 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b580e1156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b580e0e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b580e11cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f486481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48648725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f486481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4864803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b580da723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b580da7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b580d8bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b580a3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b580a3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4864804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48648050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48648050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b580a3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (2490 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055864049c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558640499505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055864049ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4ce933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4ce98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4ce933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4ce91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055864043223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558640432086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558640416f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586400c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586400c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4ce91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4ce91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4ce91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586400c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (2491 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5a89d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f5a89d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f5a89d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cf6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cf68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cf6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cf6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5a896a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5a896a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5a894ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5a85fe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5a85fde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5cf6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cf68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cf68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5a85fdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (2492 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfb60d256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dfb60cf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dfb60d2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde80733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde8078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde80733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde8071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfb606823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dfb6068086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dfb604cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dfb5cfc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dfb5cfbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde8071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde8071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde8071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfb5cfbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (2493 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc652bf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dc652bc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dc652bfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8ab01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8ab0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8ab01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8ab003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc6525523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dc65255086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dc65239f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dc64ee9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dc64ee8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe8ab004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8ab0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8ab0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc64ee8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (2494 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd7071c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bd70719505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bd7071ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5fe01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5fe0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5fe01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5fe003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd706b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bd706b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bd70696f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bd70346166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bd70345e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff5fe004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5fe0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5fe0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd70345d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (2495 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c  -check-prefix=RV64ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64im(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.aes64im(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ds(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64im(i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2b1c4c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b2b1c49505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b2b1c4ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1eb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1eb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1eb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1eb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2b1be223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b2b1be2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b2b1bc6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b2b1876166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b2b1875e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc1eb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1eb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1eb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2b1875d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (2496 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056330b4f456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056330b4f1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056330b4f4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde32f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde32f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde32f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde32f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056330b48a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056330b48a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056330b46ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056330b11e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056330b11de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fde32f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde32f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde32f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056330b11dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (2497 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055783879956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557838796505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557838799cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01dba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01dbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01dba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01dba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055783872f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055783872f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557838713f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578383c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578383c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f01dba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01dba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01dba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578383c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (2498 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adcb97256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055adcb96f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055adcb972cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29cf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29cf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29cf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29cf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adcb90823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055adcb908086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055adcb8ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055adcb59c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055adcb59be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f29cf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29cf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29cf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adcb59bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (2499 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592013a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005592013a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005592013a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a47933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a4798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a47933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a4791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055920133f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055920133f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559201323f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559200fd3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559200fd2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a4791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a4791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a4791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559200fd2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (2500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f07c6d956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f07c6d6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f07c6d9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1242933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f124298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1242933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f124291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f07c66f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f07c66f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f07c653f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f07c303166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f07c302e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f124291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f124291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f124291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f07c302d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (2501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9bc34856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c9bc345505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c9bc348cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c7a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c7a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c7a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c7a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9bc2de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c9bc2de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c9bc2c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c9bbf72166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c9bbf71e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c7a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c7a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c7a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9bbf71d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (2502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d32f49156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d32f48e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d32f491cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa86af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa86af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa86af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa86af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d32f42723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d32f427086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d32f40bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d32f0bb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d32f0bae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa86af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa86af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa86af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d32f0bad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (2503 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub
# | ...
# `---data was truncated (10240/84979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634527ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005634527ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005634527aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e1d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e1d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e1d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e1d003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056345274423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563452744086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563452728f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005634523d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005634523d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e1d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e1d0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e1d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634523d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (2504 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4d5fb456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e4d5fb1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e4d5fb4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc454733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc45478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc454733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc45471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4d5f4a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4d5f4a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4d5f2ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e4d5bde166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e4d5bdde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc45471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc45471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc45471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4d5bddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (2505 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/81507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600ac66856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005600ac665505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005600ac668cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc413b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc413b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc413b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc413b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600ac5fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600ac5fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600ac5e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005600ac292166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005600ac291e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc413b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc413b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc413b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600ac291d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (2506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056482ded656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056482ded3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056482ded6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5690849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56908a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5690849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5690831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056482de6c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056482de6c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056482de50f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056482db00166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056482daffe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5690832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56908330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56908330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056482daffd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (2507 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572c1ecc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005572c1ec9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005572c1ecccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5783a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5783aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5783a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5783a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572c1e6223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005572c1e62086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005572c1e46f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005572c1af6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005572c1af5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5783a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5783a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5783a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572c1af5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (2508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8ced3a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b8ced37505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b8ced3acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff79e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff79e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff79e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff79e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8cecd023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b8cecd0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b8cecb4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b8ce964166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b8ce963e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff79e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff79e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff79e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8ce963d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (2509 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fde36756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563fde364505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563fde367cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6399705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f639975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6399705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63996ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fde2fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563fde2fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563fde2e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563fddf91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563fddf90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f63996eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63996ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63996ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fddf90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (2510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5b433f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5b433c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5b433fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71d4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71d4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71d4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71d4e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5b42d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5b42d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5b42b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5b3f69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5b3f68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f71d4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71d4e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71d4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5b3f68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (2511 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffb172556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ffb1722505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ffb1725cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f48249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f482a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f48249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f48231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffb16bb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ffb16bb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ffb169ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ffb134f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ffb134ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2f48232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f482330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f482330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffb134ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (2512 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %
# | ...
# `---data was truncated (10240/13308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563db6b9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563db6b99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563db6b9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f757b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f757b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f757b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f757b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563db6b3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563db6b32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563db6b16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563db67c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563db67c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f757b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f757b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f757b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563db67c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (2513 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056481b71f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056481b71c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056481b71fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28b9c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28b9c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28b9c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28b9c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056481b6b523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056481b6b5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056481b699f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056481b349166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056481b348e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f28b9c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28b9c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28b9c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056481b348d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (2514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573f67e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005573f67e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005573f67e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa2ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa2ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa2ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa2ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573f677923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005573f6779086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005573f675df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005573f640d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005573f640ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa2ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa2ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa2ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573f640cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (2515 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c503b7356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c503b70505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c503b73cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd25d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd25d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd25d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd25d4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c503b0923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c503b09086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c503aedf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c50379d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c50379ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd25d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd25d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd25d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c50379cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (2516 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561dc87ec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561dc87e9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561dc87eccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6d2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6d235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6d2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6d22ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dc878223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561dc8782086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561dc8766f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561dc8416166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561dc8415e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb6d22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6d22ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6d22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561dc8415d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (2517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571e8fea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005571e8fe7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005571e8feacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7c181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7c18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7c181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7c1803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571e8f8023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571e8f80086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571e8f64f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571e8c14166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571e8c13e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7c1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7c18050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7c18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571e8c13d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (2518 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/12688) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eb742c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563eb7429505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563eb742ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c46a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c46a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c46a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c46a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eb73c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563eb73c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563eb73a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563eb7056166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563eb7055e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5c46a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c46a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c46a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eb7055d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (2519 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcedae956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fcedae6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fcedae9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3fd01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3fd0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3fd01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3fd003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fceda7f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fceda7f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fceda63f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fced713166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fced712e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc3fd004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3fd0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3fd0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fced712d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (2520 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f12e9f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f12e9f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f12e9f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15d5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15d5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15d5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15d5c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f12e98c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f12e98c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f12e970f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f12e620166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f12e61fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f15d5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15d5c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15d5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f12e61fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (2521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e307ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e307eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e307eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f31449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f314a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f31449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f31431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e3078423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e30784086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e30768f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e30418166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e30417e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5f31432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f314330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f314330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e30417d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (2522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea0e60656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea0e603505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea0e606cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9ac21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9ac2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9ac21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9ac203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea0e59c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea0e59c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea0e580f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea0e230166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea0e22fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc9ac204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9ac2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9ac2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea0e22fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (2523 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7b8e8956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b7b8e86505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b7b8e89cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa92b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa92b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa92b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa92b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7b8e1f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b7b8e1f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b7b8e03f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b7b8ab3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b7b8ab2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa92b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa92b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa92b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7b8ab2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (2524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564770e2656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564770e23505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564770e26cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3107e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3107e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3107e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3107e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564770dbc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564770dbc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564770da0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564770a50166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564770a4fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3107e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3107e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3107e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564770a4fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (2525 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4f7af056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d4f7aed505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d4f7af0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0873733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f087378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0873733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f087371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4f7a8623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d4f7a86086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d4f7a6af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d4f771a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d4f7719e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f087371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f087371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f087371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4f7719d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (2526 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc47c8956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc47c86505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc47c89cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e9cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e9cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e9cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e9cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc47c1f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc47c1f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc47c03f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc478b3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc478b2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8e9cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e9cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e9cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc478b2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (2527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @ll
# | ...
# `---data was truncated (10240/47728) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c25e25056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c25e24d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c25e250cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2584b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2584b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2584b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2584b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c25e1e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c25e1e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c25e1caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c25de7a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c25de79e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2584b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2584b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2584b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c25de79d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (2528 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055972c54556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055972c542505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055972c545cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5646249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56462a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5646249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5646231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055972c4db23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055972c4db086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055972c4bff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055972c16f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055972c16ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5646232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56462330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56462330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055972c16ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (2529 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576d6ed156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576d6ece505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576d6ed1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b0731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576d6e6723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576d6e67086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576d6e4bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576d6afb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576d6afae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b0731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576d6afad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (2530 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d63bf7e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d63bf7b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d63bf7ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dd7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dd7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dd7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dd7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d63bf1423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d63bf14086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d63bef8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d63bba8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d63bba7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2dd7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dd7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dd7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d63bba7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (2531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648ca47656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005648ca473505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005648ca476cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ec7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ec70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ec7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ec7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648ca40c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005648ca40c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005648ca3f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005648ca0a0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005648ca09fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ec7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ec70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ec70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648ca09fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (2532 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5ed3f956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5ed3f6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5ed3f9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f995db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f995db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f995db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f995db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5ed38f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5ed38f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5ed373f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5ed023166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5ed022e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f995db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f995db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f995db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5ed022d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (2533 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a45e49556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a45e492505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a45e495cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac6c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac6c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac6c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac6c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a45e42b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a45e42b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a45e40ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a45e0bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a45e0bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac6c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac6c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac6c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a45e0bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (2534 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576a522456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576a5221505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576a5224cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3908049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3908049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3908031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576a51ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576a51ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576a519ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576a4e4e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576a4e4de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3908032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39080330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576a4e4dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (2535 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a87df5356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a87df50505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a87df53cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9564049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95640a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9564049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9564031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a87dee923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a87dee9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a87decdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a87db7d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a87db7ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9564032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95640330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95640330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a87db7cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (2536 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | ...
# `---data was truncated (10240/12457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f7d35e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f7d35b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f7d35ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58b241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58b24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58b241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58b2403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f7d2f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f7d2f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f7d2d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f7cf88166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f7cf87e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f58b2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58b24050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58b24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f7cf87d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (2537 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloc
# | ...
# `---data was truncated (10240/71123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1124b056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e1124ad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e1124b0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb285733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb28578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb285733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb28571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e11244623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e112446086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e11242af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e1120da166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e1120d9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb28571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb28571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb28571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1120d9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (2538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630ce39656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005630ce393505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005630ce396cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19f5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19f58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19f5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19f5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630ce32c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005630ce32c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005630ce310f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005630cdfc0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005630cdfbfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f19f5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19f58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19f58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630cdfbfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (2539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055578837256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055578836f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555788372cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb605c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb605ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb605c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb605c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055578830823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555788308086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005557882ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555787f9c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555787f9be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb605c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb605c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb605c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555787f9bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (2540 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fd892c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558fd8929505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558fd892ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc427049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4270a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc427049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc427031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fd88c223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558fd88c2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558fd88a6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558fd8556166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558fd8555e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc427032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4270330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4270330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fd8555d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (2541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd6a89956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dd6a896505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dd6a899cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc007d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc007d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc007d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc007d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd6a82f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dd6a82f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dd6a813f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dd6a4c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dd6a4c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc007d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc007d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc007d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd6a4c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (2542 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f63f2856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555f63f25505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555f63f28cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f154c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f154c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f154c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f154c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f63ebe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555f63ebe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555f63ea2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555f63b52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555f63b51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f154c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f154c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f154c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f63b51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (2543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f38408c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f384089505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f38408ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc701449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7014a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc701449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc701431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f38402223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f384022086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f384006f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f383cb6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f383cb5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc701432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7014330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7014330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f383cb5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (2544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<vscale x
# | ...
# `---data was truncated (10240/119289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056415a83d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056415a83a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056415a83dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b89d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b89d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b89d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b89ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056415a7d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056415a7d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056415a7b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056415a467166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056415a466e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b89ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b89cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b89cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056415a466d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (2545 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | ...
# `---data was truncated (10240/12958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055581c85556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055581c852505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055581c855cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b38249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b382a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b38249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b38231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055581c7eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055581c7eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055581c7cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055581c47f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055581c47ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b38232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b382330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b382330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055581c47ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (2546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nou
# | ...
# `---data was truncated (10240/25034) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055766286656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557662863505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557662866cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff61ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff61ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff61ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff61ba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576627fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576627fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576627e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557662490166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055766248fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff61ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff61ba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff61ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055766248fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (2547 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b38e46356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b38e460505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b38e463cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bd3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bd3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bd3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bd3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b38e3f923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b38e3f9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b38e3ddf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b38e08d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b38e08ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8bd3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bd3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bd3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b38e08cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (2548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, 
# | ...
# `---data was truncated (10240/20307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d0b1bb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556d0b1b8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556d0b1bbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f123e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f123e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f123e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f123e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d0b15123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556d0b151086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556d0b135f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556d0ade5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556d0ade4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f123e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f123e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f123e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d0ade4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (2549 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, bflo
# | ...
# `---data was truncated (10240/43940) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056432224556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564322242505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564322245cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f729dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f729dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f729dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f729dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643221db23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005643221db086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005643221bff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564321e6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564321e6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f729dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f729dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f729dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564321e6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (2550 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056058960856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560589605505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560589608cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4923a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4923aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4923a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4923a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056058959e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056058959e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560589582f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560589232166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560589231e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4923a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4923a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4923a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560589231d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (2551 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056003055a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560030557505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056003055acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7260133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f726018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7260133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f726011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600304f023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600304f0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600304d4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560030184166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560030183e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f726011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f726011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f726011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560030183d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (2552 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606d36d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606d36d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606d36d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f592f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f592f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f592f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f592f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606d366a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005606d366a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005606d364ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005606d32fe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005606d32fde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f592f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f592f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f592f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606d32fdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (2553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ef881b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561ef8818505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561ef881bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ca7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ca758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ca7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ca751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ef87b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561ef87b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561ef8795f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561ef8445166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561ef8444e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ca751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ca751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ca751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ef8444d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (2554 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606229ea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005606229e7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005606229eacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2727d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2727d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2727d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2727d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056062298023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560622980086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560622964f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560622614166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560622613e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2727d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2727d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2727d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560622613d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (2555 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa684fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa684f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa684fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f262e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f262e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f262e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f262e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa6849223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa68492086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa68476f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa68126166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa68125e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f262e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f262e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f262e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa68125d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (2556 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.1a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %c.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   %2 = load <8 x i16>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %c.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   %2 = load <4 x i32>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   store <4 x i32> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32>
# |   %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32>
# |   %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i)
# |   %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   %__ret_140 = alloca <4 x i16>, align 8
# |   %__s0_140 = alloca <4 x i16>, align 8
# |   %__s1_140 = alloca <4 x i16>, align 8
# |   %__s2_140 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_140, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_140, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_140, align 8
# |   %3 = load <4 x i16>, ptr %__s0_140, align 8
# |   %4 = load <4 x i16>, ptr %__s1_140, align 8
# |   %5 = load <4 x i16>, ptr %__s2_140, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_140, align 8
# |   %16 = load <4 x i16>, ptr %__ret_140, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr
# | ...
# `---data was truncated (10240/38786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x000055abb5f6756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055abb5f64505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055abb5f67cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9f0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9f018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9f0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9f011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abb5efd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055abb5efd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055abb5ee1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055abb5b91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055abb5b90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9f011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9f011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9f011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abb5b90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (2557 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055884c89f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055884c89c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055884c89fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8d8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8d86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8d8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8d8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055884c83523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055884c835086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055884c819f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055884c4c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055884c4c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe8d8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8d86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8d86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055884c4c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (2558 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055721210e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055721210b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055721210ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7969649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79696a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7969649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7969631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572120a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005572120a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557212088f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557211d38166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557211d37e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7969632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79696330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79696330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557211d37d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (2559 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c2d2a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c2d2a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c2d2a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8372333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f837238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8372333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f837231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c2d23a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c2d23a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c2d21ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c2cece166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c2cecde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f837231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f837231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f837231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c2cecdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (2560 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6c9bd756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e6c9bd4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e6c9bd7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f514b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f514b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f514b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f514b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6c9b6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e6c9b6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e6c9b51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e6c9801166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e6c9800e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f514b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f514b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f514b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6c9800d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (2561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055695369756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556953694505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556953697cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07d401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07d40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07d401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07d4003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055695362d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055695362d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556953611f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005569532c1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005569532c0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f07d4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07d40050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07d40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569532c0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (2562 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.a
# | ...
# `---data was truncated (10240/33190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c088ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c088eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c088eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b1c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b1c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b1c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b1c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c0888423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c08884086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c08868f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c08518166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c08517e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b1c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b1c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b1c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c08517d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (2563 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e7039c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563e70399505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563e7039ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f572941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57294725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f572941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5729403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e7033223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563e70332086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563e70316f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563e6ffc6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563e6ffc5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5729404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57294050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57294050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e6ffc5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (2564 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, p
# | ...
# `---data was truncated (10240/33435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056262d11b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056262d118505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056262d11bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd062f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd062f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd062f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd062eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056262d0b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056262d0b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056262d095f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056262cd45166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056262cd44e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd062eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd062eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd062eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056262cd44d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (2565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555db05f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005555db05c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005555db05fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e27d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e27d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e27d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e27d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555daff523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005555daff5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005555dafd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005555dac89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005555dac88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e27d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e27d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e27d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555dac88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (2566 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571a70bb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005571a70b8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005571a70bbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f108bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f108bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f108bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f108beed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571a705123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571a7051086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571a7035f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005571a6ce5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005571a6ce4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f108beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f108beef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f108beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571a6ce4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (2567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cce613856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cce6135505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cce6138cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23d7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23d7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23d7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23d7c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cce60ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cce60ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cce60b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cce5d62166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cce5d61e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f23d7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23d7c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23d7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cce5d61d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (2568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d09598a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d095987505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d09598acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f519cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f519cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f519cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f519cc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d09592023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d095920086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d095904f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d0955b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d0955b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f519cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f519cc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f519cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0955b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (2569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m2_i8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m4_i8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m8_i8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m4_i8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m8_i8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_i8m8_i8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m2_u8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m4_u8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m8_u8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m4_u8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m8_u8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_u8m8_u8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m2_i16m1(<vscale x 8 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m4_i16m1(<vscale x 16 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m8_i16m1(<vscale x 32 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale
# | ...
# `---data was truncated (10240/40902) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640cf59d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640cf59a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640cf59dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe849733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe84978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe849733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe84971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640cf53323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640cf533086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640cf517f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640cf1c7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640cf1c6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe84971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe84971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe84971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640cf1c6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (2570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce4f92b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce4f928505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce4f92bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12f6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12f6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12f6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12f6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce4f8c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce4f8c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce4f8a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce4f555166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce4f554e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f12f6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12f6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12f6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce4f554d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (2571 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd62df156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd62dee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd62df1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c70733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c7078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c70733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c7071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd62d8723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd62d87086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd62d6bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd62a1b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd62a1ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8c7071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c7071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c7071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd62a1ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (2572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5882e856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a5882e5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a5882e8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48dcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48dcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48dcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48dcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a58827e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a58827e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a588262f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a587f12166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a587f11e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f48dcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48dcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48dcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a587f11d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (2573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c49a77056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c49a76d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c49a770cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dd2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dd2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dd2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dd2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c49a70623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c49a706086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c49a6eaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c49a39a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c49a399e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0dd2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dd2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dd2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c49a399d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (2574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op
# | ...
# `---data was truncated (10240/154517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055739bf6456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055739bf61505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055739bf64cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f065c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f065c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f065c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f065c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055739befa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055739befa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055739bedef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055739bb8e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055739bb8de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f065c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f065c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f065c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055739bb8dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (2575 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 =
# | ...
# `---data was truncated (10240/10936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f39fec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f39fe9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f39feccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efeef733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efeef78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efeef733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efeef71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f39f8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f39f82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f39f66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f39c16166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f39c15e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efeef71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efeef71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efeef71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f39c15d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (2576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1,
# | ...
# `---data was truncated (10240/223801) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557764fa756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557764fa4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557764fa7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdbf905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdbf95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdbf905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdbf8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557764f3d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557764f3d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557764f21f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557764bd1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557764bd0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efdbf8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdbf8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdbf8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557764bd0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-neon-shifts.c (2577 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -disable-O0-optnone    -target-cpu cortex-a8    -ffreestanding    -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"apcs-gnu"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1ab1b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e1ab1b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e1ab1b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64b8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64b86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64b8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64b8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1ab14a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e1ab14a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1ab12ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e1aadde166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e1aaddde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f64b8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64b86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64b86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1aadddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (2578 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, 
# | ...
# `---data was truncated (10240/26468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b51a31b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b51a318505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b51a31bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9d4b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9d4b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9d4b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9d4aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b51a2b123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b51a2b1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b51a295f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b519f45166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b519f44e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff9d4aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9d4aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9d4aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b519f44d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (2579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558761ef156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558761eee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558761ef1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb88f305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb88f35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb88f305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb88f2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558761e8723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558761e87086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558761e6bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558761b1b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558761b1ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb88f2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb88f2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb88f2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558761b1ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (2580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf6c98456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bf6c981505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bf6c984cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd66a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd66a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd66a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd66a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf6c91a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bf6c91a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bf6c8fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bf6c5ae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bf6c5ade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd66a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd66a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd66a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf6c5add71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (2581 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614bfada56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005614bfad7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005614bfadacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5929933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f592998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5929933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f592991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614bfa7023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005614bfa70086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005614bfa54f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005614bf704166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005614bf703e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f592991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f592991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f592991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614bf703d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (2582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <v
# | ...
# `---data was truncated (10240/22290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bd6e7f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bd6e7c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bd6e7fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f140b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f140b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f140b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f140b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bd6e1523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bd6e15086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bd6df9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bd6aa9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bd6aa8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f140b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f140b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f140b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bd6aa8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (2583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>,
# | ...
# `---data was truncated (10240/11969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e45dd3c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e45dd39505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e45dd3ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37f4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37f40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37f4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37f4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e45dcd223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e45dcd2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e45dcb6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e45d966166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e45d965e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f37f4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37f40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37f40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e45d965d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (2584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c7495b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564c74958505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564c7495bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d48049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d480a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d48049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d48031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c748f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564c748f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564c748d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564c74585166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564c74584e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d48032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d480330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d480330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c74584d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm_acle.c (2585 of 27911)
******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dmb() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dsb() #0 {
# | entry:
# |   call void @llvm.arm.dsb(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_isb() #0 {
# | entry:
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pld() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pldx() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pli() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_plix() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 32
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %4, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i32, ptr %__x.addr.i, align 4
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %shr.i = lshr i32 %5, %6
# |   %7 = load i32, ptr %__x.addr.i, align 4
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 32, %8
# |   %shl.i = shl i32 %7, %sub.i
# |   %or.i = or i32 %shr.i, %shl.i
# |   store i32 %or.i, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | __ror.exit:                                       ; preds = %if.then.i, %if.end.i
# |   %9 = load i32, ptr %retval.i, align 4
# |   ret i32 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i.i = alloca i32, align 4
# |   %__x.addr.i.i = alloca i32, align 4
# |   %__y.addr.i.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   store i32 %2, ptr %__x.addr.i.i, align 4
# |   store i32 %3, ptr %__y.addr.i.i, align 4
# |   %4 = load i32, ptr %__y.addr.i.i, align 4
# |   %rem.i.i = urem i32 %4, 32
# |   store i32 %rem.i.i, ptr %__y.addr.i.i, align 4
# |   %5 = load i32, ptr %__y.addr.i.i, align 4
# |   %cmp.i.i = icmp eq i32 %5, 0
# |   br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i
# | 
# | if.then.i.i:                                      ; preds = %entry
# |   %6 = load i32, ptr %__x.addr.i.i, align 4
# |   store i32 %6, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | if.end.i.i:                                       ; preds = %entry
# |   %7 = load i32, ptr %__x.addr.i.i, align 4
# |   %8 = load i32, ptr %__y.addr.i.i, align 4
# |   %shr.i.i = lshr i32 %7, %8
# |   %9 = load i32, ptr %__x.addr.i.i, align 4
# |   %10 = load i32, ptr %__y.addr.i.i, align 4
# |   %sub.i.i = sub i32 32, %10
# |   %shl.i.i = shl i32 %9, %sub.i.i
# |   %or.i.i = or i32 %shr.i.i, %shl.i.i
# |   store i32 %or.i.i, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | __rorl.exit:                                      ; preds = %if.then.i.i, %if.end.i.i
# |   %11 = load i32, ptr %retval.i.i, align 4
# |   ret i32 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i64, align 8
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i64, align 8
# |   %y.addr = alloca i32, align 4
# |   store i64 %x, ptr %x.addr, align 8
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i64, ptr %x.addr, align 8
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 64
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i64, ptr %__x.addr.i, align 8
# |   store i64 %4, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i64, ptr %__x.addr.i, align 8
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %sh_prom.i = zext i32 %6 to i64
# |   %shr.i = lshr i64 %5, %sh_prom.i
# |   %7 = load i64, ptr %__x.addr.i, align 8
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 64, %8
# |   %sh_prom1.i = zext i32 %sub.i to i64
# |   %shl.i = shl i64 %7, %sh_prom1.i
# |   %or.i = or i64 %shr.i, %shl.i
# |   store i64 %or.i, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | __rorll.exit:                                     ; preds = %if.then.i, %if.end.i
# |   %9 = load i64, ptr %retval.i, align 8
# |   ret i64 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clz(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzl(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzll(i64 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i64, align 8
# |   %t.addr = alloca i64, align 8
# |   store i64 %t, ptr %t.addr, align 8
# |   %0 = load i64, ptr %t.addr, align 8
# |   store i64 %0, ptr %__t.addr.i, align 8
# |   %1 = load i64, ptr %__t.addr.i, align 8
# |   %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false)
# |   %3 = trunc i64 %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %cls.i = call i32 @llvm.arm.cls(i32 %1)
# |   ret i32 %cls.i
# | }
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/86891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be907d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be907d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be907d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f955ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f955cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f955ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f955ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be9076b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be9076b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be9074ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be903ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be903fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f955ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f955ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f955ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be903fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (2586 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599bdebd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005599bdeba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005599bdebdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b44249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b442a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b44249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b44231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599bde5323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005599bde53086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005599bde37f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005599bdae7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005599bdae6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0b44232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b442330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b442330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599bdae6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (2587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/135111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbf7f8e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fbf7f8b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fbf7f8ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f531e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f531e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f531e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f531e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbf7f2423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fbf7f24086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fbf7f08f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fbf7bb8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fbf7bb7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f531e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f531e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f531e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbf7bb7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (2588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056441aa9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056441aa99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056441aa9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa31733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa3178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa31733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa3171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056441aa3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056441aa32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056441aa16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056441a6c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056441a6c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffa3171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa3171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa3171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056441a6c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (2589 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/11958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dda1d5f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dda1d5c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dda1d5fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bc9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bc96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bc9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bc9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dda1cf523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dda1cf5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dda1cd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dda1989166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dda1988e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9bc9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bc96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bc96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dda1988d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (2590 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e830dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555e830da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555e830ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bbc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bbc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bbc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bbc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e8307323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555e83073086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555e83057f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555e82d07166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555e82d06e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3bbc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bbc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bbc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e82d06d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (2591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652906a756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652906a4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652906a7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08d8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08d858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08d8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08d851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056529063d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056529063d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000565290621f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005652902d1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005652902d0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f08d851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08d851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08d851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652902d0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (2592 of 27911)
******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default<O0>,default<O2>' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.wrapper = type { %struct.task }
# | %struct.task = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" }
# | %"struct.std::coroutine_handle.0" = type { ptr }
# | %"struct.task::promise_type" = type { i8 }
# | %"struct.std::suspend_always" = type { i8 }
# | 
# | $_ZN4task12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN4task12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN4task12promise_type11return_voidEv = comdat any
# | 
# | $_ZN4task12promise_type13final_suspendEv = comdat any
# | 
# | $_ZN7wrapperC1EO4task = comdat any
# | 
# | $_ZN4taskD1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZN7wrapperC2EO4task = comdat any
# | 
# | $_ZN4taskC1EOS_ = comdat any
# | 
# | $_ZN4taskC2EOS_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEaSEDn = comdat any
# | 
# | $_ZN4taskD2Ev = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any
# | 
# | ; Function Attrs: mustprogress nounwind presplitcoroutine
# | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %gro.active = alloca i1, align 1
# |   %__promise = alloca %"struct.task::promise_type", align 1
# |   %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6
# |   %ref.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %ref.tmp2 = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null)
# |   %1 = call i1 @llvm.coro.alloc(token %0)
# |   br i1 %1, label %coro.alloc, label %coro.init
# | 
# | coro.alloc:                                       ; preds = %entry
# |   %2 = call i64 @llvm.coro.size.i64()
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14
# |   br label %coro.init
# | 
# | coro.init:                                        ; preds = %coro.alloc, %entry
# |   %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ]
# |   %4 = call ptr @llvm.coro.begin(token %0, ptr %3)
# |   store i1 false, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %__promise) #9
# |   call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9
# |   call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   store i1 true, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9
# |   call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br i1 %call1, label %init.ready, label %init.suspend
# | 
# | init.suspend:                                     ; preds = %coro.init
# |   %5 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9
# |   %6 = call i8 @llvm.coro.suspend(token %5, i1 false)
# |   switch i8 %6, label %pre.gvo.conv [
# |     i8 0, label %init.ready
# |     i8 1, label %init.cleanup
# |   ]
# | 
# | init.cleanup:                                     ; preds = %init.suspend
# |   br label %cleanup
# | 
# | init.ready:                                       ; preds = %init.suspend, %coro.init
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %init.ready, %init.cleanup
# |   %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9
# |   switch i32 %cleanup.dest.slot.0, label %unreachable [
# |     i32 0, label %cleanup.cont
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | cleanup.cont:                                     ; preds = %cleanup
# |   call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   br label %coro.final
# | 
# | coro.final:                                       ; preds = %cleanup.cont
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9
# |   call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br i1 %call4, label %final.ready, label %final.suspend
# | 
# | final.suspend:                                    ; preds = %coro.final
# |   %7 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9
# |   %8 = call i8 @llvm.coro.suspend(token %7, i1 true)
# |   switch i8 %8, label %pre.gvo.conv [
# |     i8 0, label %final.ready
# |     i8 1, label %final.cleanup
# |   ]
# | 
# | final.cleanup:                                    ; preds = %final.suspend
# |   br label %cleanup5
# | 
# | final.ready:                                      ; preds = %final.suspend, %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br label %cleanup5
# | 
# | cleanup5:                                         ; preds = %final.ready, %final.cleanup
# |   %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9
# |   switch i32 %cleanup.dest.slot.1, label %unreachable [
# |     i32 0, label %pre.gvo.conv
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | pre.gvo.conv:                                     ; preds = %cleanup5, %final.suspend, %init.suspend
# |   %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ]
# |   %InRamp = call i1 @llvm.coro.is_in_ramp()
# |   br i1 %InRamp, label %gro.conv, label %after.gro.conv
# | 
# | gro.conv:                                         ; preds = %pre.gvo.conv
# |   call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9
# |   %cleanup.is_active = load i1, ptr %gro.active, align 1
# |   br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done
# | 
# | cleanup.action:                                   ; preds = %gro.conv
# |   call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9
# |   br label %cleanup.done
# | 
# | cleanup.done:                                     ; preds = %cleanup.action, %gro.conv
# |   br label %after.gro.conv
# | 
# | after.gro.conv:                                   ; preds = %cleanup.done, %pre.gvo.conv
# |   br i1 %9, label %cleanup.cont7, label %coro.ret
# | 
# | cleanup.cont7:                                    ; preds = %after.gro.conv
# |   br label %coro.cleanup
# | 
# | coro.cleanup:                                     ; preds = %cleanup.cont7, %cleanup5, %cleanup
# |   call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9
# |   call void @llvm.lifetime.end.p0(ptr %__promise) #9
# |   %10 = call ptr @llvm.coro.free(token %0, ptr %4)
# |   %11 = icmp ne ptr %10, null
# |   br i1 %11, label %coro.free, label %after.coro.free
# | 
# | coro.free:                                        ; preds = %coro.cleanup
# |   %12 = call i64 @llvm.coro.size.i64()
# |   call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9
# |   br label %after.coro.free
# | 
# | after.coro.free:                                  ; preds = %coro.cleanup, %coro.free
# |   call void @llvm.coro.dead(ptr %4)
# |   br label %coro.ret
# | 
# | coro.ret:                                         ; preds = %after.coro.free, %after.gro.conv
# |   call void @llvm.coro.end(ptr null, i1 false, token none)
# |   ret void
# | 
# | unreachable:                                      ; preds = %cleanup5, %cleanup
# |   unreachable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i1 @llvm.coro.alloc(token) #2
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #3
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i64 @llvm.coro.size.i64() #2
# | 
# | ; Function Attrs: nounwind memory(argmem: readwrite)
# | declare ptr @llvm.coro.begin(token, ptr writeonly) #4
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5
# | 
# | ; Function Attrs: mustprogress nounwind
# | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %this.addr = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8, !tbaa !7
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"s
# | ...
# `---data was truncated (10240/31146) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default<O0>,default<O2>' -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default<O0>,default<O2> -S
# |  #0 0x000055fd8da3956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd8da36505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd8da39cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f526fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f526fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f526fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f526fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd8d9cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd8d9cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd8d9b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd8d663166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd8d662e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f526fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f526fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f526fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd8d662d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (2593 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbd316156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bbd315e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bbd3161cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80bf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80bf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80bf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80bf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbd30f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bbd30f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bbd30dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bbd2d8b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bbd2d8ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80bf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80bf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80bf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbd2d8ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (2594 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589e31b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589e31b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589e31b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8440733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f844078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8440733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f844071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589e314d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589e314d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589e3131f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589e2de1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589e2de0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f844071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f844071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f844071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589e2de0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (2595 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bc966156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563bc965e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563bc9661cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff83f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff83f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff83f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff83f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bc95f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563bc95f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563bc95dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563bc928b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563bc928ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007eff83f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff83f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff83f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bc928ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (2596 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# |  #0 0x0000558848ed756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558848ed4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558848ed7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb20c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb20c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb20c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb20c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558848e6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558848e6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558848e51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558848b01166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558848b00e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb20c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb20c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb20c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558848b00d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (2597 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/26996) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ecfb7156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ecfb6e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ecfb71cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09d6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ecfb0723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ecfb07086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ecfaebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ecf79b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ecf79ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f09d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ecf79ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (2598 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c1e82056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c1e81d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c1e820cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4162933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f416298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4162933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f416291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c1e7b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c1e7b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c1e79af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c1e44a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c1e449e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f416291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f416291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f416291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c1e449d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (2599 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x ha
# | ...
# `---data was truncated (10240/58653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fc115856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559fc1155505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559fc1158cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd2ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd2baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd2ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd2ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fc10ee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559fc10ee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559fc10d2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559fc0d82166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559fc0d81e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd2ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd2ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd2ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fc0d81d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (2600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a726d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557a726d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557a726d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b4cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b4cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b4cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b4cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a7266d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557a7266d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557a72651f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557a72301166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557a72300e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b4cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b4cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b4cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a72300d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (2601 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/98581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e21de6c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e21de69505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e21de6ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4fd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4fd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4fd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4fd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e21de0223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e21de02086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e21dde6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e21da96166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e21da95e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff4fd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4fd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4fd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e21da95d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (2602 of 27911)
******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - |     /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | @X = global i32 0, align 4
# | @Y = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @foo() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %i = alloca i32, align 4
# |   store i32 0, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %entry
# |   %0 = load i32, ptr %i, align 4
# |   %cmp = icmp slt i32 %0, 100
# |   br i1 %cmp, label %for.body, label %for.end
# | 
# | for.body:                                         ; preds = %for.cond
# |   br label %for.end
# | 
# | for.inc:                                          ; No predecessors!
# |   %1 = load i32, ptr %i, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.end:                                          ; preds = %for.body, %for.cond
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type]
# |    13 | }
# |       | ^
# | 1 warning generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# |  #0 0x000056326ad9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056326ad94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056326ad97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc65d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc65d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc65d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc65d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056326ad2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056326ad2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056326ad11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056326a9c1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056326a9c0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc65d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc65d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc65d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056326a9c0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (2603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/18873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556e11e056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005556e11dd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005556e11e0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb979e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb979e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb979e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb979e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556e117623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005556e1176086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005556e115af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005556e0e0a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005556e0e09e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb979e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb979e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb979e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556e0e09d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (2604 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564080f7d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564080f7a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564080f7dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe945c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe945c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe945c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe945c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564080f1323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564080f13086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564080ef7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564080ba7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564080ba6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe945c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe945c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe945c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564080ba6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (2605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0b74e056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e0b74dd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e0b74e0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3416b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3416b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3416b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3416aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0b747623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e0b7476086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e0b745af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e0b710a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e0b7109e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3416aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3416aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3416aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0b7109d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-neon-dot-product.c (2606 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 8
# |   %__s0_827 = alloca <4 x i32>, align 8
# |   %__s1_827 = alloca <16 x i8>, align 8
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x i32>, align 8
# |   %tmp2 = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0_827, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %1, ptr %__s1_827, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 8
# |   %4 = load <16 x i8>, ptr %__s1_827, align 8
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1,
# | ...
# `---data was truncated (10240/18322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055ac8fde556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac8fde2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac8fde5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b49733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b4978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b49733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b4971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac8fd7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac8fd7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac8fd5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac8fa0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac8fa0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b4971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b4971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b4971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac8fa0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (2607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, flo
# | ...
# `---data was truncated (10240/34773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558b125e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558b125b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558b125ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf4ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf4ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf4ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf4eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558b11f423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005558b11f4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005558b11d8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558b0e88166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558b0e87e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdf4eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf4eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf4eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558b0e87d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (2608 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b17402856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b174025505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b174028cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbf5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbf52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbf5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbf5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b173fbe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b173fbe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b173fa2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b173c52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b173c51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcbf5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbf52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbf52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b173c51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (2609 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/68429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570bf67956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005570bf676505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005570bf679cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90bc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90bc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90bc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90bc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570bf60f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570bf60f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570bf5f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570bf2a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570bf2a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f90bc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90bc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90bc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570bf2a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (2610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/13625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bea547456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bea5471505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bea5474cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e56c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e56ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e56c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e56c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bea540a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bea540a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bea53eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bea509e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bea509de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9e56c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e56c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e56c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bea509dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (2611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583b498a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005583b4987505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005583b498acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f574c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f574c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f574c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f574c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583b492023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005583b4920086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005583b4904f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005583b45b4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005583b45b3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f574c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f574c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f574c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583b45b3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (2612 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc4bdb356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc4bdb0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc4bdb3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc00c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc00c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc00c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc00c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc4bd4923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc4bd49086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc4bd2df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc4b9dd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc4b9dce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc00c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc00c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc00c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc4b9dcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (2613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555717d3f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555717d3c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555717d3fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa71a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa71a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa71a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa71a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555717cd523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555717cd5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555717cb9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555717969166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555717968e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa71a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa71a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa71a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555717968d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (2614 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560486be556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560486be2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560486be5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560486b7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560486b7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560486b5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056048680f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056048680ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f74a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056048680ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (2615 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615de6c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615de6c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615de6c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84cdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84cdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84cdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84cdc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615de65d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615de65d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615de641f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615de2f1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615de2f0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f84cdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84cdc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84cdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615de2f0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (2616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056201015b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562010158505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056201015bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8063a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8063aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8063a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8063a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620100f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005620100f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005620100d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056200fd85166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056200fd84e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8063a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8063a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8063a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056200fd84d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (2617 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056306257e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056306257b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056306257ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17a1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17a12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17a1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17a1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056306251423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563062514086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005630624f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005630621a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005630621a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f17a1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17a12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17a12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630621a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (2618 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x 
# | ...
# `---data was truncated (10240/18674) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639a58dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005639a58d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005639a58dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b58849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b588a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b58849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b58831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639a587223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005639a5872086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005639a5856f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005639a5506166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005639a5505e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b58832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b588330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b588330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639a5505d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (2619 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/32694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619856d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005619856d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005619856d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd78ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd78eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd78ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd78ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056198566b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056198566b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056198564ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005619852ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005619852fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd78ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd78ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd78ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619852fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (2620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f72c1156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f72c0e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f72c11cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0295c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0295ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0295c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0295c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f72ba723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f72ba7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f72b8bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f7283b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f7283ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0295c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0295c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0295c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f7283ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (2621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/62956) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056505faf656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056505faf3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056505faf6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70e2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70e24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70e2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70e2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056505fa8c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056505fa8c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056505fa70f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056505f720166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056505f71fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f70e2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70e24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70e24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056505f71fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (2622 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 =
# | ...
# `---data was truncated (10240/19190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9d24b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9d24b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9d24b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb57a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb57a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb57a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb57a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9d244d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f9d244d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f9d2431f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f9d20e1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f9d20e0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb57a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb57a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb57a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9d20e0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (2623 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.r
# | ...
# `---data was truncated (10240/33423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055587a40d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055587a40a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055587a40dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d28a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d28aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d28a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d28a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055587a3a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055587a3a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055587a387f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055587a037166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055587a036e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d28a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d28a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d28a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055587a036d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (2624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638cd21a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005638cd217505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005638cd21acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77fc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77fc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77fc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77fc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638cd1b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005638cd1b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005638cd194f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005638cce44166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005638cce43e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f77fc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77fc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77fc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638cce43d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (2625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/205813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568b15a956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005568b15a6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005568b15a9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dd1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dd138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dd1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dd131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568b153f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005568b153f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005568b1523f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005568b11d3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005568b11d2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2dd131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dd131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dd131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568b11d2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (2626 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/24982) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559791fe456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559791fe1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559791fe4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a55649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a55649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a55631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559791f7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559791f7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559791f5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559791c0e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559791c0de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8a55632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a556330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559791c0dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (2627 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055feff12856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055feff125505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055feff128cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d14733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d1478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d14733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d1471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feff0be23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055feff0be086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055feff0a2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fefed52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fefed51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d1471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d1471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d1471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fefed51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (2628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617bd4e256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005617bd4df505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005617bd4e2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad1bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad1bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad1bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad1bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617bd47823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005617bd478086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005617bd45cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005617bd10c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005617bd10be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fad1bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad1bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad1bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617bd10bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (2629 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056074c1fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056074c1fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056074c1fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee26733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee26733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee2671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056074c19423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056074c194086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056074c178f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056074be28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056074be27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fee2671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee2671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee2671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056074be27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (2630 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558be74f556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558be74f2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558be74f5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f490ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f490eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f490ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f490ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558be748b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558be748b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558be746ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558be711f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558be711ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f490ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f490ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f490ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558be711ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (2631 of 27911)
******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.annotated_flex = type { i64, i8, [0 x i8] }
# | 
# | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8
# | @sink = external global i64, align 8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_fam(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %2 = ptrtoint ptr %arraydecay to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %3 = icmp sgt i64 %flexible_array_member_size, -1
# |   %4 = select i1 %3, i64 %flexible_array_member_size, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_subscript(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2
# |   %2 = ptrtoint ptr %arrayidx to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 2
# |   %3 = icmp sgt i64 %result, -1
# |   %4 = and i1 true, %3
# |   %5 = select i1 %4, i64 %result, i64 0
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_addrof(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %2 = ptrtoint ptr %fam to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_fam() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %0 = icmp sgt i64 %flexible_array_member_size, -1
# |   %1 = select i1 %0, i64 %flexible_array_member_size, i64 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_subscript() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %0 = icmp sgt i64 %result, -1
# |   %1 = and i1 true, %0
# |   %2 = select i1 %1, i64 %result, i64 0
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_addrof() #0 {
# | entry:
# |   %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_fam(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %2 = icmp sgt i64 %flexible_array_member_size, -1
# |   %3 = select i1 %2, i64 %flexible_array_member_size, i64 0
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %2 = icmp sgt i64 %result, -1
# |   %3 = and i1 true, %2
# |   %4 = select i1 %3, i64 %result, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bd086f456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bd086f1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bd086f4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9730449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97304a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9730449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9730431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd0868a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bd0868a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bd0866ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bd0831e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bd0831de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9730432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97304330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97304330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd0831dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (2632 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cedbb0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cedbaff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cedbb02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8522d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8522d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8522d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8522d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cedba9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cedba98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cedba7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cedb72c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cedb72be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8522d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8522d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8522d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cedb72bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (2633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc5c9b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dc5c9b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dc5c9b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f810a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f810a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f810a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f810a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc5c94c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dc5c94c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dc5c930f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dc5c5e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dc5c5dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f810a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f810a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f810a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc5c5dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (2634 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556adf24056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556adf23d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556adf240cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6252e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6252ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6252e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6252e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556adf1d623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556adf1d6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556adf1baf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556adee6a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556adee69e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6252e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6252e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6252e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556adee69d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (2635 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572e785b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005572e7858505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005572e785bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff354533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff35458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff354533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff35451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572e77f123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005572e77f1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005572e77d5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005572e7485166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005572e7484e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff35451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff35451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff35451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572e7484d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (2636 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0934df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d0934dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d0934dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f970dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f970dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f970dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f970dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d09347523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d093475086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d093459f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d093109166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d093108e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f970dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f970dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f970dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d093108d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (2637 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fcd3fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564fcd3f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564fcd3facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f07133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f0718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f07133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f0711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fcd39023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564fcd390086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564fcd374f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564fcd024166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564fcd023e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f0711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f0711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f0711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fcd023d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (2638 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056129536a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561295367505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056129536acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0312849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0312849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0312831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056129530023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561295300086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005612952e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561294f94166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561294f93e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0312832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03128330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561294f93d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (2639 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 5)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 5)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 18)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 3)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 11)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 7)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 4)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 19)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 7)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 15)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 31)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = lshr <16 x i8> %0, splat (i8 1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = lshr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = lshr <4 x i32> %0, splat (i32 10)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   ret <16 x i8> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   ret <4 x i32> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinlin
# | ...
# `---data was truncated (10240/66359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bac78856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557bac785505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557bac788cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ef4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ef44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ef4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ef4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bac71e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557bac71e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557bac702f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557bac3b2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557bac3b1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2ef4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ef44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ef44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bac3b1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (2640 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = or <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = or <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = or <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = or <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, al
# | ...
# `---data was truncated (10240/11056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596a88a656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005596a88a3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005596a88a6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa434933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa43498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa434933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa43491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596a883c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005596a883c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005596a8820f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005596a84d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005596a84cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa43491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa43491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa43491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596a84cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (2641 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560277a8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560277a84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560277a87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafbd61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafbd6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafbd61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafbd603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560277a1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560277a1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560277a01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005602776b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005602776b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fafbd604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafbd6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafbd6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602776b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (2642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f8ad5f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555f8ad5c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555f8ad5fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda9ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda9baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda9ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda9ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f8acf523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555f8acf5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555f8acd9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555f8a989166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555f8a988e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda9ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda9ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda9ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f8a988d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (2643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615d89b656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615d89b3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615d89b6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10d4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10d40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10d4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10d4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615d894c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615d894c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615d8930f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615d85e0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615d85dfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f10d4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10d40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10d40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615d85dfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (2644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627f010a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005627f0107505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005627f010acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0270933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f027098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0270933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f027091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627f00a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627f00a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005627f0084f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005627efd34166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005627efd33e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f027091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f027091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f027091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627efd33d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (2645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a27542256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a27541f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a275422cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91d641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91d64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91d641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91d6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2753b823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a2753b8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a27539cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a27504c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a27504be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f91d6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91d64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91d64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a27504bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (2646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <v
# | ...
# `---data was truncated (10240/28691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bea56bf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bea56bc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bea56bfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe058133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe05818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe058133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe05811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bea565523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bea5655086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bea5639f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bea52e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bea52e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe05811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe05811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe05811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bea52e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (2647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562faff5556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562faff52505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562faff55cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fbc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fbc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fbc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fbc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fafeeb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562fafeeb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562fafecff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562fafb7f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562fafb7ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3fbc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fbc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fbc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fafb7ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (2648 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align
# | ...
# `---data was truncated (10240/39627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd3100b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd31008505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd3100bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddeba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddebaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddeba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddeba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd30fa123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd30fa1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd30f85f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd30c35166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd30c34e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fddeba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddeba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddeba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd30c34d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (2649 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/136489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056266158956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562661586505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562661589cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f778a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f778a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f778a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f778a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056266151f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056266151f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562661503f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005626611b3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005626611b2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f778a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f778a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f778a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626611b2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (2650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d9e8ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d9e8ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d9e8edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa745a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa745aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa745a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa745a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d9e88323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d9e883086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d9e867f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d9e517166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d9e516e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa745a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa745a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa745a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d9e516d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (2651 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae03b7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ae03b72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ae03b75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f096b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f096b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f096b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f096b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae03b0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ae03b0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ae03aeff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ae0379f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ae0379ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f096b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f096b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f096b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae0379ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (2652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056415a58356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056415a580505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056415a583cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1bf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1bf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1bf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1bf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056415a51923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056415a519086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056415a4fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056415a1ad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056415a1ace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa1bf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1bf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1bf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056415a1acd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (2653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba42f4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ba42f40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ba42f43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7909c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7909c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7909c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7909c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba42ed923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ba42ed9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ba42ebdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ba42b6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ba42b6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7909c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7909c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7909c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba42b6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (2654 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c662eb556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c662eb2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c662eb5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0865d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0865d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0865d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0865d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c662e4b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c662e4b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c662e2ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c662adf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c662adee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0865d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0865d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0865d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c662aded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (2655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm
# | ...
# `---data was truncated (10240/35597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646b1c6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646b1c6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646b1c6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ee5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ee5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ee5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ee5aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646b1c0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646b1c03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646b1be7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646b1897166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646b1896e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0ee5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ee5aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ee5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646b1896d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (2656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580f2be756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005580f2be4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005580f2be7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33a3505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33a355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33a3505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33a34ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580f2b7d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005580f2b7d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005580f2b61f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005580f2811166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005580f2810e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f33a34eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33a34ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33a34ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580f2810d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (2657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f82bf456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f82bf1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f82bf4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f187b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f187b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f187b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f187b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f82b8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f82b8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f82b6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f8281e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f8281de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f187b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f187b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f187b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f8281dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (2658 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056322422256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056322421f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563224222cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94e2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94e2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94e2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94e2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632241b823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005632241b8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056322419cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563223e4c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563223e4be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f94e2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94e2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94e2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563223e4bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (2659 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea285a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea2859d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea285a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa673105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa67315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa673105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6730ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea2853623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea28536086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea2851af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea281ca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea281c9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa6730eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6730ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6730ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea281c9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (2660 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a415be56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a415bb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a415becab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f832bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f832bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f832bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f832bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a4155423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a41554086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a41538f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a411e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a411e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f832bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f832bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f832bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a411e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (2661 of 27911)
******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc    -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | $__profc__Z6helperi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6helperi = comdat any
# | 
# | $__profc__Z6kernelPi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6kernelPi = comdat any
# | 
# | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0
# | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8
# | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8
# | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1
# | @__start___llvm_prf_names = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_names = external hidden addrspace(1) global i8
# | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__start___llvm_prf_data = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_data = external hidden addrspace(1) global i8
# | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__llvm_profile_raw_version = external addrspace(1) constant i64
# | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version }
# | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %x.addr = alloca i32, align 4, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store i32 %x, ptr %x.addr.ascast, align 4
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load i32, ptr %x.addr.ascast, align 4
# |   %add = add nsw i32 %1, 1
# |   ret i32 %add
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
# | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %p = alloca ptr, align 8, addrspace(5)
# |   %p.addr = alloca ptr, align 8, addrspace(5)
# |   %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr
# |   store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8
# |   %p1 = load ptr, ptr addrspace(5) %p, align 8
# |   store ptr %p1, ptr %p.addr.ascast, align 8
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load ptr, ptr %p.addr.ascast, align 8
# |   %2 = load i32, ptr %1, align 4
# |   %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4
# |   %3 = load ptr, ptr %p.addr.ascast, align 8
# |   store i32 %call, ptr %3, align 4
# |   ret void
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | declare i32 @__llvm_profile_sampling_gpu(i32)
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3
# | 
# | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64)
# | 
# | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { nounwind }
# | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #4 = { convergent nounwind "uniform-work-group-size" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 2, !"EnableValueProfiling", i32 0}
# | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# |  #0 0x000055ac3868556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac38682505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac38685cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8ec61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8ec6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8ec61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8ec603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac3861b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac3861b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac385fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac382af166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac382aee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8ec604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8ec6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8ec6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac382aed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (2662 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfa
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce9f6e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ce9f6e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ce9f6e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f642f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f642f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f642f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f642f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce9f67d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ce9f67d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ce9f661f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ce9f311166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ce9f310e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f642f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f642f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f642f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce9f310d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (2663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb3133756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eb31334505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eb31337cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55da933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55da98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55da933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55da91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb312cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eb312cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eb312b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eb30f61166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eb30f60e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f55da91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55da91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55da91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb30f60d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (2664 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560845f2456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560845f21505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560845f24cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8c5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8c5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8c5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8c5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560845eba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560845eba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560845e9ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560845b4e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560845b4de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb8c5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8c5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8c5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560845b4dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (2665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbcd20b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fbcd208505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fbcd20bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d53449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d534a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d53449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d53431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbcd1a123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fbcd1a1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fbcd185f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fbcce35166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fbcce34e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d53432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d534330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d534330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbcce34d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (2666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ff7e6f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557ff7e6c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557ff7e6fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5c2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5c255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5c2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5c24ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ff7e0523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557ff7e05086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557ff7de9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557ff7a99166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557ff7a98e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff5c24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5c24ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5c24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ff7a98d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (2667 of 27911)
******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %class.Foo = type { i8 }
# | %class.HasTrivialDestructor = type { i8 }
# | %struct.Data = type { ptr }
# | %struct.HasNonTrivialCopyConstructor = type { i8 }
# | %struct.HasNonTrivialCopyConstructor2 = type { i8 }
# | %struct.LargeWithCopyConstructor = type { [32 x i8] }
# | %class.anon = type { i8 }
# | 
# | $_Z12TemplateFuncIiET_S0_ = comdat any
# | 
# | $_Z6Func10IiEii = comdat any
# | 
# | $_Z6Func12IiET_S0_ = comdat any
# | 
# | @pmf = global { i64, i64 } zeroinitializer, align 8
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %entry
# |   %1 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1)
# |   ret i32 %call
# | 
# | 2:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | if.else:                                          ; preds = %entry
# |   %3 = load i32, ptr %x.addr, align 4
# |   %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3)
# |   ret i32 %call1
# | 
# | 4:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %4, %2
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | declare noundef i32 @_Z3Bari(i32 noundef) #1
# | 
# | declare noundef i32 @_Z3Bazi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z3Bari(i32 noundef %0)
# |   %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call)
# |   ret i32 %call1
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.Foo, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local void @_Z5Func5v() #0 {
# | entry:
# |   musttail call void @_Z11ReturnsVoidv()
# |   ret void
# | 
# | 0:                                                ; No predecessors!
# |   ret void
# | }
# | 
# | declare void @_Z11ReturnsVoidv() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.HasTrivialDestructor, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 {
# | entry:
# |   %data.addr = alloca ptr, align 8
# |   store ptr %data, ptr %data.addr, align 8
# |   %0 = load ptr, ptr %data.addr, align 8
# |   %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %fptr, align 8
# |   %2 = load ptr, ptr %data.addr, align 8
# |   %call = musttail call noundef i32 %1(ptr noundef %2)
# |   ret i32 %call
# | 
# | 3:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat {
# | entry:
# |   %.addr = alloca i32, align 4
# |   store i32 %0, ptr %.addr, align 4
# |   ret i32 5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %t = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 {
# | entry:
# |   %x.ad
# | ...
# `---data was truncated (10240/18685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# |  #0 0x000055929ed3256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055929ed2f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055929ed32cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f263d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f263d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f263d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f263d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055929ecc823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055929ecc8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055929ecacf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055929e95c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055929e95be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f263d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f263d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f263d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055929e95bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (2668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f6599956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f65996505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f65999cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0db7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0db78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0db7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0db7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f6592f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f6592f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f65913f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f655c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f655c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0db7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0db78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0db78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f655c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (2669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055761336756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557613364505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557613367cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86fa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86fa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86fa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86fa431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576132fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576132fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576132e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557612f91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557612f90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f86fa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86fa4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86fa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557612f90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (2670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8
# | ...
# `---data was truncated (10240/24320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055869290956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558692906505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558692909cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e5e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e5e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e5e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e5e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055869289f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055869289f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558692883f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558692533166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558692532e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4e5e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e5e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e5e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558692532d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (2671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055baedbcd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055baedbca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055baedbcdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf13b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf13b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf13b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf13b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baedb6323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055baedb63086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055baedb47f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055baed7f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055baed7f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faf13b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf13b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf13b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baed7f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (2672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5d0ee056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5d0edd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5d0ee0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c96133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c9618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c96133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c9611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5d0e7623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5d0e76086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5d0e5af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5d0b0a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5d0b09e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8c9611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c9611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c9611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5d0b09d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (2673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/110070) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e43a0456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e43a01505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e43a04cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff34d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff34d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff34d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff34d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e4399a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e4399a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e4397ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e4362e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e4362de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff34d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff34d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff34d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e4362dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (2674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056070ca2756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056070ca24505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056070ca27cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1942533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f194258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1942533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f194251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056070c9bd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056070c9bd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056070c9a1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056070c651166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056070c650e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f194251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f194251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f194251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056070c650d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (2675 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652109f356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652109f0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652109f3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87e6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87e6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87e6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87e6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056521098923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565210989086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056521096df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056521061d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056521061ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87e6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87e6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87e6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056521061cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (2676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.
# | ...
# `---data was truncated (10240/30759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c41483d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c41483a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c41483dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb011d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb011d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb011d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb011d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4147d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c4147d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c4147b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c414467166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c414466e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb011d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb011d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb011d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c414466d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (2677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055821323056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055821322d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558213230cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4967449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4967449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4967431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582131c623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582131c6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582131aaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558212e5a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558212e59e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4967432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49674330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558212e59d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (2678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64)
# | ...
# `---data was truncated (10240/34765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4b8fd756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c4b8fd4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c4b8fd7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c02105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c0215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c02105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c020ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4b8f6d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c4b8f6d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c4b8f51f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c4b8c01166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c4b8c00e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4c020eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c020ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c020ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4b8c00d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (2679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a410ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559a410eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559a410eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd86d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd86d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd86d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd86d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a4108423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559a41084086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559a41068f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559a40d18166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559a40d17e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd86d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd86d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd86d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a40d17d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (2680 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c  -check-prefix=RV32ZBKB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.brev8.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @zip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.zip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @unzip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.unzip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.brev8.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.zip.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.unzip.i32(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056370f57a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056370f577505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056370f57acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cc4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cc478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cc4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cc471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056370f51023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056370f510086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056370f4f4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056370f1a4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056370f1a3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4cc471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cc471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cc471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056370f1a3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (2681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# | ...
# `---data was truncated (10240/30866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b98749f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b98749c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b98749fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17bee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17beea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17bee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17bee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b98743523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b987435086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b987419f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9870c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9870c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f17bee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17bee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17bee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9870c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (2682 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560af843056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560af842d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560af8430cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9d2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9d24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9d2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9d2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560af83c623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560af83c6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560af83aaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560af805a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560af8059e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc9d2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9d24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9d24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560af8059d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (2683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x 
# | ...
# `---data was truncated (10240/30682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a3549a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557a35497505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557a3549acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f548bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f548bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f548bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f548bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a3543023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557a35430086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557a35414f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557a350c4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557a350c3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f548bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f548bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f548bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a350c3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (2684 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055714821156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055714820e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557148211cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafc3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafc3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafc3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafc3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571481a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571481a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055714818bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557147e3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557147e3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fafc3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafc3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafc3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557147e3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (2685 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, al
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f59fc9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f59fc99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f59fc9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4837e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4837ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4837e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4837e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f59fc3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f59fc32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f59fc16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f59f8c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f59f8c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4837e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4837e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4837e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f59f8c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (2686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7c7f0c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7c7f09505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7c7f0ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a94649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a946a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a94649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a94631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7c7ea223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7c7ea2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7c7e86f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7c7b36166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7c7b35e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4a94632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a946330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a946330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7c7b35d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (2687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedo
# | ...
# `---data was truncated (10240/30751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b7ffb656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b7ffb3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b7ffb6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79b7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79b718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79b7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79b711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b7ff4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b7ff4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b7ff30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b7fbe0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b7fbdfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f79b711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79b711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79b711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b7fbdfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (2688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f89465456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f894651505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f894654cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17c6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17c6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17c6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17c6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8945ea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f8945ea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f8945cef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f89427e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f89427de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f17c6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17c6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17c6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f89427dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (2689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/79861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055effd85d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055effd85a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055effd85dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac6a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac6a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac6a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac6a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055effd7f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055effd7f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055effd7d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055effd487166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055effd486e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac6a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac6a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac6a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055effd486d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (2690 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650dd0f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005650dd0f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005650dd0f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf61449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf614a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf61449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf61431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650dd08d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005650dd08d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005650dd071f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005650dcd21166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005650dcd20e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdf61432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf614330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf614330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650dcd20d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (2691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, 
# | ...
# `---data was truncated (10240/211231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea0a48556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ea0a482505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ea0a485cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16bf105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16bf15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16bf105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16bf0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea0a41b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ea0a41b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ea0a3fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ea0a0af166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ea0a0aee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f16bf0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16bf0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16bf0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea0a0aed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (2692 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target
# | ...
# `---data was truncated (10240/23439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b1ba9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b1ba94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b1ba97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ef8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ef818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ef8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ef811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b1ba2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b1ba2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b1ba11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b1b6c1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b1b6c0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ef811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ef811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ef811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b1b6c0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (2693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<
# | ...
# `---data was truncated (10240/11404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3953f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a3953f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a3953f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f653d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f653d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f653d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f653d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a39538c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a39538c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a395370f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a395020166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a39501fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f653d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f653d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f653d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a39501fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (2694 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562af495656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562af4953505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562af4956cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13b4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13b48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13b4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13b4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562af48ec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562af48ec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562af48d0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562af4580166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562af457fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f13b4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13b48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13b48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562af457fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (2695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e1c60f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564e1c60c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564e1c60fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f260a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f260a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f260a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f260a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e1c5a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564e1c5a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564e1c589f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564e1c239166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564e1c238e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f260a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f260a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f260a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e1c238d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (2696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609e455656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005609e4553505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005609e4556cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9093733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f909378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9093733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f909371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609e44ec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005609e44ec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005609e44d0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005609e4180166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005609e417fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f909371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f909371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f909371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609e417fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (2697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c13cec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c13ce9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c13ceccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2779a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2779aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2779a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2779a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c13c8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c13c82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c13c66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c13916166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c13915e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2779a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2779a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2779a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c13915d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (2698 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d1aaee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d1aaeb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d1aaeecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0217f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0217f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0217f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0217eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d1aa8423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d1aa84086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d1aa68f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d1a718166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d1a717e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0217eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0217eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0217eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d1a717d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (2699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd230cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dd230c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dd230cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c1603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd2306223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dd23062086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dd23046f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dd22cf6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dd22cf5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f05c1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c16050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd22cf5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (2700 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed6b55256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed6b54f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed6b552cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab09733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab0978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab09733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab0971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed6b4e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed6b4e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed6b4ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed6b17c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed6b17be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab0971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab0971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab0971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed6b17bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (2701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055803cf7256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055803cf6f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055803cf72cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa240905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa24095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa240905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2408ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055803cf0823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055803cf08086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055803ceecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055803cb9c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055803cb9be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa2408eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2408ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2408ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055803cb9bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (2702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.add
# | ...
# `---data was truncated (10240/14453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565a107556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565a1072505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565a1075cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b0a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b0a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b0a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b0a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565a100b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565a100b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565a0feff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565a0c9f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565a0c9ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b0a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b0a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b0a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565a0c9ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (2703 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055889b69856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055889b695505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055889b698cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f550cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f550cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f550cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f550cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055889b62e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055889b62e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055889b612f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055889b2c2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055889b2c1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f550cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f550cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f550cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055889b2c1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (2704 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610d1c4d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005610d1c4a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005610d1c4dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb39c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb39c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb39c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb39c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610d1be323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005610d1be3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005610d1bc7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005610d1877166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005610d1876e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb39c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb39c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb39c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610d1876d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (2705 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ed98b156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ed98ae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ed98b1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0c481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0c48725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0c481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0c4803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ed984723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ed9847086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ed982bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ed94db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ed94dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa0c4804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0c48050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0c48050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ed94dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (2706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558bdfa456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558bdfa1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558bdfa4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3721449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37214a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3721449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3721431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558bdf3a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005558bdf3a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005558bdf1ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558bdbce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558bdbcde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3721432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37214330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37214330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558bdbcdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (2707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be2b27a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be2b277505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be2b27acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f085d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f085d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f085d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f085d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be2b21023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be2b210086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be2b1f4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be2aea4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be2aea3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f085d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f085d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f085d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be2aea3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (2708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <v
# | ...
# `---data was truncated (10240/50890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bb051d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bb051a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bb051dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f824d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f824d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f824d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f824d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bb04b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bb04b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bb0497f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bb0147166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bb0146e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f824d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f824d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f824d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bb0146d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (2709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ec05ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563ec05fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563ec05ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9122333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f912238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9122333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f912231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ec059523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563ec0595086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563ec0579f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563ec0229166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563ec0228e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f912231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f912231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f912231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ec0228d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (2710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7fe0b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f7fe0b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f7fe0b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe44ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe44ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe44ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe44ec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7fe04d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f7fe04d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f7fe031f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7fdce1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7fdce0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe44ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe44ec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe44ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7fdce0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (2711 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | defin
# | ...
# `---data was truncated (10240/13035) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efe7e2b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055efe7e28505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055efe7e2bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32b8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32b8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32b8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32b8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efe7dc123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055efe7dc1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055efe7da5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055efe7a55166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055efe7a54e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f32b8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32b8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32b8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efe7a54d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (2712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/40883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acc21cf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055acc21cc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055acc21cfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93ba849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93ba8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93ba849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93ba831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acc216523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055acc2165086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055acc2149f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055acc1df9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055acc1df8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f93ba832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93ba8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93ba8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acc1df8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (2713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa8ffd456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa8ffd1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa8ffd4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f095d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f095d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f095d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f095d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa8ff6a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa8ff6a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa8ff4ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa8fbfe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa8fbfde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f095d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f095d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f095d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa8fbfdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (2714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c  -check-prefix=RV64ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0153ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f0153cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f0153cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1fc01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1fc0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1fc01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1fc003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f01536423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f015364086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f015348f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f014ff8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f014ff7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe1fc004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1fc0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1fc0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f014ff7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (2715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564948af456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564948af1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564948af4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43b1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43b1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43b1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43b1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564948a8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564948a8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564948a6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056494871e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056494871de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f43b1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43b1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43b1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056494871dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (2716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559be59b156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559be59ae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559be59b1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8a2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559be594723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559be5947086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559be592bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559be55db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559be55dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff8a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8a24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559be55dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (2717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578bee1056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578bee0d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578bee10cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8215b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8215b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8215b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8215b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578beda623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578beda6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578bed8af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578bea3a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578bea39e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8215b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8215b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8215b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578bea39d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (2718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556acc58956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556acc586505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556acc589cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d9c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d9c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d9c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d9c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556acc51f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556acc51f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556acc503f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556acc1b3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556acc1b2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d9c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d9c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d9c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556acc1b2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (2719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588ba3a556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005588ba3a2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005588ba3a5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0736e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0736ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0736e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0736e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588ba33b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005588ba33b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005588ba31ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005588b9fcf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005588b9fcee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0736e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0736e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0736e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588b9fced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (2720 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608f81f256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005608f81ef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005608f81f2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd723d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd723d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd723d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd723d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608f818823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005608f8188086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005608f816cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005608f7e1c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005608f7e1be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd723d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd723d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd723d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608f7e1bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (2721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd1d37d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cd1d37a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cd1d37dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bcc105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bcc15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bcc105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bcc0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd1d31323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cd1d313086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cd1d2f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cd1cfa7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cd1cfa6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0bcc0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bcc0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bcc0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd1cfa6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (2722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600db28156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005600db27e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005600db281cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb0c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb0c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb0c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb0c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600db21723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005600db217086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005600db1fbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005600daeab166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005600daeaae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb0c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb0c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb0c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600daeaad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (2723 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564840c8656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564840c83505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564840c86cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3706d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3706d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3706d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3706d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564840c1c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564840c1c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564840c00f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005648408b0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005648408afe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3706d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3706d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3706d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648408afd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (2724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d95dc2256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d95dc1f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d95dc22cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff75d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff75d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff75d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff75d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d95dbb823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d95dbb8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d95db9cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d95d84c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d95d84be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff75d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff75d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff75d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d95d84bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (2725 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574e112156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005574e111e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005574e1121cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff286a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff286aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff286a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff286a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574e10b723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005574e10b7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005574e109bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005574e0d4b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005574e0d4ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff286a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff286a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff286a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574e0d4ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (2726 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c  -check-prefix=RV64ZKND-ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b0887f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b0887c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b0887fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2d3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2d3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2d3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2d3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b0881523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b08815086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b087f9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b084a9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b084a8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd2d3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2d3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2d3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b084a8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (2727 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, alig
# | ...
# `---data was truncated (10240/32578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eeccaa656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eeccaa3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eeccaa6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feae0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feae0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feae0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feae0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eecca3c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eecca3c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eecca20f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eecc6d0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eecc6cfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feae0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feae0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feae0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eecc6cfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (2728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ff563d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ff563a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ff563dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7fec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7feca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7fec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7fec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ff55d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ff55d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ff55b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ff5267166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ff5266e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7fec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7fec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7fec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ff5266d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (2729 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/79071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7459a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7459a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7459a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f452dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f452dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f452dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f452dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e74593a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e74593a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e74591ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7455ce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7455cde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f452dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f452dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f452dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7455cdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (2730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586f72c956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005586f72c6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005586f72c9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1af2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1af2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1af2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1af2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586f725f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005586f725f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005586f7243f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586f6ef3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586f6ef2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1af2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1af2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1af2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586f6ef2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (2731 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ce7b9a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ce7b97505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ce7b9acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc231933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc23198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc231933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc23191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ce7b3023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ce7b30086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ce7b14f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ce77c4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ce77c3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc23191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc23191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc23191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ce77c3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (2732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, a
# | ...
# `---data was truncated (10240/28358) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589a133956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589a1336505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589a1339cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39caa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39caa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39caa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39caa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589a12cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589a12cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589a12b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589a0f63166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589a0f62e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f39caa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39caa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39caa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589a0f62d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (2733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056492e37f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056492e37c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056492e37fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b6c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b6c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b6c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b6c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056492e31523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056492e315086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056492e2f9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056492dfa9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056492dfa8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b6c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b6c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b6c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056492dfa8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (2734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055797afd856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055797afd5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055797afd8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4a5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4a5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4a5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4a5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055797af6e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055797af6e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055797af52f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055797ac02166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055797ac01e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4a5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4a5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4a5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055797ac01d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (2735 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0a28ee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d0a28eb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d0a28eecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42bec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42bec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42bec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42bec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0a288423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d0a2884086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d0a2868f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d0a2518166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d0a2517e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f42bec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42bec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42bec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0a2517d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (2736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff45fba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ff45fb7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ff45fbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5652b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5652b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5652b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5652b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff45f5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ff45f50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ff45f34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ff45be4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ff45be3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5652b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5652b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5652b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff45be3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (2737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f3c90756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f3c904505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f3c907cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c3bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c3bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c3bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c3bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f3c89d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f3c89d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f3c881f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f3c531166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f3c530e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c3bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c3bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c3bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f3c530d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (2738 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d38e9cf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d38e9cc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d38e9cfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0869f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0869f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0869f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0869f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d38e96523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d38e965086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d38e949f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d38e5f9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d38e5f8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0869f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0869f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0869f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d38e5f8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (2739 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/33772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055740916e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055740916b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055740916ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9382533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f938258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9382533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f938251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055740910423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557409104086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005574090e8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557408d98166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557408d97e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f938251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f938251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f938251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557408d97d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (2740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale 
# | ...
# `---data was truncated (10240/13048) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc40dee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc40deb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc40deecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73a4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc40d8423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc40d84086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc40d68f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc40a18166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc40a17e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f73a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73a4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc40a17d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (2741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmset_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmset_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmset_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmset_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmset_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmset_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmset_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ef523056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564ef522d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564ef5230cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7f2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7f22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7f2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7f2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ef51c623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564ef51c6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564ef51aaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ef4e5a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ef4e59e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa7f2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7f22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7f22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ef4e59d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (2742 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale
# | ...
# `---data was truncated (10240/11640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fef34c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556fef349505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556fef34ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f815e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f815e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f815e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f815e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fef2e223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556fef2e2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556fef2c6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556feef76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556feef75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f815e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f815e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f815e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556feef75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (2743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaadd_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d00906d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d00906a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d00906dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61bc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61bc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61bc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61bc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d00900323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d009003086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d008fe7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d008c97166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d008c96e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61bc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61bc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61bc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d008c96d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (2744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   
# | ...
# `---data was truncated (10240/23061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562aebce356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562aebce0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562aebce3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6312c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6312ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6312c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6312c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aebc7923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562aebc79086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562aebc5df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562aeb90d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562aeb90ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6312c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6312c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6312c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562aeb90cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (2745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccd8f4b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccd8f48505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccd8f4bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90dfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90dfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90dfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90dfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccd8ee123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccd8ee1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccd8ec5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ccd8b75166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ccd8b74e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f90dfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90dfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90dfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccd8b74d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (2746 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5fa90a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f5fa907505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f5fa90acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd8e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd8e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd8e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd8e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5fa8a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5fa8a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5fa884f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f5fa534166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f5fa533e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd8e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd8e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd8e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5fa533d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (2747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align
# | ...
# `---data was truncated (10240/14145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fb83cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555fb83c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555fb83cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb28849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb288a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb28849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb28831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fb836223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555fb8362086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555fb8346f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555fb7ff6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555fb7ff5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb28832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb288330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb288330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fb7ff5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (2748 of 27911)
******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32-unknown-unknown"
# | 
# | %struct.asc = type { i8, i16, i32, i32, float, double }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %0 = load i32, ptr %argp.next, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16
# |   store ptr %argp.next2, ptr %va, align 4
# |   %2 = load double, ptr %1, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %2
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11
# |   %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load i32, ptr %argp.next, align 8, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0)
# |   store <2 x i64> %call, ptr %r, align 16, !tbaa !9
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr n
# | ...
# `---data was truncated (10240/20646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default<O1>) --expand-variadics-override=optimize -o -
# |  #0 0x000055610875156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055610874e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556108751cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaf9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaf9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaf9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaf9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561086e723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561086e7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561086cbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055610837b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055610837ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdaf9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaf9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaf9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055610837ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (2749 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b91de6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b91de63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b91de66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9957d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9957d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9957d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9957d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b91ddfc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b91ddfc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b91dde0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b91da90166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b91da8fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9957d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9957d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9957d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b91da8fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (2750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648317f956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005648317f6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005648317f9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82c4a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82c4a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82c4a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82c4a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056483178f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056483178f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564831773f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564831423166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564831422e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82c4a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82c4a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82c4a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564831422d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (2751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d98bf4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d98bf43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d98bf46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fade2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fade238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fade2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fade231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d98bedc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d98bedc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d98bec0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d98bb70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d98bb6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fade231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fade231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fade231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d98bb6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (2752 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e4cab556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e4cab2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e4cab5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80b5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80b578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80b5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80b571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e4ca4b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e4ca4b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e4ca2ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e4c6df166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e4c6dee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f80b571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80b571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80b571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e4c6ded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (2753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 64 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, al
# | ...
# `---data was truncated (10240/30013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7dc4f456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7dc4f1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7dc4f4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e0c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e0c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e0c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e0c8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7dc48a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7dc48a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7dc46ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7dc11e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7dc11de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1e0c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e0c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e0c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7dc11dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (2754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d93ceb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d93ce8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d93cebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e7cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e7cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e7cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e7caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d93c8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d93c81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d93c65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d93915166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d93914e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e7caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e7caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e7caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d93914d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (2755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bff20a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bff209f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bff20a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdccf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bff203823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bff2038086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bff201cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bff1ccc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bff1ccbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcdccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bff1ccbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (2756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557acb6656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005557acb63505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005557acb66cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e32849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e328a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e32849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e32831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557acafc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005557acafc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005557acae0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005557ac790166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005557ac78fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e32832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e328330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e328330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557ac78fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (2757 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/62752) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055586aa9556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055586aa92505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055586aa95cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf02e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf02ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf02e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf02e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055586aa2b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055586aa2b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055586aa0ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055586a6bf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055586a6bee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdf02e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf02e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf02e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055586a6bed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (2758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddd472956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ddd4726505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ddd4729cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f901ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f901ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f901ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f901ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddd46bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ddd46bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ddd46a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ddd4353166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ddd4352e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f901ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f901ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f901ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddd4352d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (2759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e8168056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e8167d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e81680cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51c9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51c9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51c9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51c9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e8161623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e81616086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e815faf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e812aa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e812a9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f51c9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51c9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51c9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e812a9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (2760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055801705256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055801704f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558017052cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4547f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4547f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4547f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4547f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558016fe823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558016fe8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558016fccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558016c7c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558016c7be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4547f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4547f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4547f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558016c7bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (2761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.a
# | ...
# `---data was truncated (10240/38299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf6849356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf68490505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf68493cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7aa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7aa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7aa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7aa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf6842923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf68429086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf6840df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf680bd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf680bce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7aa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7aa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7aa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf680bcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (2762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc5596256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fc5595f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fc55962cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ac0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ac0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ac0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ac0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc558f823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fc558f8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fc558dcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fc5558c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fc5558be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ac0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ac0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ac0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc5558bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (2763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617b752956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005617b7526505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005617b7529cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff503049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5030a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff503049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff503031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617b74bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005617b74bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005617b74a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005617b7153166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005617b7152e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff503032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5030330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5030330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617b7152d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (2764 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563be89d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563be89d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563be89d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc27a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc27a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc27a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc27a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563be896b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563be896b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563be894ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563be85ff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563be85fee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc27a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc27a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc27a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563be85fed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (2765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/112825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640f639056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640f638d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640f6390cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e1ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e1ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e1ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e1ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640f632623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640f6326086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640f630af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640f5fba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640f5fb9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e1ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e1ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e1ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640f5fb9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (2766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/43515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eb936856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564eb9365505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564eb9368cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe85a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe85a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe85a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe85a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eb92fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564eb92fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564eb92e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564eb8f92166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564eb8f91e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe85a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe85a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe85a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eb8f91d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (2767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdb76f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bdb76f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bdb76f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99f5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99f518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99f5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99f511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdb768d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bdb768d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bdb7671f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bdb7321166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bdb7320e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f99f511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99f511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99f511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdb7320d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (2768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = ashr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = lshr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = ashr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = lshr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @lshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %shl = shl <8 x i32> %0, %1
# |   store <8 x i32> %shl, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @rshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %r
# | ...
# `---data was truncated (10240/50943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055f50734556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f507342505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f507345cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc99733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc9978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc99733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc9971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5072db23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f5072db086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f5072bff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f506f6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f506f6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc9971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc9971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc9971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f506f6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (2769 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055929560e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055929560b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055929560ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4251049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42510a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4251049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4251031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592955a423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005592955a4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559295588f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559295238166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559295237e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4251032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42510330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42510330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559295237d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (2770 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/41659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056330ec7b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056330ec78505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056330ec7bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb66961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6696725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb66961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb669603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056330ec1123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056330ec11086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056330ebf5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056330e8a5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056330e8a4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb669604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6696050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6696050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056330e8a4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (2771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0,
# | ...
# `---data was truncated (10240/28346) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9e858256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d9e857f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d9e8582cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e0fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e0faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e0fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e0fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9e851823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9e8518086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9e84fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9e81ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9e81abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e0fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e0fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e0fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9e81abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (2772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561050dfd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561050dfa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561050dfdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40a1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40a16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40a1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40a1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561050d9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561050d93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561050d77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561050a27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561050a26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f40a1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40a16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40a16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561050a26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (2773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560eb018756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560eb0184505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560eb0187cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facca933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facca98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facca933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facca91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560eb011d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560eb011d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560eb0101f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560eafdb1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560eafdb0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007facca91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facca91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facca91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560eafdb0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (2774 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aac243956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aac2436505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aac2439cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effd8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effd88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effd8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effd8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aac23cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aac23cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aac23b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aac2063166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aac2062e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007effd8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effd88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effd88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aac2062d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (2775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nx
# | ...
# `---data was truncated (10240/25567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bc0fda56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562bc0fd7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562bc0fdacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb953f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb953f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb953f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb953eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bc0f7023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562bc0f70086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562bc0f54f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562bc0c04166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562bc0c03e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb953eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb953eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb953eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bc0c03d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (2776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccb320a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ccb3207505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ccb320acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f234781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23478725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f234781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2347803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccb31a023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ccb31a0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ccb3184f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ccb2e34166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ccb2e33e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2347804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23478050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23478050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccb2e33d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (2777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa9305956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa93056505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa93059cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9072649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90726a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9072649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9072631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa92fef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa92fef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa92fd3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa92c83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa92c82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9072632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90726330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90726330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa92c82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (2778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dee6d1d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dee6d1a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dee6d1dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feef8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feef8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feef8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feef8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dee6cb323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dee6cb3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dee6c97f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dee6947166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dee6946e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feef8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feef8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feef8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dee6946d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (2779 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557339d1156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557339d0e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557339d11cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff913905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff91395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff913905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9138ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557339ca723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557339ca7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557339c8bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055733993b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055733993ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff9138eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9138ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9138ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055733993ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (2780 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e858b056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e858ad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e858b0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d92305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d9235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d92305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d922ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e8584623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e85846086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e8582af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e854da166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e854d9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d922eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d922ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d922ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e854d9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (2781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vs
# | ...
# `---data was truncated (10240/23775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e3f62a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e3f627505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e3f62acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f858bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f858bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f858bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f858bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e3f5c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e3f5c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e3f5a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e3f254166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e3f253e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f858bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f858bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f858bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e3f253d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (2782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee314be56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee314bb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee314becab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cc0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cc058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cc0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cc051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee3145423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee31454086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee31438f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee310e8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee310e7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5cc051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cc051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cc051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee310e7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (2783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee69d2556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee69d22505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee69d25cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6064849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60648a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6064849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6064831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee69cbb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee69cbb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee69c9ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee6994f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee6994ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6064832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60648330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60648330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee6994ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (2784 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3
# | ...
# `---data was truncated (10240/14330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd8dbdb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fd8dbd8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fd8dbdbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5446d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5446d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5446d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5446d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd8db7123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fd8db71086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fd8db55f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fd8d805166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fd8d804e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5446d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5446d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5446d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd8d804d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (2785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = c
# | ...
# `---data was truncated (10240/41433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056332a1ab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056332a1a8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056332a1abcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe817933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe81798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe817933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe81791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056332a14123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056332a141086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056332a125f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563329dd5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563329dd4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe81791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe81791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe81791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563329dd4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (2786 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9c861656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e9c8613505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e9c8616cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d1e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d1e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d1e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d1e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9c85ac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e9c85ac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9c8590f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e9c8240166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e9c823fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d1e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d1e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d1e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9c823fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (2787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055993200b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559932008505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055993200bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd09d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd09d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd09d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd09d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559931fa123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559931fa1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559931f85f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559931c35166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559931c34e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd09d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd09d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd09d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559931c34d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (2788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612b5ca556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005612b5ca2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005612b5ca5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b5f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b5f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b5f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b5f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612b5c3b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005612b5c3b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005612b5c1ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005612b58cf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005612b58cee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7b5f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b5f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b5f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612b58ced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (2789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622a21a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005622a219d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005622a21a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc141449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1414a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc141449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc141431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622a213623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005622a2136086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005622a211af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005622a1dca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005622a1dc9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc141432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1414330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1414330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622a1dc9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (2790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563495f2d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563495f2a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563495f2dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f779c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f779c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f779c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f779c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563495ec323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563495ec3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563495ea7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563495b57166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563495b56e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f779c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f779c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f779c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563495b56d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (2791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdb387656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bdb3873505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bdb3876cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dff431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdb380c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bdb380c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bdb37f0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bdb34a0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bdb349fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3dff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dff4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdb349fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (2792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561aa38e356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561aa38e0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561aa38e3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd189849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1898a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd189849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd189831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aa387923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561aa3879086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561aa385df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561aa350d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561aa350ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd189832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1898330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1898330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aa350cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (2793 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabi"
# | 
# | %struct.Simple = type { i8, i8 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldrex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldaex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_strex(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %res = alloca i32, align 4
# |   %var = alloca %struct.Simple, align 1
# |   %tmp = alloca i64, align 8
# |   %tmp8 = alloca double, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i32 0, ptr %res, align 4
# |   call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false)
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0)
# |   %1 = load i32, ptr %res, align 4
# |   %or = or i32 %1, %strex
# |   store i32 %or, ptr %res, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2)
# |   %3 = load i32, ptr %res, align 4
# |   %or2 = or i32 %3, %strex1
# |   store i32 %or2, ptr %res, align 4
# |   %4 = load ptr, ptr %addr.addr, align 4
# |   %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4)
# |   %5 = load i32, ptr %res, align 4
# |   %or4 = or i32 %5, %strex3
# |   store i32 %or4, ptr %res, align 4
# |   store i64 42, ptr %tmp, align 8
# |   %6 = load { i32, i32 }, ptr %tmp, align 8
# |   %7 = extractvalue { i32, i32 } %6, 0
# |   %8 = extractvalue { i32, i32 } %6, 1
# |   %9 = load ptr, ptr %addr.addr, align 4
# |   %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9)
# |   %10 = load i32, ptr %res, align 4
# |   %or5 = or i32 %10, %strexd
# |   store i32 %or5, ptr %res, align 4
# |   %11 = load ptr, ptr %addr.addr, align 4
# |   %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11)
# |   %12 = load i32, ptr %res, align 4
# |   %or7 = or i32 %12, %strex6
# |   store i32 %or7, ptr %res, align 4
# |   store double 3.141590e+00, ptr %tmp8, align 8
# |   %13 = load { i32, i32 }, ptr %tmp8, align 8
# |   %14 = extractvalue { i32, i32 } %13, 0
# |   %15 = extractvalue { i32, i32 } %13, 1
# |   %16 = load ptr, ptr %addr.addr, align 4
# |   %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16)
# |   %17 = load i32, ptr %res, align 4
# |   %or10 = or i32 %17, %strexd9
# |   store i32 %or10, ptr %res, align 4
# |   %18 = load ptr, ptr %addr.addr, ali
# | ...
# `---data was truncated (10240/16971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2757a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b2757a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b2757a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feff2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feff20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feff2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feff2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b27573a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b27573a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b27571ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b2753ce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b2753cde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feff2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feff20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feff20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2753cdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (2794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | 
# | ...
# `---data was truncated (10240/40891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da880fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055da880f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055da880facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd63d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd63d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd63d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd63d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da8809023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055da88090086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055da88074f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055da87d24166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055da87d23e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd63d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd63d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd63d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da87d23d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (2795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a83cd4c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a83cd49505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a83cd4ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5df361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5df36725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5df361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5df3603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a83cce223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a83cce2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a83ccc6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a83c976166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a83c975e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5df3604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5df36050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5df36050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a83c975d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (2796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c  -check-prefix=RV32ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa8d52956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa8d526505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa8d529cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f73a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f73aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f73a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f73a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa8d4bf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa8d4bf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa8d4a3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa8d153166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa8d152e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f73a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f73a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f73a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa8d152d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (2797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr,
# | ...
# `---data was truncated (10240/30874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc4bc1656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fc4bc13505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fc4bc16cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc4bbac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fc4bbac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fc4bb90f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fc4b840166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fc4b83fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007febca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc4b83fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (2798 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64
# | ...
# `---data was truncated (10240/97248) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056069b36a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056069b367505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056069b36acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9822b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9822b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9822b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9822b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056069b30023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056069b300086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056069b2e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056069af94166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056069af93e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9822b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9822b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9822b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056069af93d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (2799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/58326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557786d8256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557786d7f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557786d82cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd6ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd6ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd6ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd6ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557786d1823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557786d18086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557786cfcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005577869ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005577869abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efd6ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd6ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd6ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577869abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (2800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6a8fd556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f6a8fd2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f6a8fd5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc04d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc04d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc04d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc04d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6a8f6b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f6a8f6b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f6a8f4ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f6a8bff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f6a8bfee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc04d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc04d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc04d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6a8bfed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (2801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629d61f656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005629d61f3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005629d61f6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f4a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f4a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f4a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f4a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629d618c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005629d618c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005629d6170f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005629d5e20166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005629d5e1fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9f4a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f4a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f4a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629d5e1fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (2802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/34581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4123ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b4123cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b4123cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47e9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47e9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47e9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47e9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b41236423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b412364086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b412348f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b411ff8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b411ff7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47e9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47e9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47e9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b411ff7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (2803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde
# | ...
# `---data was truncated (10240/16083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f35cd856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f35cd5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f35cd8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf8c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf8c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf8c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf8c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f35c6e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f35c6e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f35c52f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f35902166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f35901e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faf8c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf8c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf8c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f35901d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (2804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056259c34456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056259c341505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056259c344cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ecc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ecc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ecc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ecc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056259c2da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056259c2da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056259c2bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056259bf6e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056259bf6de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ecc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ecc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ecc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056259bf6dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (2805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598ceff956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005598ceff6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005598ceff9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f584f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f584f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f584f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f584f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598cef8f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005598cef8f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005598cef73f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005598cec23166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005598cec22e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f584f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f584f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f584f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598cec22d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (2806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,10
# | ...
# `---data was truncated (10240/48393) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641fbef456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005641fbef1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005641fbef4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4711249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47112a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4711249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4711231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641fbe8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005641fbe8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005641fbe6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005641fbb1e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005641fbb1de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4711232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47112330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47112330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641fbb1dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (2807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653e0ff656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005653e0ff3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005653e0ff6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fbe533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fbe58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fbe533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fbe51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653e0f8c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005653e0f8c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005653e0f70f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005653e0c20166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005653e0c1fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3fbe51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fbe51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fbe51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653e0c1fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (2808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624da04056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005624da03d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005624da040cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3b5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3b5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3b5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3b5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624d9fd623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005624d9fd6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005624d9fbaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005624d9c6a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005624d9c69e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc3b5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3b5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3b5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624d9c69d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (2809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f4480756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f44804505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f44807cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47cc81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47cc8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47cc81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47cc803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f4479d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f4479d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f44781f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f44431166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f44430e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47cc804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47cc8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47cc8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f44430d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (2810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e437fb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e437f8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e437fbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1780a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1780aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1780a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1780a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e4379123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e43791086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e43775f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e43425166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e43424e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1780a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1780a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1780a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e43424d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto-multi-module.ll (2811 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# |  #0 0x00005562cf92056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005562cf91d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005562cf920cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2967933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f296798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2967933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f296791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562cf8b623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005562cf8b6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005562cf89af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005562cf54a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005562cf549e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f296791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f296791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f296791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562cf549d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (2812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647028ba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005647028b7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005647028bacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d71049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d710a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d71049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d71031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056470285023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564702850086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564702834f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005647024e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005647024e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d71032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d710330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d710330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647024e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (2813 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff6258056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ff6257d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ff62580cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f392f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f392f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f392f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f392f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff6251623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ff62516086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ff624faf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ff621aa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ff621a9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f392f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f392f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f392f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff621a9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (2814 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056107790f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056107790c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056107790fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97fb105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97fb15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97fb105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97fb0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610778a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005610778a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561077889f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561077539166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561077538e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f97fb0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97fb0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97fb0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561077538d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (2815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |  
# | ...
# `---data was truncated (10240/43478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560073afa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560073af7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560073afacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc1281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc128725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc1281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc12803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560073a9023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560073a90086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560073a74f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560073724166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560073723e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc12804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc128050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc128050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560073723d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (2816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610d3df456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005610d3df1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005610d3df4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09eb505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09eb55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09eb505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09eb4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610d3d8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005610d3d8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005610d3d6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005610d3a1e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005610d3a1de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f09eb4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09eb4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09eb4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610d3a1dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (2817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1
# | ...
# `---data was truncated (10240/19049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c291f7156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c291f6e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c291f71cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc3ca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc3ca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc3ca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc3ca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c291f0723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c291f07086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c291eebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c291b9b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c291b9ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc3ca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc3ca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc3ca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c291b9ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (2818 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cd34a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cd349d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cd34a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa487249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4872a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa487249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa487231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cd343623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cd3436086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cd341af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cd30ca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cd30c9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa487232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4872330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4872330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cd30c9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (2819 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da147ae56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055da147ab505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055da147aecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d4b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d4b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d4b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d4b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da1474423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055da14744086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055da14728f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055da143d8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055da143d7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d4b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d4b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d4b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da143d7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (2820 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a447fb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a447f8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a447fbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1a0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1a00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1a0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1a0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a4479123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a44791086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a44775f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a44425166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a44424e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd1a0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1a00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1a00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a44424d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (2821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c554bad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c554baa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c554badcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d8e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d8e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d8e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d8e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c554b4323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c554b43086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c554b27f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5547d7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5547d6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6d8e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d8e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d8e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5547d6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (2822 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b4a88256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559b4a87f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559b4a882cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2df4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2df418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2df4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2df411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b4a81823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559b4a818086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559b4a7fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559b4a4ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559b4a4abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2df411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2df411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2df411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b4a4abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (2823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbe068e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dbe068b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dbe068ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f302bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f302bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f302bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f302bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbe062423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dbe0624086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dbe0608f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dbe02b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dbe02b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f302bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f302bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f302bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbe02b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (2824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f57a1956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f57a16505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f57a19cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb8c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb8c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb8c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb8c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f579af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f579af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f57993f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f57643166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f57642e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb8c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb8c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb8c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f57642d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (2825 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b61ba7156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b61ba6e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b61ba71cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf52649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf526a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf52649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf52631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b61ba0723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b61ba07086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b61b9ebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b61b69b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b61b69ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcf52632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf526330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf526330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b61b69ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (2826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574709ea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005574709e7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005574709eacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feec4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feec48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feec4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feec4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055747098023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557470980086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557470964f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557470614166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557470613e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feec4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feec48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feec48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557470613d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (2827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a89976c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a899769505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a89976ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8f0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8f08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8f0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8f0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a89970223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a899702086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a8996e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a899396166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a899395e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8f0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8f08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8f08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a899395d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (2828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c96d6856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558c96d65505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558c96d68cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe124049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1240a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe124049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe124031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c96cfe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558c96cfe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558c96ce2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558c96992166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558c96991e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe124032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1240330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1240330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c96991d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (2829 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("ris
# | ...
# `---data was truncated (10240/26965) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567ca35f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005567ca35c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005567ca35fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd148933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd14898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd148933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd14891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567ca2f523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005567ca2f5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005567ca2d9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005567c9f89166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005567c9f88e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd14891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd14891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd14891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567c9f88d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (2830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cb213556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563cb2132505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563cb2135cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5903d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5903d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5903d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5903d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cb20cb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563cb20cb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563cb20aff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563cb1d5f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563cb1d5ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5903d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5903d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5903d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cb1d5ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (2831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cd032d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564cd032a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564cd032dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22ead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22ead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22ead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22ead1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cd02c323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564cd02c3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564cd02a7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564ccff57166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564ccff56e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22ead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22ead1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22ead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ccff56d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (2832 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056049393956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560493936505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560493939cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c0c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c0c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c0c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c0c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604938cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005604938cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005604938b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560493563166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560493562e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c0c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c0c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c0c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560493562d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (2833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/64341) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561398f1356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561398f10505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561398f13cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6eb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6eb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6eb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6eb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561398ea923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561398ea9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561398e8df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561398b3d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561398b3ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa6eb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6eb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6eb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561398b3cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (2834 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e3eb7b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e3eb78505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e3eb7bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cc7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cc7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cc7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cc7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e3eb1123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e3eb11086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e3eaf5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e3e7a5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e3e7a4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8cc7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cc7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cc7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e3e7a4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (2835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d671a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560d671a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560d671a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b4b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b4b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b4b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b4b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d6713a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560d6713a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560d6711ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560d66dce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560d66dcde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b4b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b4b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b4b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d66dcdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (2836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = all
# | ...
# `---data was truncated (10240/41587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdebd4556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bdebd42505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bdebd45cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1714533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f171458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1714533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f171451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdebcdb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bdebcdb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bdebcbff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bdeb96f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bdeb96ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f171451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f171451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f171451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdeb96ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (2837 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<
# | ...
# `---data was truncated (10240/119297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e331fd456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e331fd1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e331fd4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d24c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d24ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d24c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d24c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e331f6a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e331f6a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e331f4ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e331bfe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e331bfde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d24c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d24c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d24c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e331bfdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bfbe3c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560bfbe39505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560bfbe3ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff78ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff78eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff78ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff78ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bfbdd223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560bfbdd2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560bfbdb6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560bfba66166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560bfba65e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff78ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff78ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff78ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bfba65d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (2839 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a51bba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a51bb7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a51bbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1737133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f173718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1737133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f173711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a51b5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a51b50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a51b34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a517e4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a517e3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f173711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f173711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f173711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a517e3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (2840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c79a9a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c79a99d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c79a9a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14d2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14d22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14d2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14d2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c79a93623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c79a936086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c79a91af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c79a5ca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c79a5c9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f14d2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14d22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14d22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c79a5c9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (2841 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055919e8b956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055919e8b6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055919e8b9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30a9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30a98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30a9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30a9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055919e84f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055919e84f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055919e833f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055919e4e3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055919e4e2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f30a9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30a98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30a98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055919e4e2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (2842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c116a4456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c116a41505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c116a44cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5aee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5aeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5aee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5aee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1169da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1169da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1169bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c11666e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c11666de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa5aee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5aee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5aee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c11666dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (2843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstrid
# | ...
# `---data was truncated (10240/28111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc9625056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc9624d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc96250cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d10d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc961e623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc961e6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc961caf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc95e7a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc95e79e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc95e79d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (2844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c  -check-prefix=RV32ZKSH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c30185f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c30185c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c30185fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72a3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72a318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72a3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72a311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3017f523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3017f5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3017d9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c301489166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c301488e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72a311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72a311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72a311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c301488d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (2845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/12177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d7e55556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d7e552505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d7e555cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0998c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0998ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0998c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0998c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d7e4eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d7e4eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d7e4cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d7e17f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d7e17ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0998c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0998c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0998c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d7e17ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (2846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc9225556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cc92252505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cc92255cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fc7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fc7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fc7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fc7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc921eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cc921eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cc921cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cc91e7f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cc91e7ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2fc7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fc7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fc7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc91e7ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (2847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/15718) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055601e85c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055601e859505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055601e85ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dfbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dfbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dfbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dfbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055601e7f223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055601e7f2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055601e7d6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055601e486166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055601e485e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5dfbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dfbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dfbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055601e485d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (2848 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578ca0fe56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578ca0fb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578ca0fecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faca2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faca2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faca2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faca2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578ca09423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578ca094086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578ca078f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578c9d28166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578c9d27e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faca2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faca2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faca2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578c9d27d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (2849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faeedd856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055faeedd5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055faeedd8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c62105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c6215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c62105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c620ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faeed6e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055faeed6e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055faeed52f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055faeea02166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055faeea01e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c620eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c620ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c620ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faeea01d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (2850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bc86c256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556bc86bf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556bc86c2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2264d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2264d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2264d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2264d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bc865823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556bc8658086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556bc863cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556bc82ec166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556bc82ebe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2264d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2264d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2264d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bc82ebd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (2851 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x half>, ptr %0, align 2
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x float>, ptr %0, align 4
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i8>, ptr %0, align 1
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i8>, ptr %0, align 1
# |   %2 = sext <4 x i8> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = a
# | ...
# `---data was truncated (10240/50873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4e73d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4e73d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4e73d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0615049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06150a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0615049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0615031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4e736d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f4e736d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f4e7351f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4e7001166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4e7000e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0615032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06150330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06150330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4e7000d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (2852 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0723c556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a0723c2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a0723c5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29cee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29ceea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29cee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29cee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a07235b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a07235b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a07233ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a071fef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a071feee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f29cee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29cee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29cee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a071feed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (2853 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e5a3ff56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556e5a3fc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556e5a3ffcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f434b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f434b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f434b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f434b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e5a39523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556e5a395086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556e5a379f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556e5a029166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556e5a028e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f434b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f434b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f434b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e5a028d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (2854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564847b0856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564847b05505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564847b08cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03b381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03b38725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03b381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03b3803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564847a9e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564847a9e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564847a82f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564847732166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564847731e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03b3804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03b38050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03b38050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564847731d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (2855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/17403) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566956f156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005566956ee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005566956f1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effe1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effe1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effe1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effe1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055669568723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556695687086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055669566bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055669531b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055669531ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007effe1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effe1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effe1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055669531ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (2856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c7cb3656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560c7cb33505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560c7cb36cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f668d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f668d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f668d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f668d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c7cacc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560c7cacc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560c7cab0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560c7c760166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560c7c75fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f668d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f668d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f668d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c7c75fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (2857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee9c5a556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee9c5a2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee9c5a5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e26333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e2638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e26333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e2631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee9c53b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee9c53b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee9c51ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee9c1cf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee9c1cee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e2631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e2631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e2631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee9c1ced71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (2858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a30bc556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558a30bc2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558a30bc5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2093c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2093ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2093c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2093c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a30b5b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558a30b5b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558a30b3ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558a307ef166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558a307eee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2093c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2093c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2093c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a307eed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (2859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16e30f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c16e30c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c16e30fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ab7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ab715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ab7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ab70ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c16e2a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c16e2a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c16e289f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c16df39166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c16df38e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ab70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ab70ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ab70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c16df38d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.ad
# | ...
# `---data was truncated (10240/26762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ac2df756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ac2df4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ac2df7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bec849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bec8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bec849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bec831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ac2d8d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ac2d8d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ac2d71f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ac2a21166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ac2a20e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1bec832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bec8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bec8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ac2a20d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (2861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561327d7556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561327d72505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561327d75cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dcda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dcdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dcda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dcda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561327d0b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561327d0b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561327ceff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056132799f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056132799ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4dcda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dcda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dcda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056132799ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (2862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat>
# | ...
# `---data was truncated (10240/53686) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555991a8d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555991a8a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555991a8dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c1fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c1fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c1fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c1fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555991a2323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555991a23086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555991a07f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559916b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559916b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4c1fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c1fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c1fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559916b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (2863 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3c287e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d3c287b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d3c287ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b58449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b584a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b58449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b58431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3c281423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d3c2814086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d3c27f8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d3c24a8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d3c24a7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7b58432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b584330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b584330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3c24a7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (2864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6f188e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6f188b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6f188ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbaa7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbaa758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbaa7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbaa751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6f182423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b6f1824086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b6f1808f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6f14b8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6f14b7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbaa751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbaa751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbaa751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6f14b7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (2865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6be98d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f6be98a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f6be98dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe45ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe45aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe45ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe45ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6be92323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f6be923086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f6be907f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f6be5b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f6be5b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe45ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe45ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe45ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6be5b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (2866 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560481c4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560481c40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560481c43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe77bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe77bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe77bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe77bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560481bd923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560481bd9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560481bbdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056048186d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056048186ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe77bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe77bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe77bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056048186cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (2867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f5b23856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f5b235505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f5b238cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd65b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd65b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd65b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd65b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f5b1ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f5b1ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f5b1b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f5ae62166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f5ae61e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd65b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd65b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd65b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f5ae61d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (2868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e48893756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e488934505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e488937cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb9bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb9bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb9bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb9bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4888cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e4888cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e4888b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e488561166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e488560e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ffb9bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb9bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb9bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e488560d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (2869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a191caa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a191ca7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a191caacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e95705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e9575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e95705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e956ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a191c4023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a191c40086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a191c24f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a1918d4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a1918d3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e956eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e956ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e956ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1918d3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (2870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056208101656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562081013505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562081016cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff16a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff16a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff16a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff16a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562080fac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562080fac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562080f90f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562080c40166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562080c3fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff16a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff16a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff16a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562080c3fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (2871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8a719556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f8a7192505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f8a7195cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef99305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef9935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef99305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef992ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8a712b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f8a712b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f8a710ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f8a6dbf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f8a6dbee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef992eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef992ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef992ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8a6dbed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-cde-vec.c (2872 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 {
# | entry:
# |   %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111)
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %acc, ptr %acc.addr, align 8
# |   %0 = load <4 x i32>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113)
# |   %3 = bitcast <16 x i8> %2 to <4 x i32>
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <8 x half>, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   %0 = load <8 x half>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <4 x float>, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %n.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112)
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <2 x i64>, align 8
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = load <2 x i64>, ptr %n.addr, align 8
# |   %3 = bitcast <2 x i64> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113)
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x i32> %m, ptr %m.addr, align 8
# |   %0 = load <8 x i16>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <16 x i8>
# |   %2 = load <4 x i32>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x i32> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <2 x i64>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <2 x i64>, ptr %n.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %2 = load <4 x float>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12)
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load <8 x i16>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x i16> %1 to <16 x i8>
# |   %3 = load <4 x float>, ptr %m.addr, align 8
# |   %4 = bitcast <4 x float> %3 to <16 x i8>
# |   %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %n.addr, align 8
# |   %2 = bitcast <4 x float> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = load <8 x half>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x half> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %m.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# | ...
# `---data was truncated (10240/13030) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4eb18f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4eb18c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4eb18fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f745ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f745aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f745ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f745ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4eb12523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f4eb125086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f4eb109f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4eadb9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4eadb8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f745ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f745ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f745ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4eadb8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (2873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfa456c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfa4569505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfa456ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff679a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff679aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff679a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff679a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfa450223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfa4502086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfa44e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfa4196166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfa4195e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff679a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff679a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff679a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfa4195d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (2874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055582cb7d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055582cb7a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055582cb7dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cf281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cf28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cf281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cf2803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055582cb1323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055582cb13086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055582caf7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055582c7a7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055582c7a6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5cf2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cf28050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cf28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055582c7a6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (2875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/51759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055814f15756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055814f154505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055814f157cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6def505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6def55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6def505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6def4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055814f0ed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055814f0ed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055814f0d1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055814ed81166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055814ed80e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6def4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6def4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6def4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055814ed80d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (2876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee0bc4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ee0bc43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ee0bc46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0db249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0db2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0db249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0db231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee0bbdc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ee0bbdc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ee0bbc0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ee0b870166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ee0b86fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd0db232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0db2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0db2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee0b86fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (2877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfb5f9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bfb5f8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bfb5f90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2615f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2615f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2615f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2615f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfb5f2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bfb5f26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bfb5f0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bfb5bba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bfb5bb9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2615f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2615f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2615f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfb5bb9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (2878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be5568556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be55682505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be55685cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61e0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61e078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61e0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61e071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be5561b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be5561b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be555fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be552af166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be552aee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61e071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61e071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61e071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be552aed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (2879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d8cf8f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562d8cf8c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562d8cf8fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba8c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba8c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba8c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba8c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d8cf2523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562d8cf25086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562d8cf09f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562d8cbb9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562d8cbb8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fba8c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba8c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba8c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d8cbb8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (2880 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double
# | ...
# `---data was truncated (10240/29119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056484441d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056484441a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056484441dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe2761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe276725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe2761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe27603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648443b323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005648443b3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564844397f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564844047166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564844046e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbe27604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe276050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe276050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564844046d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (2881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i
# | ...
# `---data was truncated (10240/14788) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c57de8056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c57de7d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c57de80cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8999449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89994a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8999449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8999431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c57de1623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c57de16086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c57ddfaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c57daaa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c57daa9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8999432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89994330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89994330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c57daa9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (2882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055858336856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558583365505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558583368cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0ba105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0ba15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0ba105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0ba0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585832fe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005585832fe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005585832e2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558582f92166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558582f91e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe0ba0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0ba0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0ba0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558582f91d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (2883 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b99ce8a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b99ce87505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b99ce8acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd12b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd12b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd12b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd12b8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b99ce2023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b99ce20086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b99ce04f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b99cab4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b99cab3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd12b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd12b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd12b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b99cab3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (2884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, i64 %2, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_
# | ...
# `---data was truncated (10240/15323) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f3b81256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f3b80f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f3b812cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92ed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92ed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92ed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92ed31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f3b7a823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f3b7a8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f3b78cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f3b43c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f3b43be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f92ed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92ed31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92ed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f3b43bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (2885 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e633ec056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e633ebd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e633ec0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac70733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac7078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac70733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac7071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e633e5623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e633e56086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e633e3af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e633aea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e633ae9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fac7071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac7071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac7071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e633ae9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (2886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b2e0d056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b2e0cd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b2e0d0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0acd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0acd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0acd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0acced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b2e06623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b2e066086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b2e04af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b2dcfa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b2dcf9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb0acceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0accef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0accef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b2dcf9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (2887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efea3bf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055efea3bc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055efea3bfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff18a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff18a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff18a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff18a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efea35523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055efea355086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055efea339f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055efe9fe9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055efe9fe8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff18a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff18a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff18a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efe9fe8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (2888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a7f4c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561a7f4c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561a7f4c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f395fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f395fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f395fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f395faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a7f45d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561a7f45d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561a7f441f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561a7f0f1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561a7f0f0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f395faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f395faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f395faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a7f0f0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (2889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647aee0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005647aedff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005647aee02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9310f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9310f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9310f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9310eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647aed9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005647aed98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005647aed7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005647aea2c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005647aea2be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9310eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9310eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9310eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647aea2bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (2890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x_x_v_u64
# | ...
# `---data was truncated (10240/29259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579a6e0c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005579a6e09505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005579a6e0ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb29333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb2938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb29333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb2931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579a6da223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005579a6da2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005579a6d86f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005579a6a36166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005579a6a35e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcb2931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb2931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb2931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579a6a35d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (2891 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa4328c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa43289505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa4328ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca40849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca408a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca40849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca40831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa4322223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa43222086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa43206f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa42eb6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa42eb5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca40832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca408330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca408330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa42eb5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (2892 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1)
# |   store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.fptosi.sat.i64.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   st
# | ...
# `---data was truncated (10240/53064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5a241a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e5a2417505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e5a241acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77a1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77a198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77a1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77a191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5a23b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e5a23b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e5a2394f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e5a2044166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e5a2043e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f77a191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77a191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77a191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5a2043d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (2893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfb286656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfb2863505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfb2866cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7699133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f769918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7699133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f769911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfb27fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfb27fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfb27e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfb2490166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfb248fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f769911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f769911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f769911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfb248fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (2894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055698436756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556984364505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556984367cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedf2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedf238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedf2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedf231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569842fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005569842fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005569842e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556983f91166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556983f90e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fedf231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedf231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedf231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556983f90d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (2895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558638f256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558638ef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558638f2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdea2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdea275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdea2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdea26ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055586388823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555863888086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055586386cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055586351c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055586351be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdea26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdea26ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdea26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055586351bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (2896 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, al
# | ...
# `---data was truncated (10240/28866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056077f7af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056077f7ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056077f7afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08df649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08df6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08df649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08df631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056077f74523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056077f745086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056077f729f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056077f3d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056077f3d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f08df632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08df6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08df6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056077f3d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (2897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_i8m1_i8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m1_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m2_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m1_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m2_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m4_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 32 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> %0, <vscale x 32 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8>, <vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_u8m1_u8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m1_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m2_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m1_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m2_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m4_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, p
# | ...
# `---data was truncated (10240/54546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be8b60d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be8b60a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be8b60dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d03a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d03aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d03a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d03a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be8b5a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be8b5a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be8b587f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be8b237166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be8b236e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d03a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d03a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d03a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be8b236d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (2898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv
# | ...
# `---data was truncated (10240/83637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cc7f8f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560cc7f8c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560cc7f8fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22cfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22cfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22cfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22cfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cc7f2523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560cc7f25086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560cc7f09f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560cc7bb9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560cc7bb8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22cfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22cfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22cfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cc7bb8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (2899 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b08735a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b087357505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b08735acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0468649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04686a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0468649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0468631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0872f023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b0872f0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b0872d4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b086f84166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b086f83e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0468632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04686330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04686330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b086f83d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (2900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dcf90556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563dcf902505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563dcf905cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d77c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d77ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d77c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d77c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dcf89b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563dcf89b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563dcf87ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563dcf52f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563dcf52ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d77c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d77c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d77c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dcf52ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (2901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcee9dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dcee9d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dcee9dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2d7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2d70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2d7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2d7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcee97223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dcee972086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dcee956f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dcee606166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dcee605e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd2d7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2d70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2d70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcee605d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (2902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055872d3c756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055872d3c4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055872d3c7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a1141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a114725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a1141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a11403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055872d35d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055872d35d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055872d341f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055872cff1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055872cff0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0a11404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a114050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a114050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055872cff0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (2903 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de7861e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de7861b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de7861ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d86431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de785b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de785b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de78598f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de78248166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de78247e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d864330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de78247d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (2904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ef757956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ef7576505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ef7579cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b8af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b8af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b8af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b8af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ef750f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ef750f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ef74f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ef71a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ef71a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b8af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b8af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b8af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ef71a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (2905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b14363756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b143634505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b143637cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdef7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdef7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdef7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdef7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1435cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b1435cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b1435b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b143261166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b143260e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdef7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdef7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdef7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b143260d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (2906 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615edc0d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005615edc0a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005615edc0dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7954733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f795478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7954733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f795471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615edba323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005615edba3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005615edb87f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615ed837166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615ed836e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f795471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f795471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f795471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615ed836d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (2907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fccb24b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fccb248505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fccb24bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f344a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f344a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f344a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f344a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fccb1e123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fccb1e1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fccb1c5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fccae75166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fccae74e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f344a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f344a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f344a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fccae74d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (2908 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i)
# |   store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i)
# |   store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005576d0efd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005576d0efa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005576d0efdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd91ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd91baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd91ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd91ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576d0e9323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005576d0e93086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005576d0e77f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005576d0b27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005576d0b26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd91ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd91ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd91ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576d0b26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (2909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569880cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005569880c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005569880cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f360ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f360ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f360ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f360ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055698806123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556988061086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556988045f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556987cf5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556987cf4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f360ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f360ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f360ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556987cf4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (2910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/12656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a462d4e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a462d4b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a462d4ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc615e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc615e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc615e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc615e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a462ce423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a462ce4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a462cc8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a462978166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a462977e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc615e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc615e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc615e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a462977d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (2911 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | 
# | ...
# `---data was truncated (10240/34641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056290bbe456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056290bbe1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056290bbe4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f491a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f491a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f491a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f491a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056290bb7a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056290bb7a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056290bb5ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056290b80e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056290b80de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f491a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f491a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f491a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056290b80dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (2912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644e592556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005644e5922505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005644e5925cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5087a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5087aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5087a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5087a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644e58bb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005644e58bb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005644e589ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005644e554f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005644e554ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5087a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5087a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5087a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644e554ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (2913 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %class.anon = type { i8 }
# | 
# | $_Z15template_functyIiET_S0_ = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_caller() #0 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | declare i32 @normal_callee() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_callee() #0 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_decl() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_caller() #3 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_callee() #3 {
# | entry:
# |   %call = call i32 @streaming_compatible_decl() #16
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_compatible_decl() #4
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_caller() #5 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_callee() #5 {
# | entry:
# |   %call = call i32 @locally_streaming_caller() #17
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_caller() #6 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_callee() #6 {
# | entry:
# |   %call = call i32 @shared_za_decl() #18
# |   ret i32 %call
# | }
# | 
# | declare i32 @shared_za_decl() #7
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_caller() #8 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_callee() #8 {
# | entry:
# |   %call = call i32 @preserves_za_decl() #19
# |   ret i32 %call
# | }
# | 
# | declare i32 @preserves_za_decl() #9
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_caller() #10 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_callee() #10 {
# | entry:
# |   %call = call i32 @private_za_decl()
# |   ret i32 %call
# | }
# | 
# | declare i32 @private_za_decl() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_caller() #11 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee() #12 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | declare i32 @agnostic_za_decl() #13
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee_live_za() #6 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #16
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #18
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #19
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %fptr.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %fptr, ptr %fptr.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %fptr.addr, align 8
# |   %1 = load ptr, ptr %0, align 8
# |   %2 = load ptr, ptr %1, align 8
# |   %3 = load i32, ptr %x.addr, align 4
# |   %4 = load i32, ptr %y.addr, align 4
# |   call void %2(i32 noundef %3, i32 noundef %4) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @_Z24test_same_type_streamingv() #12 {
# | entry:
# |   call void @_Z10streaming1v() #15
# |   call void @_Z10streaming2v() #15
# |   call void @_Z20same_type_streaming1v() #15
# |   call void @_Z20same_type_streaming2v() #15
# |   ret void
# | }
# | 
# | declare void @_Z10streaming1v() #2
# | 
# | declare void @_Z10streaming2v() #2
# | 
# | declare void @_Z20same_type_streaming1v() #2
# | 
# | declare void @_Z20same_type_streaming2v() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   ret float %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   %call = call noundef float @_Z12overloadedfnf(float noundef %0)
# |   ret float %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %F = alloca %class.anon, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 {
# | entry:
# |   %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z25locally_streaming_inheritv() #5 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret void
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define dso_local noundef i32 @_Z4callv() #14 {
# | entry:
# |   ret i32 0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 {
# | entry:
# |   %f.addr.i16 = alloca ptr, align 8
# |   %f.addr.i12 = alloca ptr, align 8
# |   %other.addr.i13 = alloca ptr, align 8
# |   %f.addr.i7 = alloca ptr, align 8
# |   %other.addr.i8 = alloca ptr, align 8
# |   %other.addr2.i9 = alloca ptr, align 8
# |   %f.addr.i1 = alloca ptr, align 8
# |   %other.addr.i2 = alloca ptr, align 8
# |   %other.addr2.i3 = alloca ptr, align 8
# |   %other.addr4.i4 = alloca ptr, align 8
# |   %f.addr.i = alloca ptr, align 8
# |   %other.addr.i = alloca ptr, align 8
# |   %other.addr2.i = alloca ptr, align 8
# |   %other.addr4.i = alloca ptr, align 8
# |   %other.addr6.i = alloca ptr, align 8
# |   store ptr @normal_callee, ptr %f.addr.i, align 8
# |   store ptr @streaming_decl, ptr %other.addr.i, align 8
# |   store ptr @streaming_compatible_decl
# | ...
# `---data was truncated (10240/15241) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055975970856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559759705505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559759708cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5713649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57136a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5713649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5713631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055975969e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055975969e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559759682f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559759332166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559759331e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5713632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57136330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57136330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559759331d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x00005646ea5ab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646ea5a8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646ea5abcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5245905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f524595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5245905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52458ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646ea54123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646ea541086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646ea525f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646ea1d5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646ea1d4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f52458eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52458ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52458ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646ea1d4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (2914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale 
# | ...
# `---data was truncated (10240/40937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f1ea9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561f1ea8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561f1ea90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39d021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39d02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39d021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39d0203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f1ea2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561f1ea26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561f1ea0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561f1e6ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561f1e6b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f39d0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39d02050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39d02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f1e6b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (2915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593e4ac056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005593e4abd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005593e4ac0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d6dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d6dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d6dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d6dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593e4a5623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005593e4a56086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005593e4a3af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005593e46ea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005593e46e9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d6dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d6dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d6dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593e46e9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (2916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fae895356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fae8950505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fae8953cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb146d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb146d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb146d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb146d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fae88e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fae88e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fae88cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fae857d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fae857ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb146d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb146d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb146d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fae857cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (2917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559afbfba56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559afbfb7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559afbfbacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbede733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbede78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbede733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbede71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559afbf5023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559afbf50086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559afbf34f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559afbbe4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559afbbe3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbede71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbede71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbede71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559afbbe3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (2918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca583b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ca583b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ca583b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff987333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff98738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff987333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff98731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca5834d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ca5834d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ca58331f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ca57fe1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ca57fe0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff98731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff98731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff98731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca57fe0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (2919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f31eeb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557f31ee8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557f31eebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e40e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e40ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e40e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e40e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f31e8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557f31e81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557f31e65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557f31b15166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557f31b14e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e40e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e40e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e40e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f31b14d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (2920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a39c6756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a39c64505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a39c67cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7b4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7b4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7b4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7b4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a39bfd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a39bfd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a39be1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a39891166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a39890e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa7b4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7b4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7b4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a39890d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (2921 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(
# | ...
# `---data was truncated (10240/32505) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055694be1656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055694be13505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055694be16cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc590f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc590f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc590f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc590f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055694bdac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055694bdac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055694bd90f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055694ba40166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055694ba3fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc590f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc590f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc590f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055694ba3fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (2922 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c52582656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c525823505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c525826cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda54933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda5498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda54933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda5491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5257bc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5257bc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5257a0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c525450166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c52544fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fda5491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda5491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda5491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c52544fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (2923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623b1ab156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005623b1aae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005623b1ab1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae0d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae0d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae0d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae0d003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623b1a4723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005623b1a47086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005623b1a2bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005623b16db166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005623b16dae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae0d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae0d0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae0d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623b16dad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (2924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5a6e7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a5a6e74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a5a6e77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fded201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fded20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fded201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fded2003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5a6e0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a5a6e0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a5a6df1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a5a6aa1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a5a6aa0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fded2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fded20050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fded20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5a6aa0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (2925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a3a3cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556a3a3c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556a3a3cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82d3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82d3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82d3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82d3e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a3a36223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556a3a362086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556a3a346f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556a39ff6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556a39ff5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f82d3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82d3e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82d3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a39ff5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (2926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc1f46556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bc1f462505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bc1f465cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9df1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9df175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9df1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9df16ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc1f3fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bc1f3fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bc1f3dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bc1f08f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bc1f08ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9df16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9df16ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9df16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc1f08ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (2927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv
# | ...
# `---data was truncated (10240/20082) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b67a7956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b67a76505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b67a79cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaf9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaf978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaf9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaf971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b67a0f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b67a0f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b679f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b676a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b676a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feaf971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaf971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaf971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b676a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (2928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4f118356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f4f1180505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f4f1183cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d6c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d6c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d6c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d6c4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4f111923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f4f1119086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f4f10fdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f4f0dad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f4f0dace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d6c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d6c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d6c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4f0dacd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (2929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4
# | ...
# `---data was truncated (10240/25575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0514d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e0514d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e0514d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ffb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ffb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ffb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ffb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e05146e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e05146e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e051452f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e051102166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e051101e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ffb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ffb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ffb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e051101d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (2930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2884ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e2884cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e2884cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d83905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d8395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d83905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d838ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e28846423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e288464086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e288448f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e2880f8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e2880f7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d838eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d838ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d838ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2880f7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (2931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d4d14856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555d4d145505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555d4d148cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe85d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe85d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe85d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe85d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d4d0de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555d4d0de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555d4d0c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555d4cd72166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555d4cd71e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe85d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe85d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe85d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d4cd71d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (2932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577a71bc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005577a71b9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005577a71bccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f565fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f565fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f565fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f565fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577a715223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005577a7152086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005577a7136f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005577a6de6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005577a6de5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f565fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f565fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f565fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577a6de5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (2933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056213e7f056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056213e7ed505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056213e7f0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5b1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5b1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5b1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5b1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056213e78623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056213e786086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056213e76af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056213e41a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056213e419e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5b1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5b1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5b1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056213e419d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (2934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3bd6d356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c3bd6d0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c3bd6d3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd44f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd44f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd44f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd44f8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3bd66923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c3bd669086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c3bd64df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c3bd2fd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c3bd2fce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd44f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd44f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd44f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3bd2fcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (2935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c787a156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c7879e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c787a1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f37f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f37f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f37f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f37f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c7873723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c78737086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c7871bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c783cb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c783cae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f37f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f37f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f37f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c783cad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (2936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/26520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646f1acc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005646f1ac9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005646f1acccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f761b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f761b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f761b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f761b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646f1a6223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646f1a62086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646f1a46f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005646f16f6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005646f16f5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f761b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f761b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f761b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646f16f5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (2937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5a722a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5a7227505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5a722acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febf7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febf758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febf7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febf751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5a71c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5a71c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5a71a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5a6e54166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5a6e53e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007febf751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febf751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febf751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5a6e53d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (2938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561e9b6056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561e9b5d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561e9b60cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6acb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6acb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6acb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6acb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561e9af623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561e9af6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561e9adaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005561e978a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005561e9789e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6acb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6acb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6acb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561e9789d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (2939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab9408556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab94082505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab94085cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa76f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa76f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa76f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa76f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab9401b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab9401b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab93ffff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab93caf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab93caee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faa76f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa76f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa76f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab93caed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (2940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d53563f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d53563c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d53563fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca18733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca1878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca18733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca1871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5355d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d5355d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d5355b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d535269166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d535268e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fca1871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca1871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca1871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d535268d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (2941 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5adf7956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5adf76505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5adf79cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd467533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd46758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd467533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd46751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5adf0f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5adf0f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5adef3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5adba3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5adba2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd46751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd46751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd46751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5adba2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (2942 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# |  #0 0x000055ace26b456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ace26b1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ace26b4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f394c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f394c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f394c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f394c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ace264a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ace264a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ace262ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ace22de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ace22dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f394c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f394c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f394c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ace22ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (2943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c484cf756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c484cf4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c484cf7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc72d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc72d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc72d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc72d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c484c8d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c484c8d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c484c71f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c484921166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c484920e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc72d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc72d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc72d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c484920d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (2944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a760d4756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a760d44505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a760d47cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f802df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f802df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f802df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f802df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a760cdd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a760cdd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a760cc1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a760971166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a760970e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f802df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f802df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f802df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a760970d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (2945 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret bfloat %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x bfloat> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | !llvm.errno.tbaa = !{!6}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# | !6 = !{!7, !8, i64 0}
# | !7 = !{!"__libc_errno", !8, i64 0}
# | !8 = !{!"int", !9, i64 0}
# | !9 = !{!"omnipotent char", !10, i64 0}
# | !10 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055665f79f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055665f79c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055665f79fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff339649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3396a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff339649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff339631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055665f73523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055665f735086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055665f719f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055665f3c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055665f3c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff339632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3396330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3396330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055665f3c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (2946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32> %maske
# | ...
# `---data was truncated (10240/75397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d94c6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d94c6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d94c6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb6ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb6ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb6ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb6ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d94c0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d94c03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d94be7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d94897166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d94896e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbb6ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb6ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb6ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d94896d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (2947 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c7600f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c7600c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c7600fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc391b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc391b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc391b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc391b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c75fa523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c75fa5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c75f89f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c75c39166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c75c38e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc391b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc391b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc391b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c75c38d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (2948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c679d2356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c679d20505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c679d23cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc22bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc22bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c679cb923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c679cb9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c679c9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c67994d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c67994ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc22bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c67994cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (2949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f304d6456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f304d61505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f304d64cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef4a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef4a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef4a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef4a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f304cfa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f304cfa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f304cdef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f30498e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f30498de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fef4a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef4a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef4a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f30498dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (2950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582ec19456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005582ec191505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005582ec194cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf5d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf5d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf5d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf5d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582ec12a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005582ec12a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005582ec10ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005582ebdbe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005582ebdbde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faf5d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf5d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf5d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582ebdbdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (2951 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr
# | ...
# `---data was truncated (10240/44315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005643b911856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005643b9115505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005643b9118cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc695249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6952a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc695249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc695231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643b90ae23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005643b90ae086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005643b9092f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005643b8d42166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005643b8d41e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc695232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6952330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6952330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643b8d41d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (2952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |  
# | ...
# `---data was truncated (10240/28350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563601ef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563601ec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563601efcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20ce849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20ce8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20ce849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20ce831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055636018523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556360185086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556360169f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055635fe19166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055635fe18e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f20ce832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20ce8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20ce8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055635fe18d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (2953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af31cf456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af31cf1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af31cf4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f789dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f789dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f789dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f789dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af31c8a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af31c8a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af31c6ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af3191e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af3191de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f789dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f789dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f789dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af3191dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (2954 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vsca
# | ...
# `---data was truncated (10240/11229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583339b056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005583339ad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005583339b0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e5ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e5ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e5ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e5ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055833394623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558333946086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055833392af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005583335da166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005583335d9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e5ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e5ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e5ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583335d9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (2955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559c4d4856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559c4d45505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559c4d48cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9263533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f926358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9263533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f926351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559c4cde23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559c4cde086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559c4cc2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559c4972166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559c4971e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f926351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f926351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f926351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559c4971d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (2956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f00036956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f000366505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f000369cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8402933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f840298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8402933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f840291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0002ff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0002ff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0002e3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055effff93166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055effff92e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f840291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f840291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f840291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055effff92d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (2957 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bc0de556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559bc0de2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559bc0de5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5956333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f595638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5956333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f595631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bc0d7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559bc0d7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559bc0d5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559bc0a0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559bc0a0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f595631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f595631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f595631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bc0a0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (2958 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>
# | ...
# `---data was truncated (10240/51185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056207b28556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056207b282505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056207b285cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb40ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb40ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb40ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb40ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056207b21b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056207b21b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056207b1fff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056207aeaf166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056207aeaee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb40ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb40ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb40ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056207aeaed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (2959 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f82a02856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f82a025505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f82a028cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f285ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f285baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f285ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f285ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f829fbe23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f829fbe086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f829fa2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f829c52166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f829c51e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f285ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f285ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f285ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f829c51d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (2960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c4a86c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561c4a869505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561c4a86ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faebaa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faebaa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faebaa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faebaa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c4a80223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561c4a802086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561c4a7e6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561c4a496166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561c4a495e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faebaa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faebaa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faebaa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c4a495d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (2961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5fd4ea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d5fd4e7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d5fd4eacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fdcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fdcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fdcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fdcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5fd48023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d5fd480086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d5fd464f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d5fd114166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d5fd113e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7fdcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fdcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fdcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5fd113d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (2962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056053480d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056053480a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056053480dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd36e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd36ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd36e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd36e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605347a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005605347a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560534787f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560534437166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560534436e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd36e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd36e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd36e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560534436d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (2963 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac5ca3156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ac5ca2e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ac5ca31cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc657c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc657ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc657c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc657c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac5c9c723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ac5c9c7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ac5c9abf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ac5c65b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ac5c65ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc657c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc657c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc657c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac5c65ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (2964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605057a456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005605057a1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005605057a4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f594fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f594fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f594fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f594fe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056050573a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056050573a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056050571ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005605053ce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005605053cde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f594fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f594fe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f594fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605053cdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (2965 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055816c61956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055816c616505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055816c619cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bdbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bdbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bdbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bdbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055816c5af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055816c5af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055816c593f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055816c243166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055816c242e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4bdbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bdbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bdbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055816c242d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (2966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb6c81256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb6c80f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb6c812cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8399249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8399249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8399231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb6c7a823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb6c7a8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb6c78cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb6c43c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb6c43be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8399232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83992330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb6c43bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (2967 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624f090056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005624f08fd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005624f0900cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f081e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f081e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f081e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f081e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624f089623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005624f0896086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005624f087af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005624f052a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005624f0529e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f081e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f081e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f081e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624f0529d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (2968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/26748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aaddd9156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aaddd8e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aaddd91cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c30649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c306a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c30649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c30631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aaddd2723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aaddd27086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aaddd0bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aadd9bb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aadd9bae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c30632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c306330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c306330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aadd9bad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (2969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %bas
# | ...
# `---data was truncated (10240/29817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563824be256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563824bdf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563824be2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f448f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f448f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f448f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f448f203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563824b7823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563824b78086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563824b5cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056382480c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056382480be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f448f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f448f2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f448f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056382480bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (2970 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c  -check-prefix=RV64XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %not = xor i64 %0, -1
# |   %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bdafda56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559bdafd7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559bdafdacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43af649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43af6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43af649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43af631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bdaf7023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559bdaf70086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559bdaf54f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559bdac04166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559bdac03e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f43af632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43af6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43af6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bdac03d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (2971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr.i = alloca bfloat, align 2
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   store bfloat %0, ptr %bf.addr.i, align 2
# |   %1 = load bfloat, ptr %bf.addr.i, align 2
# |   %2 = fpext bfloat %1 to float
# |   ret float %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr.i = alloca float, align 4
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   store float %0, ptr %sf.addr.i, align 4
# |   %1 = load float, ptr %sf.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   ret bfloat %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da0381056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055da0380d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055da03810cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0997b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0997b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0997b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0997b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da037a623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055da037a6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055da0378af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055da0343a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055da03439e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0997b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0997b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0997b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da03439d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (2972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc5110856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fc51105505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fc51108cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4048d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4048d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4048d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4048d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc5109e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fc5109e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fc51082f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fc50d32166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fc50d31e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4048d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4048d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4048d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc50d31d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (2973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2d48c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a2d48c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a2d48c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5dc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5dc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5dc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5dc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2d485c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a2d485c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a2d4840f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a2d44f0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a2d44efe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5dc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5dc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5dc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2d44efd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (2974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563530d2356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563530d20505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563530d23cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f383b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f383b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f383b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f383b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563530cb923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563530cb9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563530c9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056353094d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056353094ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f383b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f383b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f383b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056353094cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (2975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ad360156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557ad35fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557ad3601cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa361e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa361ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa361e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa361e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ad359723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557ad3597086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557ad357bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557ad322b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557ad322ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa361e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa361e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa361e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ad322ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (2976 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609577bd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005609577ba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005609577bdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce09249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce09249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce09231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056095775323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560957753086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560957737f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005609573e7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005609573e6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fce09232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce092330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609573e6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (2977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bb535356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bb5350505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bb5353cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2100849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21008a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2100849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2100831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bb52e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bb52e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bb52cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bb4f7d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bb4f7ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2100832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21008330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21008330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bb4f7cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (2978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x flo
# | ...
# `---data was truncated (10240/29327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcbbbee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bcbbbeb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bcbbbeecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e9ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e9ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e9ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e9ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcbbb8423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bcbbb84086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bcbbb68f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bcbb818166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bcbb817e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4e9ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e9ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e9ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcbb817d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (2979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055679ed2a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055679ed27505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055679ed2acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97fae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97faea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97fae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97fae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055679ecc023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055679ecc0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055679eca4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055679e954166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055679e953e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f97fae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97fae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97fae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055679e953d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (2980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10878) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611655b756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005611655b4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005611655b7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22ecc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22ecca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22ecc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22ecc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056116554d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056116554d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561165531f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005611651e1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005611651e0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f22ecc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22ecc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22ecc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611651e0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (2981 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056010344856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560103445505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560103448cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe442449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe442449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe442431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601033de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005601033de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005601033c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560103072166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560103071e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe442432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4424330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560103071d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (2982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d027e6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d027e6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d027e6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7901733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f790178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7901733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f790171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d027e0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d027e03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d027de7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d027a97166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d027a96e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f790171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f790171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f790171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d027a96d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (2983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f7db2f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560f7db2c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560f7db2fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcab0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcab0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcab0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcab0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f7dac523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560f7dac5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560f7daa9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560f7d759166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560f7d758e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcab0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcab0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcab0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f7d758d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (2984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/13581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ce94cc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ce94c9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ce94cccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff10b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff10b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff10b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff10b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ce946223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ce9462086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ce9446f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ce90f6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ce90f5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff10b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff10b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff10b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ce90f5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (2985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e9c33c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561e9c339505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561e9c33ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64da21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64da2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64da21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64da203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e9c2d223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561e9c2d2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561e9c2b6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561e9bf66166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561e9bf65e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f64da204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64da2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64da2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e9bf65d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (2986 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a8a43756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558a8a434505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558a8a437cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f889f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f889f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f889f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f889f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a8a3cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558a8a3cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558a8a3b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558a8a061166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558a8a060e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f889f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f889f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f889f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a8a060d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (2987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 
# | ...
# `---data was truncated (10240/39226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad68c8256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad68c7f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad68c82cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa60a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa60a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa60a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa60a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad68c1823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad68c18086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad68bfcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad688ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad688abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa60a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa60a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa60a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad688abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (2988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056253bf1256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056253bf0f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056253bf12cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0118f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0118f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0118f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0118eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056253bea823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056253bea8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056253be8cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056253bb3c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056253bb3be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0118eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0118eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0118eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056253bb3bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (2989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056532996a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565329967505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056532996acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3f9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3f9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3f9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3f9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056532990023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000565329900086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005653298e4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000565329594166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000565329593e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe3f9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3f9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3f9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565329593d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (2990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610454af56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005610454ac505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005610454afcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4e4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4e438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4e4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4e431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056104544523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561045445086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561045429f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005610450d9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005610450d8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc4e431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4e431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4e431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610450d8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (2991 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fa562d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560fa562a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560fa562dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbddc21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbddc2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbddc21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbddc203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fa55c323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560fa55c3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560fa55a7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560fa5257166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560fa5256e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbddc204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbddc2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbddc2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fa5256d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (2992 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055791fbc456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055791fbc1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055791fbc4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07bef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07bef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07bef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07bef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055791fb5a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055791fb5a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055791fb3ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055791f7ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055791f7ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f07bef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07bef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07bef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055791f7edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (2993 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# |  #0 0x000055651357956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556513576505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556513579cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6184f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6184f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6184f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6184f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055651350f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055651350f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565134f3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565131a3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565131a2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6184f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6184f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6184f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565131a2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (2994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d2eb8756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d2eb84505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d2eb87cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7110533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f711058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7110533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f711051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d2eb1d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d2eb1d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d2eb01f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d2e7b1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d2e7b0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f711051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f711051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f711051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d2e7b0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (2995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5d7fa856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a5d7fa5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a5d7fa8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91be649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91be6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91be649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91be631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5d7f3e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a5d7f3e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a5d7f22f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a5d7bd2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a5d7bd1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f91be632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91be6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91be6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5d7bd1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (2996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8eb25756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e8eb254505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e8eb257cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9c0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9c018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9c0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9c011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8eb1ed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e8eb1ed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8eb1d1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e8eae81166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e8eae80e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9c011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9c011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9c011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8eae80d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (2997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c3ca7f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556c3ca7c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556c3ca7fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f927af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f927af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f927af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f927af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c3ca1523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556c3ca15086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556c3c9f9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556c3c6a9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556c3c6a8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f927af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f927af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f927af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c3c6a8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (2998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb442c056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb442bd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb442c0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78a3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78a3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78a3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78a3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb4425623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb44256086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb4423af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb43eea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb43ee9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78a3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78a3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78a3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb43ee9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (2999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557404c9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557404c8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557404c90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa019d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa019d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa019d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa019d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557404c2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557404c26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557404c0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005574048ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005574048b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa019d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa019d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa019d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574048b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (3000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dead74a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dead747505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dead74acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ea241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ea24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ea241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ea2403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dead6e023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dead6e0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dead6c4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dead374166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dead373e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ea2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ea24050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ea24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dead373d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (3001 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vsc
# | ...
# `---data was truncated (10240/21473) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f0618f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f0618c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f0618fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9245e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9245ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9245e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9245e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f0612523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f06125086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f06109f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f05db9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f05db8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9245e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9245e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9245e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f05db8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (3002 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-none-elf"
# | 
# | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any
# | 
# | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any
# | 
# | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any
# | 
# | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{i32 1, !5}
# | !5 = !{!"aarch64.mem_hint", i32 0}
# | !6 = !{i32 1, !7}
# | !7 = !{!"aarch64.mem_hint", i32 1}
# | !8 = !{i32 0, !9}
# | !9 = !{!"aarch64.mem_hint", i32 3}
# | !10 = !{i32 0, !11}
# | !11 = !{!"aarch64.mem_hint", i32 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a97b3756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560a97b34505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560a97b37cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ad441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ad44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ad441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ad4403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a97acd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560a97acd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560a97ab1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560a97761166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560a97760e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ad4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ad44050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ad44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a97760d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (3003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056460194f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056460194c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056460194fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4b941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4b94725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4b941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4b9403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646018e523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005646018e5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005646018c9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564601579166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564601578e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff4b9404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4b94050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4b94050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564601578d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (3004 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x half> %0, i32 2
# |   ret half %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x float> %0, i32 3
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 4
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 0
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 10
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 3
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 3
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 1
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 1
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca <8 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load half, ptr %a.addr, align 2
# |   %2 = insertelement <8 x half> %0, half %1, i32 4
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load float, ptr %a.addr, align 4
# |   %2 = insertelement <4 x float> %0, float %1, i32 2
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 12
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 6
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 2
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 0
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 2
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 7
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 1
# |   ret <2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x00005581d69c856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005581d69c5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005581d69c8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f103b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f103b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f103b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f103b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581d695e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005581d695e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005581d6942f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005581d65f2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005581d65f1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f103b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f103b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f103b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581d65f1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (3005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e34918456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e349181505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e349184cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadb5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadb558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadb5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadb551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e34911a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e34911a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e3490fef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e348dae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e348dade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fadb551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadb551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadb551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e348dadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (3006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale
# | ...
# `---data was truncated (10240/14485) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563e373e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563e373b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563e373ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb65ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb65ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb65ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb65ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563e36d423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005563e36d4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005563e36b8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005563e3368166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005563e3367e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb65ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb65ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb65ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563e3367d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (3007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056012107256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056012106f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560121072cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ea5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ea5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ea5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ea5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056012100823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560121008086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560120fecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560120c9c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560120c9be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ea5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ea5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ea5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560120c9bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (3008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a96c08e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a96c08b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a96c08ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f85e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f85ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f85e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f85e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a96c02423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a96c024086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a96c008f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a96bcb8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a96bcb7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f85e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f85e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f85e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a96bcb7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (3009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056549d3e156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056549d3de505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056549d3e1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9eff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9eff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9eff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9eff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056549d37723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056549d377086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056549d35bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056549d00b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056549d00ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe9eff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9eff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9eff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056549d00ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (3010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055708d5cd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055708d5ca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055708d5cdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2602649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26026a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2602649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2602631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055708d56323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055708d563086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055708d547f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055708d1f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055708d1f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2602632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26026330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26026330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055708d1f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (3011 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f28dab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f28da8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f28dabcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c80b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c80b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c80b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c80aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f28d4123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f28d41086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f28d25f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f289d5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f289d4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2c80aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c80aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c80aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f289d4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (3012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |  
# | ...
# `---data was truncated (10240/19083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec8d69956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ec8d696505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ec8d699cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09fe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09fe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09fe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09fe431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec8d62f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ec8d62f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ec8d613f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ec8d2c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ec8d2c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f09fe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09fe4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09fe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec8d2c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (3013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define 
# | ...
# `---data was truncated (10240/18595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556eed2bb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556eed2b8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556eed2bbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7bc21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7bc2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7bc21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7bc203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556eed25123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556eed251086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556eed235f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556eecee5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556eecee4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb7bc204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7bc2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7bc2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eecee4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (3014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa25fb356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aa25fb0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aa25fb3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04d9e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04d9e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04d9e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04d9e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa25f4923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aa25f49086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aa25f2df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aa25bdd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aa25bdce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f04d9e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04d9e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04d9e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa25bdcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (3015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9246c456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9246c1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9246c4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91b5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91b558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91b5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91b551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f92465a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f92465a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f92463ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f9242ee166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f9242ede83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f91b551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91b551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91b551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9242edd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (3016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #
# | ...
# `---data was truncated (10240/26584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560bbaeb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005560bbae8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005560bbaebcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5262849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5262849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5262831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560bba8123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005560bba81086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005560bba65f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005560bb715166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005560bb714e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5262832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52628330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560bb714d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (3017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6c6f0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d6c6eff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d6c6f02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4abcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4abcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4abcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4abcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6c6e9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d6c6e98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d6c6e7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d6c6b2c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d6c6b2be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4abcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4abcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4abcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6c6b2bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (3018 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fb23d456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559fb23d1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559fb23d4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ce9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ce9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ce9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ce9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fb236a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559fb236a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559fb234ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559fb1ffe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559fb1ffde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5ce9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ce9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ce9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fb1ffdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (3019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558baa17856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558baa175505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558baa178cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb76049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb760a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb76049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb76031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558baa10e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558baa10e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558baa0f2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558ba9da2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558ba9da1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feb76032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb760330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb760330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ba9da1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (3020 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffa904f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ffa904c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ffa904fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62bac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62baca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62bac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62bac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffa8fe523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ffa8fe5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ffa8fc9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ffa8c79166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ffa8c78e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f62bac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62bac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62bac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffa8c78d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (3021 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# |  #0 0x0000555fc7ee556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555fc7ee2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555fc7ee5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ac1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ac138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ac1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ac131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fc7e7b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555fc7e7b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555fc7e5ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555fc7b0f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555fc7b0ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0ac131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ac131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ac131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fc7b0ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (3022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, alig
# | ...
# `---data was truncated (10240/26754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568354fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005568354f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005568354facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7b601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7b60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7b601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7b6003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055683549023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556835490086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556835474f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556835124166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556835123e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc7b6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7b60050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7b60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556835123d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (3023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync
# | ...
# `---data was truncated (10240/10618) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056043f44e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056043f44b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056043f44ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2d2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056043f3e423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056043f3e4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056043f3c8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056043f078166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056043f077e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe2d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056043f077d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (3024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb4b3c056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eb4b3bd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eb4b3c0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f64333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f6438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f64333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f6431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb4b35623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eb4b356086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eb4b33af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eb4afea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eb4afe9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f6431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f6431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f6431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb4afe9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (3025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.a
# | ...
# `---data was truncated (10240/73947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565f4df256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565f4def505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565f4df2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5fab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5fab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5fab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5faaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565f4d8823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565f4d88086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565f4d6cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565f4a1c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565f4a1be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5faaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5faaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5faaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565f4a1bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (3026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564535ee856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564535ee5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564535ee8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73afe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73afea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73afe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73afe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564535e7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564535e7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564535e62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564535b12166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564535b11e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f73afe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73afe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73afe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564535b11d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (3027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570e5ea356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005570e5ea0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005570e5ea3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe21c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe21c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe21c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe21c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570e5e3923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005570e5e39086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005570e5e1df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005570e5acd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005570e5acce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe21c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe21c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe21c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570e5accd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (3028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/18691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d7064756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564d70644505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564d70647cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f7ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f7ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f7ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f7ee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d705dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564d705dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564d705c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564d70271166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564d70270e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7f7ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f7ee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f7ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d70270d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (3029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 =
# | ...
# `---data was truncated (10240/26564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf03f6956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cf03f66505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cf03f69cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb08d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb08d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb08d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb08d403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf03eff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cf03eff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cf03ee3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cf03b93166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cf03b92e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb08d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb08d4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb08d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf03b92d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (3030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>
# | ...
# `---data was truncated (10240/47764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055996a55756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055996a554505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055996a557cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87a9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87a9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87a9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87a9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055996a4ed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055996a4ed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055996a4d1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055996a181166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055996a180e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87a9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87a9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87a9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055996a180d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (3031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055627c82456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055627c821505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055627c824cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e56133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e5618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e56133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e5611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055627c7ba23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055627c7ba086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055627c79ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055627c44e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055627c44de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e5611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e5611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e5611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055627c44dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (3032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565189a5256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565189a4f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565189a52cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5122049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51220a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5122049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5122031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651899e823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651899e8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651899ccf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056518967c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056518967be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5122032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51220330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51220330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056518967bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (3033 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4957dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d4957d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d4957dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ccbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ccbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ccbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ccbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d49577223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d495772086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d495756f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d495406166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d495405e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ccbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ccbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ccbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d495405d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (3034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e9451456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e94511505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e94514cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1af933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1af98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1af933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1af91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e944aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e944aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e9448ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e9413e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e9413de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff1af91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1af91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1af91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e9413dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (3035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055570333d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055570333a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055570333dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ef3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ef358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ef3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ef351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557032d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005557032d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005557032b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555702f67166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555702f66e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4ef351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ef351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ef351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555702f66d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (3036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 
# | ...
# `---data was truncated (10240/26333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1a2b8d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1a2b8a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1a2b8dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93ea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93ea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93ea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93ea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1a2b2323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1a2b23086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1a2b07f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1a27b7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1a27b6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f93ea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93ea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93ea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1a27b6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (3037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b98d0856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b98d05505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b98d08cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93ee449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93ee4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93ee449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93ee431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b98c9e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b98c9e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b98c82f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b98932166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b98931e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f93ee432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93ee4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93ee4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b98931d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (3038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/12680) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056208a04356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056208a040505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056208a043cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbab449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbab4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbab449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbab431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562089fd923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562089fd9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562089fbdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562089c6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562089c6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdbab432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbab4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbab4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562089c6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (3039 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4ab27456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a4ab271505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a4ab274cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd39a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd39a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd39a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd39a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4ab20a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a4ab20a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a4ab1eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a4aae9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a4aae9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd39a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd39a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd39a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4aae9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (3040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 
# | ...
# `---data was truncated (10240/28361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bad7ef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558bad7ec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558bad7efcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9609e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9609ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9609e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9609e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bad78523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558bad785086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558bad769f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558bad419166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558bad418e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9609e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9609e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9609e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bad418d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (3041 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2e04dc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2e04d9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2e04dccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41d0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41d0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41d0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41d0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2e047223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f2e0472086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f2e0456f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f2e0106166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f2e0105e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f41d0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41d0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41d0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2e0105d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (3042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vect
# | ...
# `---data was truncated (10240/24229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a649f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562a649f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562a649f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b8ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b8ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b8ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b8ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a6498d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562a6498d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562a64971f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562a64621166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562a64620e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3b8ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b8ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b8ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a64620d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (3043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e39c6056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559e39c5d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559e39c60cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5411a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5411aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5411a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5411a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e39bf623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559e39bf6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559e39bdaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559e3988a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559e39889e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5411a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5411a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5411a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e39889d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (3044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601e9db956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005601e9db6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005601e9db9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bf3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bf398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bf3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bf391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601e9d4f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005601e9d4f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005601e9d33f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005601e99e3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005601e99e2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8bf391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bf391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bf391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601e99e2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (3045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a2c38756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555a2c384505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555a2c387cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0268b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0268b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0268b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0268b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a2c31d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555a2c31d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555a2c301f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555a2bfb1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555a2bfb0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0268b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0268b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0268b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a2bfb0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (3046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055869f05a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055869f057505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055869f05acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48a1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48a198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48a1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48a191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055869eff023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055869eff0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055869efd4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055869ec84166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055869ec83e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f48a191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48a191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48a191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055869ec83d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (3047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637d8af156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637d8aee505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637d8af1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b90133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b9018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b90133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b9011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637d8a8723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005637d8a87086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005637d8a6bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005637d871b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005637d871ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b9011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b9011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b9011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637d871ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (3048 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vundefined_bf16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vundefined_bf16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vundefined_bf16m1() #0 {
# | entry:
# |   ret <vscale x 4 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vundefined_bf16m2() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vundefined_bf16m4() #0 {
# | entry:
# |   ret <vscale x 16 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vundefined_bf16m8() #0 {
# | entry:
# |   ret <vscale x 32 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vundefined_bf16mf4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vundefined_bf16mf4x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vundefined_bf16mf4x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vundefined_bf16mf4x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vundefined_bf16mf4x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vundefined_bf16mf4x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vundefined_bf16mf4x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vundefined_bf16mf2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vundefined_bf16mf2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vundefined_bf16mf2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vundefined_bf16mf2x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vundefined_bf16mf2x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vundefined_bf16mf2x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vundefined_bf16mf2x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vundefined_bf16m1x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vundefined_bf16m1x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vundefined_bf16m1x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vundefined_bf16m1x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vundefined_bf16m1x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vundefined_bf16m1x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vundefined_bf16m1x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vundefined_bf16m2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vundefined_bf16m2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vundefined_bf16m2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vundefined_bf16m4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad63f7356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ad63f70505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ad63f73cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cf9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cf90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cf9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cf9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad63f0923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ad63f09086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ad63eedf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ad63b9d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ad63b9ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8cf9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cf90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cf90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad63b9cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (3049 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a52281656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a522813505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a522816cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76e4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76e478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76e4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76e471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5227ac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a5227ac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a522790f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a522440166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a52243fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f76e471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76e471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76e471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a52243fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (3050 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef4ee7756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ef4ee74505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ef4ee77cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f8e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f8e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f8e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f8e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef4ee0d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ef4ee0d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ef4edf1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ef4eaa1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ef4eaa0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9f8e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f8e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f8e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef4eaa0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (3051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055caf4ac856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055caf4ac5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055caf4ac8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa423449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4234a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa423449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa423431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caf4a5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055caf4a5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055caf4a42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055caf46f2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055caf46f1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa423432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4234330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4234330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055caf46f1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (3052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055980f43856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055980f435505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055980f438cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d14649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d14649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d14631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055980f3ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055980f3ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055980f3b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055980f062166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055980f061e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d14632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d146330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055980f061d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (3053 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d694fb056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d694fad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d694fb0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1268733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f126878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1268733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f126871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d694f4623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d694f46086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d694f2af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d694bda166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d694bd9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f126871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f126871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f126871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d694bd9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (3054 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2b3ed356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2b3ed0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2b3ed3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1326b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1326b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1326b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1326b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2b3e6923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f2b3e69086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f2b3e4df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f2b3afd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f2b3afce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1326b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1326b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1326b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2b3afcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (3055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d0e3c056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561d0e3bd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561d0e3c0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4792449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47924a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4792449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4792431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d0e35623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561d0e356086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561d0e33af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561d0dfea166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561d0dfe9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4792432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47924330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47924330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d0dfe9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (3056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c240e056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c240dd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c240e0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23dd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23dd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23dd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23dd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c2407623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c24076086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c2405af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c23d0a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c23d09e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f23dd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23dd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23dd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c23d09d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (3057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056206fe5956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056206fe56505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056206fe59cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f032141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03214725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f032141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0321403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056206fdef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056206fdef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056206fdd3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056206fa83166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056206fa82e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0321404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03214050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03214050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056206fa82d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (3058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592af8fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005592af8f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005592af8fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d11333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d1138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d11333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d1131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592af89223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005592af892086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005592af876f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005592af526166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005592af525e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2d1131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d1131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d1131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592af525d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (3059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c174f3a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c174f37505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c174f3acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5146c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5146ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5146c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5146c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c174ed023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c174ed0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c174eb4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c174b64166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c174b63e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5146c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5146c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5146c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c174b63d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (3060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 
# | ...
# `---data was truncated (10240/21465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055999c98c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055999c989505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055999c98ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab26b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab26b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab26b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab26b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055999c92223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055999c922086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055999c906f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055999c5b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055999c5b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fab26b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab26b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab26b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055999c5b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (3061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2b267a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b2b2677505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b2b267acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff09b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff09b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff09b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff09b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2b261023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b2b2610086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b2b25f4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b2b22a4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b2b22a3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff09b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff09b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff09b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2b22a3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (3062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c  -check-prefix=RV32ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a43a9bd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a43a9ba505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a43a9bdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d8f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d8f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d8f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d8f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a43a95323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a43a953086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a43a937f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a43a5e7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a43a5e6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7d8f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d8f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d8f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a43a5e6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (3063 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055caf40a056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055caf409d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055caf40a0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdac231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caf403623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055caf4036086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055caf401af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055caf3cca166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055caf3cc9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbdac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdac2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055caf3cc9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (3064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de9c86556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055de9c862505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055de9c865cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1840933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f184098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1840933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f184091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de9c7fb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055de9c7fb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055de9c7dff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055de9c48f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055de9c48ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f184091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f184091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f184091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de9c48ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (3065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | de
# | ...
# `---data was truncated (10240/12091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d6a1ab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559d6a1a8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559d6a1abcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7b6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7b698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7b6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7b691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d6a14123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559d6a141086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559d6a125f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559d69dd5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559d69dd4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa7b691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7b691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7b691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d69dd4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (3066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055addb5d056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055addb5cd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055addb5d0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c36b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c36b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c36b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c36b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055addb56623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055addb566086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055addb54af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055addb1fa166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055addb1f9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5c36b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c36b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c36b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055addb1f9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (3067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %1, <vsc
# | ...
# `---data was truncated (10240/12290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562855c4956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562855c46505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562855c49cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31d1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31d198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31d1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31d191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562855bdf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562855bdf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562855bc3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562855873166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562855872e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f31d191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31d191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31d191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562855872d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (3068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0fd7dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e0fd7da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e0fd7ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29b7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0fd77323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e0fd773086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e0fd757f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e0fd407166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e0fd406e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f29b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29b78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0fd406d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (3069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c8a04c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555c8a049505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555c8a04ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f404e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f404e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f404e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f404e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c89fe223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555c89fe2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555c89fc6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555c89c76166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555c89c75e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f404e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f404e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f404e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c89c75d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (3070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale
# | ...
# `---data was truncated (10240/12129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620a181156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005620a180e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005620a1811cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa54b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa54b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa54b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa54b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620a17a723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005620a17a7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005620a178bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005620a143b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005620a143ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa54b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa54b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa54b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620a143ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (3071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9a743856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b9a7435505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b9a7438cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45fa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45fa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45fa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45fa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9a73ce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b9a73ce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b9a73b2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b9a7062166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b9a7061e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f45fa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45fa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45fa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9a7061d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (3072 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9355dd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f9355da505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f9355ddcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2b9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2b92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2b9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2b9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f93557323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f935573086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f935557f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f935207166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f935206e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff2b9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2b92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2b92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f935206d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (3073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055877f9c356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055877f9c0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055877f9c3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8963105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f896315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8963105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89630ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055877f95923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055877f959086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055877f93df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055877f5ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055877f5ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f89630eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89630ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89630ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055877f5ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (3074 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6eafc856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e6eafc5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e6eafc8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7df733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7df78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7df733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7df71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6eaf5e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e6eaf5e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e6eaf42f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e6eabf2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e6eabf1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd7df71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7df71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7df71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6eabf1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-fma.c (3075 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf    -target-abi aapcs    -target-cpu cortex-a7    -mfloat-abi hard    -ffreestanding    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-none-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %accum.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %accum, ptr %accum.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %accum.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %accum.addr = alloca <4 x float>, align 8
# |   %lhs.addr = alloca <4 x float>, align 8
# |   %rhs.addr = alloca <4 x float>, align 8
# |   store <4 x float> %accum, ptr %accum.addr, align 8
# |   store <4 x float> %lhs, ptr %lhs.addr, align 8
# |   store <4 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x float>, ptr %accum.addr, align 8
# |   %1 = load <4 x float>, ptr %lhs.addr, align 8
# |   %2 = load <4 x float>, ptr %rhs.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store <4 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <2 x float>, align 8
# |   %__p1.addr.i.i = alloca <2 x float>, align 8
# |   %__p2.addr.i.i = alloca <2 x float>, align 8
# |   %__ret.i.i = alloca <2 x float>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <2 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <2 x float> %7, ptr %__p2.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %11 = bitcast <8 x i8> %8 to <2 x float>
# |   %12 = bitcast <8 x i8> %9 to <2 x float>
# |   %13 = bitcast <8 x i8> %10 to <2 x float>
# |   %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11)
# |   store <2 x float> %14, ptr %ref.tmp.i.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8
# |   store <2 x float> %15, ptr %__ret.i.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i.i, align 8
# |   store <2 x float> %16, ptr %__ret.i, align 8
# |   %17 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x float>, align 8
# |   %__p1.addr.i.i = alloca <4 x float>, align 8
# |   %__p2.addr.i.i = alloca <4 x float>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 8
# |   %ref.tmp.i.i = alloca <16 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 8
# |   %.compoundliteral.i = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <4 x float> %9, ptr %__p2.addr.i.i, align 8
# |   %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8
# |   %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8
# |   %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8
# |   %13 = bitcast <16 x i8> %10 to <4 x float>
# |   %14 = bitcast <16 x i8> %11 to <4 x float>
# |   %15 = bitcast <16 x i8> %12 to <4 x float>
# |   %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13)
# |   store <4 x float> %16, ptr %ref.tmp.i.i, align 8
# |   %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8
# |   store <4 x float> %17, ptr %__ret.i.i, align 8
# |   %18 = load <4 x float>, ptr %__ret.i.i, align 8
# |   store <4 x float> %18, ptr %__ret.i, align 8
# |   %19 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %19
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005637020b056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637020ad505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637020b0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f283eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f283eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f283eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f283eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056370204623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563702046086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056370202af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563701cda166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563701cd9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f283eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f283eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f283eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563701cd9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (3076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625eb4f256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625eb4ef505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625eb4f2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd2b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd2b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd2b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd2b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625eb48823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005625eb488086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005625eb46cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005625eb11c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005625eb11be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd2b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd2b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd2b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625eb11bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (3077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/63510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b91ba756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555b91ba4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555b91ba7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3828933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f382898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3828933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f382891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b91b3d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555b91b3d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555b91b21f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555b917d1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555b917d0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f382891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f382891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f382891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b917d0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (3078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, a
# | ...
# `---data was truncated (10240/43486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e061aa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562e061a7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562e061aacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a5d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a5d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a5d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a5d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e0614023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562e06140086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562e06124f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562e05dd4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562e05dd3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3a5d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a5d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a5d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e05dd3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (3079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9f531956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d9f5316505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d9f5319cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b20333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b2038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b20333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b2031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9f52af23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d9f52af086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d9f5293f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d9f4f43166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d9f4f42e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3b2031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b2031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b2031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9f4f42d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (3080 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |  
# | ...
# `---data was truncated (10240/29535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9661a256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c96619f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c9661a2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8b0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8b0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8b0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8b0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c96613823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c966138086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c96611cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c965dcc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c965dcbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd8b0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8b0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8b0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c965dcbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (3081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.a
# | ...
# `---data was truncated (10240/32394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a27f20356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a27f200505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a27f203cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec4b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec4b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec4b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec4b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a27f19923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a27f199086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a27f17df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a27ee2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a27ee2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec4b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec4b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec4b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a27ee2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (3082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqr
# | ...
# `---data was truncated (10240/28170) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556849bfc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556849bf9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556849bfccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e4ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e4aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e4ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e4ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556849b9223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556849b92086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556849b76f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556849826166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556849825e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2e4ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e4ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e4ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556849825d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (3083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = loa
# | ...
# `---data was truncated (10240/33443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c9c43756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560c9c434505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560c9c437cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a17849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a17849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a17831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c9c3cd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560c9c3cd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560c9c3b1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560c9c061166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560c9c060e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3a17832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a178330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c9c060d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (3084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fa4d5756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556fa4d54505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556fa4d57cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fa4ced23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556fa4ced086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556fa4cd1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556fa4981166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556fa4980e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7aa5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fa4980d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (3085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562018acb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562018ac8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562018acbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6581249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65812a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6581249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6581231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562018a6123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562018a61086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562018a45f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005620186f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005620186f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6581232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65812330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65812330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620186f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (3086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562366c2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562366c29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562366c2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5b4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5b495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5b4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5b48ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562366bc223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562366bc2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562366ba6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562366856166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562366855e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe5b48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5b48ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5b48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562366855d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (3087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb9a04e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cb9a04b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cb9a04ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7046333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f704638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7046333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f704631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb99fe423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cb99fe4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cb99fc8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cb99c78166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cb99c77e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f704631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f704631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f704631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb99c77d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (3088 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b67b43f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b67b43c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b67b43fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e0e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e0e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e0e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e0e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b67b3d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b67b3d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b67b3b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b67b069166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b67b068e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4e0e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e0e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e0e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b67b068d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (3089 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-unknown-linux-gnu"
# | 
# | @__riscv_cpu_model = external dso_local global { i32, i64, i64 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1808
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372035378380799
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 1152921505839391232
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775800
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 102892581
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775543
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 337970694
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b474f3f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b474f3c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b474f3fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66b941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66b94725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66b941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66b9403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b474ed523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b474ed5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b474eb9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b474b69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b474b68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f66b9404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66b94050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66b94050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b474b68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-vcadd.c (3090 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic  -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.3a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i)
# |   %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i)
# |   %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i)
# |   %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %result = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i)
# |   %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i)
# |   %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i)
# |   %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i)
# |   %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 
# | ...
# `---data was truncated (10240/13572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# |  #0 0x0000557e1f97156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557e1f96e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557e1f971cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5b821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5b82725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5b821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5b8203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e1f90723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557e1f907086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557e1f8ebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557e1f59b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557e1f59ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa5b8204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5b82050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5b82050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e1f59ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (3091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a406dda56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a406dd7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a406ddacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f489e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f489e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f489e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f489e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a406d7023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a406d70086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a406d54f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a406a04166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a406a03e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f489e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f489e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f489e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a406a03d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (3092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652b290156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005652b28fe505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005652b2901cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe148a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe148aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe148a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe148a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652b289723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005652b2897086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005652b287bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005652b252b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005652b252ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe148a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe148a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe148a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652b252ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (3093 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %
# | ...
# `---data was truncated (10240/13690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056418e92256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056418e91f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056418e922cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae4ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae4caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae4ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae4ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056418e8b823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056418e8b8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056418e89cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056418e54c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056418e54be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fae4ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae4ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae4ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056418e54bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (3094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563d3bfb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005563d3bf8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005563d3bfbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6245533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f624558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6245533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f624551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563d3b9123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005563d3b91086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005563d3b75f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005563d3825166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005563d3824e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f624551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f624551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f624551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563d3824d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (3095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055610eeef56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055610eeec505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055610eeefcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd17133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd1718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd17133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd1711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055610ee8523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055610ee85086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055610ee69f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055610eb19166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055610eb18e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbd1711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd1711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd1711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055610eb18d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (3096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dc546b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556dc5468505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556dc546bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa294649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2946a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa294649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa294631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dc540123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556dc5401086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556dc53e5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556dc5095166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556dc5094e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa294632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2946330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2946330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dc5094d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (3097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b072d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563b072d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563b072d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f83d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f83d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f83d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f83d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b0726b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563b0726b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563b0724ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563b06eff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563b06efee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3f83d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f83d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f83d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b06efed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (3098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eef843256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eef842f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eef8432cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f432e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f432e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f432e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f432e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eef83c823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eef83c8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eef83acf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eef805c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eef805be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f432e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f432e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f432e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eef805bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (3099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbea01656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bbea013505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bbea016cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46f1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46f10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46f1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46f1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbe9fac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bbe9fac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bbe9f90f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bbe9c40166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bbe9c3fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f46f1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46f10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46f10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbe9c3fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (3100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6bb00356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a6bb000505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a6bb003cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd07ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd07cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd07ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd07ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6baf9923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a6baf99086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a6baf7df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a6bac2d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a6bac2ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd07ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd07ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd07ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6bac2cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (3101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619e7d4f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005619e7d4c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005619e7d4fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9868d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9868d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9868d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9868d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619e7ce523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005619e7ce5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005619e7cc9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005619e7979166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005619e7978e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9868d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9868d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9868d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619e7978d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (3102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.ris
# | ...
# `---data was truncated (10240/18562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559437d6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559437d6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559437d6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7316649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73166a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7316649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7316631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559437d0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559437d03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559437ce7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559437997166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559437996e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7316632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73166330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73166330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559437996d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (3103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/25287) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055710222b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557102228505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055710222bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bbf305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bbf35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bbf305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bbf2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571021c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005571021c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005571021a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557101e55166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557101e54e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0bbf2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bbf2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bbf2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557101e54d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (3104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056335b63a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056335b637505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056335b63acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f710e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f710e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f710e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f710e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056335b5d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056335b5d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056335b5b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056335b264166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056335b263e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f710e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f710e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f710e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056335b263d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (3105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/41651) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f750b9456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f750b91505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f750b94cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7681849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76818a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7681849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7681831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f750b2a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f750b2a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f750b0ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f7507be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f7507bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7681832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76818330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76818330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7507bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (3106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0f3db256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f0f3daf505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f0f3db2cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a36133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a3618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a36133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a3611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0f3d4823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f0f3d48086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f0f3d2cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f0f39dc166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f0f39dbe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4a3611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a3611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a3611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0f39dbd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (3107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643b5c1056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005643b5c0d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005643b5c10cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0495933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f049598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0495933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f049591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643b5ba623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005643b5ba6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005643b5b8af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005643b583a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005643b5839e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f049591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f049591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f049591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643b5839d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (3108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555e3d0556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005555e3d02505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005555e3d05cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b7ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b7ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b7ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b7ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555e3c9b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005555e3c9b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005555e3c7ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005555e392f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005555e392ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b7ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b7ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b7ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555e392ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (3109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/14832) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6bad4956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c6bad46505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c6bad49cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f248d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f248d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f248d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f248d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6bacdf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c6bacdf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c6bacc3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c6ba973166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c6ba972e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f248d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f248d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f248d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6ba972d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (3110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f2b13f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563f2b13c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563f2b13fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f430ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f430ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f430ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f430eced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f2b0d523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563f2b0d5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563f2b0b9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563f2ad69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563f2ad68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f430eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f430ecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f430ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f2ad68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (3111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056112c0df56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056112c0dc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056112c0dfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d91e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d91ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d91e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d91e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056112c07523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056112c075086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056112c059f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056112bd09166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056112bd08e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d91e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d91e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d91e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056112bd08d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (3112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align
# | ...
# `---data was truncated (10240/29111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609d23fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005609d23fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005609d23fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f274de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f274dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f274de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f274de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609d239323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005609d2393086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005609d2377f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005609d2027166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005609d2026e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f274de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f274de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f274de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609d2026d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (3113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559c358256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005559c357f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005559c3582cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc370449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3704a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc370449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc370431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559c351823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005559c3518086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005559c34fcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005559c31ac166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005559c31abe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc370432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3704330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3704330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559c31abd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (3114 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_zt0() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_zt0() #1 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_zt0() #2 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_zt0() #3 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_zt0() #4 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_za_zt0() #5 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_za_zt0() #6 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_za_zt0() #7 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_za_zt0() #8 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_za_zt0() #9 {
# | entry:
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609ab75956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005609ab756505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005609ab759cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a2e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a2e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a2e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a2e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609ab6ef23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005609ab6ef086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005609ab6d3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005609ab383166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005609ab382e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1a2e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a2e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a2e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609ab382d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x000055e7d3cbc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7d3cb9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7d3cbccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd74b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd74b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd74b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd74b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7d3c5223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7d3c52086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7d3c36f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7d38e6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7d38e5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd74b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd74b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd74b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7d38e5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (3115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/30690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2dd2e856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d2dd2e5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d2dd2e8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8a6d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8a6d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8a6d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8a6ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2dd27e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d2dd27e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d2dd262f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d2dcf12166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d2dcf11e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8a6ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8a6cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8a6cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2dcf11d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (3116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fa176f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558fa176c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558fa176fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5580f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5580f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5580f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5580f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fa170523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558fa1705086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558fa16e9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558fa1399166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558fa1398e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5580f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5580f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5580f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fa1398d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (3117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555be9d2056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555be9d1d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555be9d20cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e3f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e3f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e3f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e3f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555be9cb623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555be9cb6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555be9c9af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555be994a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555be9949e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e3f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e3f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e3f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555be9949d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (3118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bb7c5856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564bb7c55505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564bb7c58cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe64a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe64a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe64a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe64a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bb7bee23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564bb7bee086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564bb7bd2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564bb7882166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564bb7881e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe64a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe64a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe64a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bb7881d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (3119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558e7e4256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005558e7e3f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005558e7e42cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa78d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa78d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa78d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa78d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558e7dd823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005558e7dd8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005558e7dbcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005558e7a6c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005558e7a6be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa78d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa78d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa78d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558e7a6bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (3120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d73cdee56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d73cdeb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d73cdeecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f532ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f532ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f532ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f532ba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d73cd8423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d73cd84086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d73cd68f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d73ca18166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d73ca17e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f532ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f532ba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f532ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d73ca17d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (3121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @or_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %or = or <32 x i8> %0, %1
# |   store <32 x i8> %or, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 
# | ...
# `---data was truncated (10240/30877) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000564f48d3956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564f48d36505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564f48d39cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c68d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c68d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c68d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c68d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f48ccf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564f48ccf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564f48cb3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564f48963166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564f48962e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1c68d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c68d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c68d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f48962d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (3122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb5de5156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fb5de4e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fb5de51cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb086449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb086449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb086431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb5dde723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fb5dde7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fb5ddcbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fb5da7b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fb5da7ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb086432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0864330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb5da7ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (3123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055733cc7356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055733cc70505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055733cc73cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d14733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d1478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d14733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d1471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055733cc0923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055733cc09086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055733cbedf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055733c89d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055733c89ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d1471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d1471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d1471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055733c89cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-vget.c (3124 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -target-abi apcs-gnu    -target-cpu cortex-a8    -mfloat-abi soft    -target-feature +soft-float-abi    -ffreestanding    -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x float> @low_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr
# | ...
# `---data was truncated (10240/15571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f0457156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560f0456e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560f04571cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61ca133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61ca18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61ca133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61ca11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f0450723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560f04507086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560f044ebf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560f0419b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560f0419ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f61ca11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61ca11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61ca11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f0419ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (3125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c6096756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562c60964505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562c60967cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27eaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27eaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27eaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27eaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c608fd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562c608fd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562c608e1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562c60591166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562c60590e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f27eaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27eaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27eaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c60590d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (3126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558510f9f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558510f9c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558510f9fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd01fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd01fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd01fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd01fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558510f3523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558510f35086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558510f19f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558510bc9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558510bc8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd01fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd01fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd01fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558510bc8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (3127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fa2ab556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564fa2ab2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564fa2ab5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff16761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1676725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff16761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff167603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fa2a4b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564fa2a4b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564fa2a2ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564fa26df166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564fa26dee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff167604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1676050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1676050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fa26ded71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (3128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055824d42a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055824d427505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055824d42acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc78661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7866725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc78661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc786603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055824d3c023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055824d3c0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055824d3a4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055824d054166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055824d053e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc786604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7866050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7866050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055824d053d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/cx-complex-range-real.c (3129 of 27911)
******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %mul.rl = fmul float %a.real, %0
# |   %mul.il = fmul float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.il, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul.rl = fmul float %.real, %0
# |   %mul.il = fmul float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %mul.rl, ptr %.realp1, align 4
# |   store float %mul.il, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca float, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul.rl = fmul float %0, %b.real
# |   %mul.ir = fmul float %0, %b.imag
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.ir, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = fdiv float %a.real, %0
# |   %2 = fdiv float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %1, ptr %retval.realp, align 4
# |   store float %2, ptr %retval.imagp, align 4
# |   %3 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %2 = fdiv float %.real, %0
# |   %3 = fdiv float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %2, ptr %.realp1, align 4
# |   store float %3, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load double, ptr %a.imagp, align 8
# |   %2 = load double, ptr %b.addr, align 8
# |   %3 = fdiv double %a.real, %2
# |   %4 = fdiv double %a.imag, %2
# |   %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1
# |   store double %3, ptr %retval.realp, align 8
# |   store double %4, ptr %retval.imagp, align 8
# |   %5 = load { double, double }, ptr %retval, align 8
# |   ret { double, double } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { double, double }, align 8
# |   %a.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %1, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %2 = load double, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   %b.real = load double, ptr %b.realp, align 8
# |   %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   %b.imag = load double, ptr %b.imagp, align 8
# |   %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2
# |   %3 = extractvalue { double, double } %call, 0
# |   %4 = extractvalue { double, double } %call, 1
# |   %conv = fptrunc double %3 to float
# |   %conv1 = fptrunc double %4 to float
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %conv, ptr %retval.realp, align 4
# |   store float %conv1, ptr %retval.imagp, align 4
# |   %5 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %5
# | }
# | 
# | declare { double, double } @__divdc3(double, double, double, double)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca double, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.real = load double, ptr %.realp, align 8
# |   %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   %.imag = load double, ptr %.imagp, align 8
# |   %2 = fdiv double %.real, %0
# |   %3 = fdiv double %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   store double %2, ptr %.realp1, align 8
# |   store double %3, ptr %.imagp2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %retval = alloca { x86_fp80, x86_fp80 }, align 16
# |   %b.addr = alloca x86_fp80, align 16
# |   store x86_fp80 %b, ptr %b.addr, align 16
# |   %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0
# |   %a.real = load x86_fp80, ptr %a.realp, align 16
# |   %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1
# |   %a.imag = load x86_fp80, ptr %a.imagp, align 16
# |   %0 = load x86_fp80, ptr %b.addr, align 16
# |   %1 = fdiv x86_fp80 %a.real, %0
# |   %2 = fdiv x86_fp80 %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1
# |   store x86_fp80 %1, ptr %retval.realp, align 16
# |   store x86_fp80 %2, ptr %retval.imagp, align 16
# |   %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16
# |   ret { x86_fp80, x86_fp80 } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %a.addr 
# | ...
# `---data was truncated (10240/11567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000557927b3256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557927b2f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557927b32cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe217849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe217849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe217831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557927ac823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557927ac8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557927aacf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055792775c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055792775be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe217832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2178330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055792775bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (3130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c38b59656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c38b593505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c38b596cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe83a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe83a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe83a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe83a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c38b52c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c38b52c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c38b510f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c38b1c0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c38b1bfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe83a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe83a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe83a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c38b1bfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (3131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b28a01256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b28a00f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b28a012cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f777b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f777b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f777b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f777b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b289fa823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b289fa8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b289f8cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b289c3c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b289c3be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f777b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f777b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f777b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b289c3bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (3132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1c945456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e1c9451505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e1c9454cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecd1305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecd135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecd1305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecd12ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1c93ea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e1c93ea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1c93cef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e1c907e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e1c907de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fecd12eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecd12ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecd12ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1c907dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (3133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr
# | ...
# `---data was truncated (10240/27541) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623ad04956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005623ad046505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005623ad049cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc40b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc40b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc40b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc40b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623acfdf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005623acfdf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005623acfc3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005623acc73166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005623acc72e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc40b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc40b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc40b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623acc72d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (3134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eba3a8b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055eba3a88505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055eba3a8bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa458533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa45858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa458533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa45851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eba3a2123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055eba3a21086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055eba3a05f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055eba36b5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055eba36b4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa45851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa45851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa45851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eba36b4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (3135 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aca08ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aca08aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aca08adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f417aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f417aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f417aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f417aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aca084323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aca0843086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aca0827f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aca04d7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aca04d6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f417aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f417aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f417aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aca04d6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (3136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055825addc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055825add9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055825addccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5937733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f593778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5937733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f593771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055825ad7223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055825ad72086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055825ad56f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055825aa06166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055825aa05e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f593771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f593771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f593771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055825aa05d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (3137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcb41fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fcb41fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fcb41fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c10133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c1018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c10133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c1011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcb419323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fcb4193086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fcb4177f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fcb3e27166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fcb3e26e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0c1011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c1011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c1011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcb3e26d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (3138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560af837456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560af8371505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560af8374cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4fa305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4fa35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4fa305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4fa2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560af830a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560af830a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560af82eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560af7f9e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560af7f9de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb4fa2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4fa2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4fa2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560af7f9dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (3139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e13029f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e13029c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e13029fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efff6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efff64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efff6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efff6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e13023523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e130235086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e130219f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e12fec9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e12fec8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efff6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efff64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efff64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e12fec8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (3140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfe9d2956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055cfe9d26505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055cfe9d29cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d95c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d95c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d95c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d95c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfe9cbf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055cfe9cbf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055cfe9ca3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055cfe9953166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055cfe9952e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8d95c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d95c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d95c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfe9952d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (3141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555df587d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555df587a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555df587dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9382c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9382ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9382c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9382c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555df581323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555df5813086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555df57f7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555df54a7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555df54a6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9382c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9382c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9382c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555df54a6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (3142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1beca456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e1beca1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e1beca4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4640333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f464038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4640333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f464031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1bec3a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e1bec3a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1bec1ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e1be8ce166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e1be8cde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f464031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f464031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f464031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1be8cdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (3143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2310c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2310c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2310c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a61049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a610a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a61049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a61031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f23105c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f23105c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f231040f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f230cf0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f230cefe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a61032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a610330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a610330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f230cefd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (3144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("risc
# | ...
# `---data was truncated (10240/14659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c7909356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561c79090505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561c79093cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59a5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59a58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59a5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59a5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c7902923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561c79029086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561c7900df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561c78cbd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561c78cbce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f59a5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59a58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59a58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c78cbcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (3145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vs
# | ...
# `---data was truncated (10240/10886) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cdec8f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562cdec8c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562cdec8fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa143449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1434a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa143449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa143431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cdec2523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562cdec25086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562cdec09f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562cde8b9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562cde8b8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa143432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1434330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1434330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cde8b8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (3146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e24b63a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e24b637505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e24b63acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8ca733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8ca78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8ca733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8ca71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e24b5d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e24b5d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e24b5b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e24b264166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e24b263e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe8ca71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8ca71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8ca71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e24b263d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (3147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055589771c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555897719505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055589771ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4118933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f411898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4118933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f411891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558976b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005558976b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555897696f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555897346166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555897345e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f411891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f411891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f411891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555897345d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (3148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"SmallDataLi
# | ...
# `---data was truncated (10240/10285) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558abf41e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558abf41b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558abf41ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b7e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b7e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b7e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b7e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558abf3b423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558abf3b4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558abf398f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558abf048166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558abf047e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6b7e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b7e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b7e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558abf047d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (3149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8
# | ...
# `---data was truncated (10240/60809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056273016156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056273015e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562730161cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3241533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f324158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3241533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f324151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627300f723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005627300f7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005627300dbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056272fd8b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056272fd8ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f324151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f324151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f324151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056272fd8ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (3150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625c679a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005625c6797505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005625c679acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e64d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e64d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e64d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e64d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625c673023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005625c6730086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005625c6714f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005625c63c4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005625c63c3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5e64d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e64d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e64d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625c63c3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (3151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d3f79156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558d3f78e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558d3f791cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d75649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d75649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d75631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d3f72723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558d3f727086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558d3f70bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558d3f3bb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558d3f3bae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3d75632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d756330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d3f3bad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (3152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c0fd5356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561c0fd50505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561c0fd53cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb42c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb42c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb42c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb42c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c0fce923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561c0fce9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561c0fccdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561c0f97d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561c0f97ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb42c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb42c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb42c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c0f97cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (3153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578ae73a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578ae737505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578ae73acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd28e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd28e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd28e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd28e8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578ae6d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578ae6d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578ae6b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578ae364166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578ae363e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd28e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd28e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd28e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578ae363d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (3154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.ad
# | ...
# `---data was truncated (10240/13903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa4a64856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fa4a645505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fa4a648cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19a2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa4a5de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fa4a5de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fa4a5c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fa4a272166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fa4a271e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f19a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19a24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa4a271d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (3155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfb72e056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bfb72dd505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bfb72e0cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a62705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a6275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a62705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a626ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfb727623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bfb7276086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bfb725af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bfb6f0a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bfb6f09e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7a626eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a626ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a626ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfb6f09d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (3156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056484b32e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056484b32b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056484b32ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24da61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24da6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24da61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24da603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056484b2c423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056484b2c4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056484b2a8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056484af58166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056484af57e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f24da604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24da6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24da6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056484af57d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (3157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e5d1ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556e5d1ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556e5d1edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feadd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feadd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feadd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feadd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e5d18323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556e5d183086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556e5d167f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556e5ce17166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556e5ce16e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007feadd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feadd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feadd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e5ce16d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (3158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558305eec56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558305ee9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558305eeccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f6441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f644725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f6441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f64403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558305e8223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558305e82086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558305e66f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558305b16166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558305b15e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8f64404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f644050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f644050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558305b15d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (3159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca60b0356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ca60b00505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ca60b03cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd6f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd6f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd6f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd6f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca60a9923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ca60a99086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ca60a7df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ca6072d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ca6072ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcd6f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd6f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd6f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca6072cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (3160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056507fb2b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056507fb28505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056507fb2bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc72b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc72b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc72b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc72b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056507fac123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056507fac1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056507faa5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056507f755166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056507f754e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc72b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc72b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc72b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056507f754d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (3161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.
# | ...
# `---data was truncated (10240/11504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab13e2356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ab13e20505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ab13e23cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faef1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faef1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faef1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faef1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab13db923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ab13db9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ab13d9df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ab13a4d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ab13a4ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007faef1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faef1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faef1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab13a4cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (3162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | 
# | ...
# `---data was truncated (10240/12652) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e88247556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e882472505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e882475cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90dc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90dc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90dc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90dc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e88240b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e88240b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e8823eff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e88209f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e88209ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f90dc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90dc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90dc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e88209ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (3163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdab20d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bdab20a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bdab20dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c36d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c36d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c36d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c36d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdab1a323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bdab1a3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bdab187f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bdaae37166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bdaae36e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5c36d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c36d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c36d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdaae36d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (3164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056369d41f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056369d41c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056369d41fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f3f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f3f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f3f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f3f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056369d3b523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056369d3b5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056369d399f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056369d049166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056369d048e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f3f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f3f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f3f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056369d048d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (3165 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# |  #0 0x0000563ae745356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563ae7450505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563ae7453cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7d6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7d658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7d6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7d651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ae73e923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563ae73e9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563ae73cdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563ae707d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563ae707ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc7d651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7d651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7d651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ae707cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (3166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f3bc1e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555f3bc1b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555f3bc1ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec0d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec0d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec0d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec0d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f3bbb423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555f3bbb4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555f3bb98f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555f3b848166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555f3b847e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fec0d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec0d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec0d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f3b847d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (3167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ed722b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559ed7228505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559ed722bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e70133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e7018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e70133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e7011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ed71c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559ed71c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559ed71a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559ed6e55166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559ed6e54e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9e7011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e7011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e7011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ed6e54d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (3168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb7917756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bb79174505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bb79177cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb40fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb40fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb40fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb40fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb7910d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bb7910d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bb790f1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bb78da1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bb78da0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb40fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb40fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb40fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb78da0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (3169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/22367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ee661056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562ee660d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562ee6610cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0be8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0be82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0be8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0be8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ee65a623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562ee65a6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562ee658af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562ee623a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562ee6239e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0be8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0be82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0be82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ee6239d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (3170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcb73e656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bcb73e3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bcb73e6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e29e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e29ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e29e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e29e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcb737c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bcb737c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bcb7360f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bcb7010166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bcb700fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7e29e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e29e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e29e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcb700fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (3171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b20851356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b208510505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b208513cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cbe133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cbe18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cbe133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cbe11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2084a923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b2084a9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b20848df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b20813d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b20813ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0cbe11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cbe11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cbe11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b20813cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (3172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, a
# | ...
# `---data was truncated (10240/30276) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055559808456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555598081505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555598084cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d79a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d79aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d79a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d79a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055559801a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055559801a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555597ffef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555597cae166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555597cade83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6d79a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d79a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d79a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555597cadd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (3173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565137a3356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000565137a30505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000565137a33cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b50649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b506a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b50649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b50631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651379c923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005651379c9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005651379adf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056513765d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056513765ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8b50632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b506330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b506330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056513765cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (3174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642d574456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005642d5741505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005642d5744cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94dd305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94dd35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94dd305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94dd2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642d56da23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005642d56da086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005642d56bef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005642d536e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005642d536de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f94dd2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94dd2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94dd2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642d536dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (3175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056452b1e756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056452b1e4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056452b1e7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c4ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c4caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c4ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c4ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056452b17d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056452b17d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056452b161f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056452ae11166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056452ae10e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3c4ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c4ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c4ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056452ae10d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (3176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/18353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561187f8356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561187f80505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561187f83cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8904849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89048a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8904849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8904831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561187f1923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561187f19086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561187efdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561187bad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561187bace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8904832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89048330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89048330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561187bacd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (3177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0cbbe356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c0cbbe0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c0cbbe3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd05bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd05bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd05bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd05bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0cbb7923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c0cbb79086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c0cbb5df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c0cb80d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c0cb80ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd05bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd05bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd05bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0cb80cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (3178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561417fea56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561417fe7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561417feacab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12afb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12afb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12afb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12afb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561417f8023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561417f80086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561417f64f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561417c14166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561417c13e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f12afb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12afb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12afb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561417c13d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (3179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/15211) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056487f48c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056487f489505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056487f48ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bb6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bb638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bb6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bb631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056487f42223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056487f422086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056487f406f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056487f0b6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056487f0b5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4bb631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bb631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bb631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056487f0b5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/SystemZ/zvector.c (3180 of 27911)
******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector  -emit-llvm -o - -W -Wall -Werror  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c"
# | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
# | target triple = "s390x-unknown-linux-gnu"
# | 
# | @sc2 = global <16 x i8> zeroinitializer, align 8
# | @sc = global <16 x i8> zeroinitializer, align 8
# | @uc2 = global <16 x i8> zeroinitializer, align 8
# | @uc = global <16 x i8> zeroinitializer, align 8
# | @ss2 = global <8 x i16> zeroinitializer, align 8
# | @ss = global <8 x i16> zeroinitializer, align 8
# | @us2 = global <8 x i16> zeroinitializer, align 8
# | @us = global <8 x i16> zeroinitializer, align 8
# | @si2 = global <4 x i32> zeroinitializer, align 8
# | @si = global <4 x i32> zeroinitializer, align 8
# | @ui2 = global <4 x i32> zeroinitializer, align 8
# | @ui = global <4 x i32> zeroinitializer, align 8
# | @sl2 = global <2 x i64> zeroinitializer, align 8
# | @sl = global <2 x i64> zeroinitializer, align 8
# | @ul2 = global <2 x i64> zeroinitializer, align 8
# | @ul = global <2 x i64> zeroinitializer, align 8
# | @slll2 = global <1 x i128> zeroinitializer, align 8
# | @slll = global <1 x i128> zeroinitializer, align 8
# | @ulll2 = global <1 x i128> zeroinitializer, align 8
# | @ulll = global <1 x i128> zeroinitializer, align 8
# | @fd2 = global <2 x double> zeroinitializer, align 8
# | @fd = global <2 x double> zeroinitializer, align 8
# | @bc2 = global <16 x i8> zeroinitializer, align 8
# | @bc = global <16 x i8> zeroinitializer, align 8
# | @bs2 = global <8 x i16> zeroinitializer, align 8
# | @bs = global <8 x i16> zeroinitializer, align 8
# | @bi2 = global <4 x i32> zeroinitializer, align 8
# | @bi = global <4 x i32> zeroinitializer, align 8
# | @bl2 = global <2 x i64> zeroinitializer, align 8
# | @bl = global <2 x i64> zeroinitializer, align 8
# | @blll2 = global <1 x i128> zeroinitializer, align 8
# | @blll = global <1 x i128> zeroinitializer, align 8
# | @cnt = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_assign() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_pos() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_neg() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %sub = sub <16 x i8> zeroinitializer, %0
# |   store volatile <16 x i8> %sub, ptr @sc, align 8
# |   %1 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %sub1 = sub <8 x i16> zeroinitializer, %1
# |   store volatile <8 x i16> %sub1, ptr @ss, align 8
# |   %2 = load volatile <4 x i32>, ptr @si2, align 8
# |   %sub2 = sub <4 x i32> zeroinitializer, %2
# |   store volatile <4 x i32> %sub2, ptr @si, align 8
# |   %3 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %sub3 = sub <2 x i64> zeroinitializer, %3
# |   store volatile <2 x i64> %sub3, ptr @sl, align 8
# |   %4 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %sub4 = sub <1 x i128> zeroinitializer, %4
# |   store volatile <1 x i128> %sub4, ptr @slll, align 8
# |   %5 = load volatile <2 x double>, ptr @fd2, align 8
# |   %fneg = fneg <2 x double> %5
# |   store volatile <2 x double> %fneg, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_preinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_postinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_predec() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %dec = add <16 x i8> %0, splat (i8 -1)
# |   store volatile <16 x i8> %dec, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %dec1 = add <16 x i8> %1, splat (i8 -1)
# |   store volatile <16 x i8> %dec1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %dec2 = add <8 x i16> %2, splat (i16 -1)
# |   store volatile <8 x i16> %dec2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %dec3 = add <8 x i16> %3, splat (i16 -1)
# |   store volatile <8 x i16> %dec3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %dec4 = add <4 x i32> %4, splat (i32 -1)
# |   store volatile <4 x i32> %dec4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %dec5 = add <4 x i32> %5, splat (i32 -1)
# |   store volatile <4 x i32> %dec5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %dec6 = add <2 x i64> %6, splat (i64 -1)
# |   store volatile <2 x i64> %dec6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %dec7 = add <2 x i64> %7, splat (i64 -1)
# |   store volatile <2 x i64> %dec7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %dec8 = add <1 x i128> %8, splat (i128 -1)
# |   store volatile <1 x i128> %dec8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %dec
# | ...
# `---data was truncated (10240/152876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560472cdf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560472cdc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560472cdfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b62849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b62849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b62831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560472c7523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560472c75086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560472c59f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560472909166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560472908e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2b62832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b628330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560472908d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (3181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c22ded56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561c22dea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561c22dedcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ba7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ba778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ba7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ba771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c22d8323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561c22d83086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561c22d67f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561c22a17166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561c22a16e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8ba771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ba771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ba771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c22a16d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/packed-structure.c (3182 of 27911)
******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | %struct.s0 = type { i32, i32 }
# | %struct.s1 = type { i32, i32 }
# | %struct.s2 = type { i32, i32 }
# | %struct.s3 = type <{ i16, i32, [10 x i8] }>
# | 
# | @s0_align_x = global i32 4, align 4
# | @s0_align_y = global i32 1, align 4
# | @s0_align = global i32 4, align 4
# | @s1_align_x = global i32 1, align 4
# | @s1_align_y = global i32 1, align 4
# | @s1_align = global i32 1, align 4
# | @s2_align_x = global i32 2, align 4
# | @s2_align_y = global i32 2, align 4
# | @s2_align = global i32 2, align 4
# | @s3_1 = global i32 1, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @test3(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %anInt, align 2
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# |  #0 0x0000555a6397a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555a63977505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555a6397acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7caa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7caa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7caa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7caa431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a6391023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555a63910086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555a638f4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555a635a4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555a635a3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7caa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7caa4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7caa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a635a3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (3183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f3487456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562f34871505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562f34874cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85a0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f3480a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562f3480a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562f347eef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562f3449e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562f3449de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f85a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85a08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f3449dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (3184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559eccffb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559eccff8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559eccffbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47cab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47cab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47cab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47cab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559eccf9123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559eccf91086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559eccf75f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559eccc25166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559eccc24e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47cab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47cab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47cab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559eccc24d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (3185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640c572256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005640c571f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005640c5722cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10d9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10d998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10d9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10d991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640c56b823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005640c56b8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005640c569cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005640c534c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005640c534be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f10d991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10d991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10d991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640c534bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (3186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649bbb9c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005649bbb99505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005649bbb9ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2195e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2195ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2195e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2195e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649bbb3223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005649bbb32086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005649bbb16f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005649bb7c6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005649bb7c5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2195e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2195e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2195e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649bb7c5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (3187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561ceef956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005561ceef6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005561ceef9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facca449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facca4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facca449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facca431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561cee8f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005561cee8f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005561cee73f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005561ceb23166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005561ceb22e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007facca432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facca4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facca4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561ceb22d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (3188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fabef4556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055fabef42505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055fabef45cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ed1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ed118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ed1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ed111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fabeedb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055fabeedb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055fabeebff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055fabeb6f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055fabeb6ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9ed111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ed111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ed111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fabeb6ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (3189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056301df1156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056301df0e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056301df11cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6105049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61050a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6105049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6105031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056301dea723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056301dea7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056301de8bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056301db3b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056301db3ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6105032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61050330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61050330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056301db3ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (3190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562811de856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562811de5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562811de8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4c6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4c6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4c6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4c6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562811d7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562811d7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562811d62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562811a12166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562811a11e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd4c6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4c6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4c6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562811a11d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (3191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa1e1ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055aa1e1aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055aa1e1adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee2b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee2b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee2b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa1e14323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055aa1e143086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055aa1e127f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055aa1ddd7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055aa1ddd6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fee2b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee2b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee2b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa1ddd6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (3192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x d
# | ...
# `---data was truncated (10240/19901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f247b0556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f247b02505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f247b05cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f939f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f939f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f939f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f939f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f247a9b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f247a9b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f247a7ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f24772f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f24772ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f939f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f939f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f939f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f24772ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (3193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562baee4356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562baee40505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562baee43cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00ef733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00ef78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00ef733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00ef71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562baedd923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562baedd9086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562baedbdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562baea6d166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562baea6ce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f00ef71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00ef71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00ef71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562baea6cd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (3194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589acd1056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005589acd0d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005589acd10cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96c4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96c4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96c4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96c4e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589acca623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005589acca6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005589acc8af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005589ac93a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005589ac939e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f96c4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96c4e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96c4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589ac939d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-riscv.c (3195 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 10, ptr %res, align 4
# |   store volatile i32 11, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637ee8fa56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005637ee8f7505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005637ee8facab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d07849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d078a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d07849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d07831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637ee89023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005637ee890086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005637ee874f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005637ee524166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005637ee523e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d07832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d078330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d078330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637ee523d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (3196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c5feb456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557c5feb1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557c5feb4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa887533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa88758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa887533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa88751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c5fe4a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557c5fe4a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557c5fe2ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557c5fade166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557c5fadde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa88751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa88751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa88751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c5faddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (3197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/32702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574710b356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005574710b0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005574710b3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfb7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfb7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfb7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfb7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055747104923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557471049086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055747102df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557470cdd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557470cdce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdfb7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfb7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfb7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557470cdcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (3198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5c308356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b5c3080505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b5c3083cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2d9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2d975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2d9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2d96ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5c301923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b5c3019086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b5c2ffdf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b5c2cad166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b5c2cace83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb2d96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2d96ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2d96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5c2cacd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (3199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d466fb156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d466fae505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d466fb1cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e08249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e082a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e08249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e08231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d466f4723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d466f47086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d466f2bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d466bdb166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d466bdae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1e08232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e082330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e082330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d466bdad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (3200 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ce3f9756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556ce3f94505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556ce3f97cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1263505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f126355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1263505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12634ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ce3f2d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556ce3f2d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556ce3f11f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556ce3bc1166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556ce3bc0e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f12634eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12634ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12634ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ce3bc0d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (3201 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557739fa656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557739fa3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557739fa6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff244305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff24435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff244305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2442ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557739f3c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557739f3c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557739f20f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557739bd0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557739bcfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff2442eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2442ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2442ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557739bcfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (3202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i6
# | ...
# `---data was truncated (10240/18619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055964ffd356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055964ffd0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055964ffd3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6377049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63770a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6377049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6377031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055964ff6923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055964ff69086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055964ff4df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055964fbfd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055964fbfce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6377032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63770330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63770330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055964fbfcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (3203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf0f09a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bf0f097505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bf0f09acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9af249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9af2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9af249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9af231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf0f03023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bf0f030086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bf0f014f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bf0ecc4166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bf0ecc3e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc9af232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9af2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9af2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf0ecc3d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (3204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f24829456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f248291505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f248294cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f42e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f42ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f42e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f42e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f24822a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f24822a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f24820ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f247ebe166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f247ebde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5f42e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f42e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f42e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f247ebdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (3205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f67164856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f671645505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f671648cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc9c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc9c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc9c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc9c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6715de23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f6715de086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f6715c2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f671272166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f671271e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc9c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc9c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc9c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f671271d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (3206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587f4d0256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005587f4cff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005587f4d02cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a28333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a28333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a2831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587f4c9823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005587f4c98086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005587f4c7cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005587f492c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005587f492be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5a2831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a2831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a2831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587f492bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (3207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d0d03f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556d0d03c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556d0d03fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb845133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb84518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb845133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb84511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d0cfd523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556d0cfd5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556d0cfb9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556d0cc69166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556d0cc68e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb84511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb84511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb84511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d0cc68d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (3208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565dd66656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565dd663505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565dd666cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc1b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc1b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc1b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc1b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565dd5fc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005565dd5fc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005565dd5e0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005565dd290166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005565dd28fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdc1b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc1b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc1b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565dd28fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (3209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb30c2c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055bb30c29505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055bb30c2ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1aec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1aec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1aec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1aec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb30bc223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055bb30bc2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055bb30ba6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055bb30856166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055bb30855e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe1aec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1aec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1aec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb30855d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (3210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055882f21c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055882f219505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055882f21ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71b6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71b638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71b6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71b631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055882f1b223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055882f1b2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055882f196f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055882ee46166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055882ee45e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f71b631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71b631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71b631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055882ee45d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (3211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056221e0ab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056221e0a8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056221e0abcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6554333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f655438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6554333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f655431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056221e04123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056221e041086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056221e025f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056221dcd5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056221dcd4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f655431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f655431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f655431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056221dcd4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/linker-diagnostic.ll (3212 of 27911)
******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# |  #0 0x00005616c8a1656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005616c8a13505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005616c8a16cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50c5705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50c575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50c5705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50c56ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616c89ac23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005616c89ac086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005616c8990f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005616c8640166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005616c863fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f50c56eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50c56ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50c56ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616c863fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (3213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613f0a1a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613f0a17505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613f0a1acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50c1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50c195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50c1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50c18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613f09b023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613f09b0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613f0994f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613f0644166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613f0643e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f50c18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50c18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50c18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613f0643d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (3214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4f506956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c4f5066505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c4f5069cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72eca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72ecaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72eca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72eca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4f4fff23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c4f4fff086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c4f4fe3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c4f4c93166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c4f4c92e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f72eca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72eca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72eca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4f4c92d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (3215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ec8b6a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563ec8b67505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563ec8b6acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6e1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6e1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6e1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6e1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ec8b0023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563ec8b00086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563ec8ae4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563ec8794166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563ec8793e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd6e1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6e1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6e1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ec8793d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (3216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056486e0ed56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056486e0ea505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056486e0edcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc4de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc4dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc4de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc4de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056486e08323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056486e083086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056486e067f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056486dd17166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056486dd16e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efc4de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc4de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc4de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056486dd16d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (3217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>
# | ...
# `---data was truncated (10240/22898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e56a23a56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e56a237505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e56a23acab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc63c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc63ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc63c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc63c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e56a1d023d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e56a1d0086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e56a1b4f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e569e64166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e569e63e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcc63c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc63c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc63c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e569e63d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (3218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9e989856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e9e9895505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e9e9898cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a70933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a7098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a70933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a7091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9e982e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e9e982e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e9e9812f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e9e94c2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e9e94c1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6a7091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a7091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a7091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9e94c1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (3219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565381e956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005565381e6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005565381e9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8e2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8e218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8e2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8e211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055653817f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055653817f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556538163f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556537e13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556537e12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa8e211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8e211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8e211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556537e12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (3220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llv
# | ...
# `---data was truncated (10240/59779) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e0734656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560e07343505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560e07346cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9237533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f923758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9237533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f923751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e072dc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560e072dc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560e072c0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560e06f70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560e06f6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f923751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f923751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f923751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e06f6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (3221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/10610) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec6984756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ec69844505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ec69847cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69cfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69cfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69cfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69cfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec697dd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ec697dd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ec697c1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ec69471166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ec69470e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f69cfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69cfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69cfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec69470d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (3222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a701c0656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a701c03505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a701c06cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbebf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbebf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbebf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbebf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a701b9c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a701b9c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a701b80f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a701830166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a70182fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbebf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbebf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbebf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a70182fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (3223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 
# | ...
# `---data was truncated (10240/11237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c703e9056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c703e8d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c703e90cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3806449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3806449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3806431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c703e2623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c703e26086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c703e0af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c703aba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c703ab9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3806432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c703ab9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (3224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e17e14956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e17e146505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e17e149cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f996ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f996ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f996ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f996ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e17e0df23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e17e0df086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e17e0c3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e17dd73166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e17dd72e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f996ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f996ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f996ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e17dd72d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (3225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x
# | ...
# `---data was truncated (10240/15375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed659cd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ed659ca505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ed659cdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9cb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9cb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9cb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9cb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed6596323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ed65963086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ed65947f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ed655f7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ed655f6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa9cb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9cb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9cb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed655f6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (3226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cd754156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560cd753e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560cd7541cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9130249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91302a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9130249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9130231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cd74d723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560cd74d7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560cd74bbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560cd716b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560cd716ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9130232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91302330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91302330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cd716ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (3227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b7466f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557b7466c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557b7466fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed28049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed280a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed28049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed28031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b7460523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557b74605086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557b745e9f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557b74299166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557b74298e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fed28032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed280330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed280330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b74298d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (3228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/22375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af32fb656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af32fb3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af32fb6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31aa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31aa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31aa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31aa403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af32f4c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af32f4c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af32f30f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af32be0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af32bdfe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f31aa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31aa4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31aa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af32bdfd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (3229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2d175556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f2d1752505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f2d1755cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea14b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea14b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea14b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea14aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2d16eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f2d16eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f2d16cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f2d137f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f2d137ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fea14aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea14aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea14aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2d137ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (3230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fec02c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555fec029505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555fec02ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb96249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb962a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb96249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb96231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555febfc223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555febfc2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555febfa6f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555febc56166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555febc55e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdb96232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb962330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb962330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555febc55d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (3231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c918b1e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c918b1b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c918b1ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cf3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cf32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cf3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cf3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c918ab423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c918ab4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c918a98f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c918748166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c918747e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4cf3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cf32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cf32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c918747d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (3232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1,
# | ...
# `---data was truncated (10240/28354) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578c69b356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005578c69b0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005578c69b3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3898e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3898ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3898e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3898e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578c694923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005578c6949086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005578c692df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005578c65dd166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005578c65dce83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3898e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3898e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3898e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578c65dcd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (3233 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %x.addr, align 8
# |   %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>
# |   ret <8 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   %p.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   store <8 x i8> %p, ptr %p.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %p.addr, align 8
# |   %mask = and <8 x i8> %1, splat (i8 7)
# |   %shuf_idx = extractelement <8 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <8 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <8 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <8 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <8 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <8 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <8 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <8 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   ret <8 x i8> %shuf_ins21
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %x.addr, align 16
# |   %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
# |   ret <16 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %p.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store <16 x i8> %p, ptr %p.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %p.addr, align 16
# |   %mask = and <16 x i8> %1, splat (i8 15)
# |   %shuf_idx = extractelement <16 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <16 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <16 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <16 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <16 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <16 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <16 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <16 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   %shuf_idx22 = extractelement <16 x i8> %mask, i64 8
# |   %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22
# |   %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8
# |   %shuf_idx25 = extractelement <16 x i8> %mask, i64 9
# |   %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25
# |   %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9
# |   %shuf_idx28 = extractelement <16 x i8> %mask, i64 10
# |   %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28
# |   %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10
# |   %shuf_idx31 = extractelement <16 x i8> %mask, i64 11
# |   %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31
# |   %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11
# |   %shuf_idx34 = extractelement <16 x i8> %mask, i64 12
# |   %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34
# |   %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12
# |   %shuf_idx37 = extractelement <16 x i8> %mask, i64 13
# |   %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37
# |   %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13
# |   %shuf_idx40 = extractelement <16 x i8> %mask, i64 14
# |   %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40
# |   %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14
# |   %shuf_idx43 = extractelement <16 x i8> %mask, i64 15
# |   %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43
# |   %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15
# |   ret <16 x i8> %shuf_ins45
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1dde4656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c1dde43505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c1dde46cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc968f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc968f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc968f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc968f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1ddddc23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c1ddddc086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c1dddc0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c1dda70166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c1dda6fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fc968f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc968f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc968f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1dda6fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (3234 of 27911)
******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# |  #0 0x0000558e7fd6156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558e7fd5e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558e7fd61cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e33449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e334a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e33449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e33431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e7fcf723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558e7fcf7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558e7fcdbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558e7f98b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558e7f98ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6e33432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e334330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e334330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e7f98ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (3235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/12648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ff282556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557ff2822505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557ff2825cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d42849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d428a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d42849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d42831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ff27bb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557ff27bb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557ff279ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557ff244f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557ff244ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0d42832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d428330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d428330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ff244ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (3236 of 27911)
******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | declare noundef zeroext i1 @_Z1av() #1
# | 
# | declare noundef zeroext i1 @_Z1bv() #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.expect.i64(i64, i64) #2
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true)
# |   br i1 %call.expval, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true)
# |   br i1 %call1.expval, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i1 @llvm.expect.i1(i1, i1) #2
# | 
# | declare noundef zeroext i1 @_Z1cv() #1
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1cv()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:                                          ; preds = %lor.lhs.false
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %lor.end
# | 
# | lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
# |   %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.end
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %if.then, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %if.then, label %lor.lhs.false2
# | 
# | lor.lhs.false2:                                   ; preds = %lor.lhs.false
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.lhs.false2, %lor.lhs.false, %entry
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.lhs.false2
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %dec = add nsw i32 %2, -1
# |   store i32 %dec, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:     
# | ...
# `---data was truncated (10240/28468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# |  #0 0x00005560f059956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005560f0596505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005560f0599cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b0d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b0d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b0d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b0d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560f052f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005560f052f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005560f0513f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005560f01c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005560f01c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9b0d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b0d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b0d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560f01c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (3237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16
# | ...
# `---data was truncated (10240/15367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c03c6e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563c03c6b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563c03c6ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d44b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d44b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d44b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d44b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c03c0423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563c03c04086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563c03be8f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563c03898166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563c03897e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5d44b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d44b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d44b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c03897d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (3238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580ac9d856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005580ac9d5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005580ac9d8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd499733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd49978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd499733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd49971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580ac96e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005580ac96e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005580ac952f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005580ac602166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005580ac601e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd49971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd49971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd49971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580ac601d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (3239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056160ae2756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056160ae24505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056160ae27cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0cf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0cf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0cf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0cf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056160adbd23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056160adbd086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056160ada1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056160aa51166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056160aa50e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe0cf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0cf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0cf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056160aa50d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (3240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056238190f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056238190c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056238190fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e53733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e5378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e53733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e5371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623818a523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005623818a5086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562381889f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562381539166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562381538e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0e5371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e5371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e5371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562381538d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (3241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055731c73956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055731c736505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055731c739cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff27db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff27db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff27db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff27db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055731c6cf23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055731c6cf086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055731c6b3f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055731c363166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055731c362e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff27db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff27db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff27db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055731c362d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (3242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d847e556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000559d847e2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000559d847e5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4ca733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4ca78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4ca733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4ca71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d8477b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000559d8477b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000559d8475ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000559d8440f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000559d8440ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe4ca71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4ca71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4ca71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d8440ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (3243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd3b6cb56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055dd3b6c8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055dd3b6cbcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb073933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb07398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb073933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb07391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd3b66123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055dd3b661086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055dd3b645f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055dd3b2f5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055dd3b2f4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb07391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb07391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb07391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd3b2f4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (3244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af4de6256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055af4de5f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055af4de62cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2cba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2cbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2cba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2cba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af4ddf823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055af4ddf8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055af4dddcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055af4da8c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055af4da8be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff2cba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2cba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2cba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af4da8bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (3245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2
# | ...
# `---data was truncated (10240/32198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575ea5f556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005575ea5f2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005575ea5f5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fd7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fd738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fd7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fd731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575ea58b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005575ea58b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005575ea56ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005575ea21f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005575ea21ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4fd731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fd731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fd731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575ea21ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (3246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b9ca5656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555b9ca53505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555b9ca56cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b48c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b48ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b48c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b48c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b9c9ec23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555b9c9ec086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555b9c9d0f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555b9c680166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555b9c67fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4b48c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b48c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b48c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b9c67fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (3247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/18867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056202330256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005620232ff505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562023302cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f6c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f6c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f6c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f6c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056202329823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562023298086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056202327cf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562022f2c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562022f2be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6f6c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f6c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f6c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562022f2bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (3248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5b42fc56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5b42f9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5b42fccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb31841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3184725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb31841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb318403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5b429223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5b4292086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5b4276f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5b3f26166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5b3f25e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb318404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3184050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3184050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5b3f25d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (3249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 
# | ...
# `---data was truncated (10240/24206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056523d49956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000056523d496505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000056523d499cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb27a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb27a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb27a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb27a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056523d42f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056523d42f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000056523d413f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000056523d0c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056523d0c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb27a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb27a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb27a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056523d0c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (3250 of 27911)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.funcref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f281c3856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f281c35505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f281c38cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9538933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f953898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9538933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f953891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f281bce23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f281bce086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f281bb2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f281862166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f281861e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f953891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f953891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f953891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f281861d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (3251 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |  
# | ...
# `---data was truncated (10240/15969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f78a1e956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f78a1e6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f78a1e9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6218849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6218849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6218831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f78a17f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f78a17f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f78a163f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f789e13166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f789e12e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f6218832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62188330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f789e12d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (3252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/32701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055899ca5156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055899ca4e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055899ca51cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d42d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d42d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d42d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d42d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055899c9e723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055899c9e7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055899c9cbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055899c67b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055899c67ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7d42d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d42d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d42d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055899c67ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (3253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562aecee656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000562aecee3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000562aecee6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5760849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57608a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5760849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5760831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aece7c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000562aece7c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000562aece60f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000562aecb10166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000562aecb0fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f5760832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57608330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57608330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562aecb0fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (3254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055660641456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556606411505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556606414cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d07649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d076a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d07649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d07631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566063aa23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005566063aa086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055660638ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055660603e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055660603de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f1d07632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d076330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d076330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055660603dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (3255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eabd6256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561eabd5f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561eabd62cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7255849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72558a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7255849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7255831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eabcf823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561eabcf8086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561eabcdcf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561eab98c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000561eab98be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7255832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72558330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72558330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eab98bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (3256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b1777856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000564b17775505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000564b17778cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3be705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3be75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3be705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3be6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b1770e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000564b1770e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000564b176f2f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000564b173a2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000564b173a1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff3be6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3be6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3be6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b173a1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (3257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i
# | ...
# `---data was truncated (10240/14325) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7bb32156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7bb31e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7bb321cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40c1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40c158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40c1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40c151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7bb2b723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7bb2b7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7bb29bf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7baf4b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7baf4ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f40c151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40c151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40c151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7baf4ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (3258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558217ce856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558217ce5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558217ce8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5aa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5aa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5aa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5aa431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558217c7e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558217c7e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558217c62f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558217912166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558217911e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd5aa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5aa4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5aa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558217911d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (3259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e14017256b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e14016f505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e140172cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e36c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e36c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e36c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e36c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e14010823d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e140108086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e1400ecf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e13fd9c166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e13fd9be83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4e36c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e36c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e36c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e13fd9bd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (3260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055564bcb456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055564bcb1505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055564bcb4cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8014933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8014933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055564bc4a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055564bc4a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055564bc2ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055564b8de166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055564b8dde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f801491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055564b8ddd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (3261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 
# | ...
# `---data was truncated (10240/10944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8fb95556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055d8fb952505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055d8fb955cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd44fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd44fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd44fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd44fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8fb8eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055d8fb8eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055d8fb8cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055d8fb57f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055d8fb57ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fd44fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd44fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd44fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8fb57ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (3262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a130f756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556a130f4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556a130f7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86d5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86d58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86d5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86d5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a1308d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556a1308d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556a13071f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556a12d21166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556a12d20e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f86d5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86d58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86d58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a12d20d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (3263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f28962b56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055f289628505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055f28962bcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79b7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79b70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79b7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79b7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2895c123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055f2895c1086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055f2895a5f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055f289255166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055f289254e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f79b7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79b70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79b70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f289254d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (3264 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# |  #0 0x000055a46f35456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a46f351505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a46f354cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0acee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aceea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0acee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0acee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a46f2ea23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a46f2ea086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a46f2cef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a46ef7e166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a46ef7de83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f0acee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0acee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0acee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a46ef7dd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (3265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594fa20c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005594fa209505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005594fa20ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe73cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe73cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe73cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe73cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594fa1a223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005594fa1a2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005594fa186f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005594f9e36166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005594f9e35e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe73cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe73cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe73cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594f9e35d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (3266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b1679f56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556b1679c505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556b1679fcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87db849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87db8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87db849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87db831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b1673523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556b16735086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556b16719f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556b163c9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556b163c8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f87db832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87db8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87db8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b163c8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (3267 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   ret <8 x half> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   ret <4 x float> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca half, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %3, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %3, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2,
# | ...
# `---data was truncated (10240/17297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000563d54f4156b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000563d54f3e505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000563d54f41cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbed0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbed0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbed0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbed0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d54ed723d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000563d54ed7086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000563d54ebbf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000563d54b6b166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000563d54b6ae83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbed0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbed0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbed0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d54b6ad71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (3268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561632dad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561632daa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561632dadcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3af533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3af58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3af533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3af51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561632d4323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561632d43086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561632d27f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005616329d7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005616329d6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa3af51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3af51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3af51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616329d6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (3269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585f36bf56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005585f36bc505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005585f36bfcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d25305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d2535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d25305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d252ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585f365523d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005585f3655086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005585f3639f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005585f32e9166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005585f32e8e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f4d252eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d252ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d252ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585f32e8d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (3270 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573be85556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005573be852505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005573be855cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b7ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b7ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b7ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b7ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573be7eb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005573be7eb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005573be7cff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005573be47f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005573be47ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f3b7ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b7ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b7ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573be47ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (3271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572954d956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005572954d6505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005572954d9cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf3cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf3cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf3cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf3cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055729546f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055729546f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557295453f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557295103166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557295102e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fcf3cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf3cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf3cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557295102d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (3272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7bf05756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055e7bf054505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055e7bf057cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cffe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cffea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cffe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cffe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7befed23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055e7befed086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055e7befd1f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055e7bec81166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055e7bec80e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2cffe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cffe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cffe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7bec80d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (3273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/41102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebe899056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055ebe898d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055ebe8990cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f807f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f807f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f807f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f807f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebe892623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055ebe8926086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055ebe890af39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055ebe85ba166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055ebe85b9e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f807f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f807f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f807f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebe85b9d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (3274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, al
# | ...
# `---data was truncated (10240/13263) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613b1c1c56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005613b1c19505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005613b1c1ccab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9210333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f921038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9210333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f921031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613b1bb223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005613b1bb2086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005613b1b96f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005613b1846166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005613b1845e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f921031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f921031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f921031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613b1845d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (3275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   
# | ...
# `---data was truncated (10240/12381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da213ce56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055da213cb505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055da213cecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ea1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ea118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ea1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ea111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da2136423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055da21364086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055da21348f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055da20ff8166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055da20ff7e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f7ea111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ea111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ea111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da20ff7d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (3276 of 27911)
******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20       -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone       | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.MyTask = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { ptr }
# | %"struct.std::suspend_always" = type { i8 }
# | %struct.Awaiter = type { ptr }
# | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" }
# | 
# | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15await_transformERKi = comdat any
# | 
# | $_ZN7Awaiter11await_readyEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any
# | 
# | $_ZN7Awaiter12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type13final_suspendEv = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | @g_array = global [32 x i32] zeroinitializer, align 16
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local ptr @_Z6FooBarv() #0 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6
# |   store ptr @_Z6FooBarv.resume, ptr %call, align 8
# |   %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup
# |   %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8
# |   store ptr %0, ptr %destroy.addr, align 8
# |   %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18
# |   %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24
# |   %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32
# |   %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40
# |   %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48
# |   %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56
# |   %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19
# |   %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16
# |   %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call1, ptr %coerce.dive2, align 8
# |   call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   br i1 %call3, label %init.ready, label %CoroSave
# | 
# | CoroSave:                                         ; preds = %entry
# |   %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 0, ptr %index.addr39, align 1
# |   call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | init.ready:                                       ; preds = %entry
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   store ptr @g_array, ptr %__range1.reload.addr, align 8
# |   store ptr @g_array, ptr %__begin1.reload.addr, align 8
# |   store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %init.ready
# |   %1 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %2 = load ptr, ptr %__end1.reload.addr, align 8
# |   %cmp = icmp ne ptr %1, %2
# |   br i1 %cmp, label %for.body, label %coro.final
# | 
# | for.body:                                         ; preds = %for.cond
# |   %3 = load ptr, ptr %__begin1.reload.addr, align 8
# |   store ptr %3, ptr %x.reload.addr, align 8
# |   %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2
# |   %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4)
# |   %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0
# |   store ptr %call5, ptr %coerce.dive6, align 8
# |   %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   br i1 %call7, label %await.ready, label %CoroSave27
# | 
# | CoroSave27:                                       ; preds = %for.body
# |   %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 1, ptr %index.addr40, align 1
# |   %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call)
# |   %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0
# |   %7 = load ptr, ptr %6, align 8
# |   call void %7(ptr %5)
# |   br label %AfterCoroEnd
# | 
# | await.ready:                                      ; preds = %for.body
# |   call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   %cond = icmp eq i32 0, 0
# |   %cond26 = icmp eq i32 0, 0
# |   br i1 %cond26, label %for.inc, label %coro.final
# | 
# | for.inc:                                          ; preds = %await.ready
# |   %8 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1
# |   store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8
# |   br label %for.cond
# | 
# | coro.final:                                       ; preds = %await.ready, %for.cond
# |   call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7
# |   %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   br i1 %call20, label %final.ready, label %CoroSave31
# | 
# | CoroSave31:                                       ; preds = %coro.final
# |   store ptr null, ptr %call, align 8
# |   call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | final.ready:                                      ; preds = %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   %9 = icmp ne ptr %call, null
# |   br i1 %9, label %coro.free, label %AfterCoroEnd
# | 
# | coro.free:                                        ; preds = %final.ready
# |   call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7
# |   br label %AfterCoroEnd
# | 
# | AfterCoroEnd:                                     ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave
# |   %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0
# |   %10 = load ptr, ptr %coerce.dive25, align 8
# |   ret ptr %10
# | }
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %this.addr = alloca ptr, align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call, ptr %coerce.dive2, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false)
# |   %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0
# |   %0 = load ptr, ptr %coerce.dive4, align 8
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret i1 false
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 {
# | entry:
# |   %.addr = alloca ptr, align 8
# |   %.addr1 = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %0, ptr %.addr, align 8
# |   store ptr %1, ptr %.addr1, align 8
# |   %2 = load ptr, ptr %.addr, align 8
# |   %3 = load ptr, ptr %.addr1, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7
# |   
# | ...
# `---data was truncated (10240/37953) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# |  #0 0x00005616aa93d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005616aa93a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005616aa93dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe178f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe178f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe178f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe178eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616aa8d323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005616aa8d3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005616aa8b7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005616aa567166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005616aa566e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe178eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe178eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe178eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616aa566d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (3277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 
# | ...
# `---data was truncated (10240/12465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5bae1e56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055a5bae1b505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055a5bae1ecab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa04fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa04fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa04fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa04fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5badb423d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055a5badb4086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055a5bad98f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055a5baa48166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055a5baa47e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fa04fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa04fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa04fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5baa47d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (3278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586bbd6d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005586bbd6a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005586bbd6dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe731f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe731f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe731f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe731f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586bbd0323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005586bbd03086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005586bbce7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005586bb997166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005586bb996e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fe731f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe731f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe731f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586bb996d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (3279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be1261756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055be12614505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055be12617cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f461cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f461cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f461cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f461caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be125ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055be125ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055be12591f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055be12241166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055be12240e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f461caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f461caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f461caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be12240d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (3280 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f699d756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000556f699d4505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000556f699d7cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe8c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe8c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe8c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe8c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f6996d23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000556f6996d086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000556f69951f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000556f69601166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000556f69600e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007efe8c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe8c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe8c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f69600d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (3281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645d9aab56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005645d9aa8505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005645d9aabcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a29733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a2978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a29733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a2971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645d9a4123d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005645d9a41086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005645d9a25f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005645d96d5166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005645d96d4e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f2a2971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a2971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a2971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645d96d4d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (3282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bc29a856b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000560bc29a5505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000560bc29a8cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9bf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9bf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9bf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9bf031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bc293e23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000560bc293e086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000560bc2922f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000560bc25d2166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000560bc25d1e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007ff9bf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9bf0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9bf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bc25d1d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (3283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580b5ed556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005580b5ed2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005580b5ed5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580b5e6b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005580b5e6b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005580b5e4ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005580b5aff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005580b5afee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fbeb911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580b5afed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-loongarch.c (3284 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "loongarch32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 4, ptr %res, align 4
# |   store volatile i32 5, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055895a83556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055895a832505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055895a835cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd35b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd35b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd35b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd35b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055895a7cb23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055895a7cb086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055895a7aff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055895a45f166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055895a45ee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fdd35b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd35b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd35b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055895a45ed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (3285 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %
# | ...
# `---data was truncated (10240/15051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b089dc356b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b089dc0505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b089dc3cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03a2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03a258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03a2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03a251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b089d5923d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b089d59086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b089d3df39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b0899ed166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b0899ece83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f03a251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03a251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03a251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0899ecd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (3286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e44a1756b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000555e44a14505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000555e44a17cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43ebf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e449ad23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000555e449ad086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000555e44991f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000555e44641166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000555e44640e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f43ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e44640d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (3287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056158269956b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561582696505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561582699cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7972333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f797238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7972333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f797231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056158262f23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000056158262f086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561582613f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005615822c3166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005615822c2e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f797231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f797231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f797231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615822c2d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (3288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574352c656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005574352c3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005574352c6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6c8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6c898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6c8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6c891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055743525c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055743525c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557435240f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557434ef0166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557434eefe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb6c891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6c891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6c891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557434eefd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (3289 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5)
# |   %7 = extractvalue { i32, <4 x i32> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <4 x i32> } %6, 1
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# | 
# | ...
# `---data was truncated (10240/11454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bcc3fd56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000557bcc3fa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000557bcc3fdcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8771d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8771d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8771d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8771d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bcc39323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000557bcc393086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000557bcc377f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000557bcc027166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000557bcc026e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8771d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8771d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8771d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bcc026d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (3290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607b915d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005607b915a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005607b915dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bff249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bff2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bff249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bff231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607b90f323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005607b90f3086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005607b90d7f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005607b8d87166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005607b8d86e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f8bff232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bff2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bff2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607b8d86d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (3291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3,
# | ...
# `---data was truncated (10240/29443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2380d556b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b2380d2505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b2380d5cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f386f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f386f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f386f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f386f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b23806b23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b23806b086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b23804ff39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b237cff166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b237cfee83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f386f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f386f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f386f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b237cfed71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (3292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055779ec9456b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055779ec91505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055779ec94cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d14533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d1458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d14533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d1451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055779ec2a23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055779ec2a086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055779ec0ef39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055779e8be166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055779e8bde83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f9d1451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d1451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d1451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055779e8bdd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (3293 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# |  #0 0x000055b6107ac56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055b6107a9505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055b6107accab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47cd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47cd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47cd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47cd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b61074223d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055b610742086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055b610726f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055b6103d6166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055b6103d5e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f47cd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47cd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47cd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6103d5d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (3294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5f01ad56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x000055c5f01aa505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x000055c5f01adcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78b8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78b8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78b8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78b8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5f014323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x000055c5f0143086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x000055c5f0127f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x000055c5efdd7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000055c5efdd6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f78b8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78b8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78b8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5efdd6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (3295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633ec43056b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x00005633ec42d505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x00005633ec430cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb175533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb17558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb175533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb17551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633ec3c623d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x00005633ec3c6086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x00005633ec3aaf39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x00005633ec05a166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x00005633ec059e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007fb17551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb17551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb17551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633ec059d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (3296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f2c89d56b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000558f2c89a505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000558f2c89dcab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51aa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51aa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51aa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51aa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f2c83323d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000558f2c833086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000558f2c817f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000558f2c4c7166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x0000558f2c4c6e83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f51aa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51aa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51aa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f2c4c6d71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (3619 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561510ce656b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2356b)
# |  #1 0x0000561510ce3505 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20505)
# |  #2 0x0000561510ce6cab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19a0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561510c7c23d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b923d)
# |  #8 0x0000561510c7c086 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9086)
# |  #9 0x0000561510c60f39 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df39)
# | #10 0x0000561510910166 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d166)
# | #11 0x000056151090fe83 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce83)
# | #12 0x00007f19a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19a08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056151090fd71 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd71)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. 
********************
Failed Tests (3297):
  Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c
  Clang :: CodeGen/2005-09-24-AsmUserPrefix.c
  Clang :: CodeGen/2008-07-17-no-emit-on-error.c
  Clang :: CodeGen/AArch64/atomic-hint-template.cpp
  Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c
  Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c
  Clang :: CodeGen/AArch64/fp8-cast.c
  Clang :: CodeGen/AArch64/fp8-extract.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/neon-2velem.c
  Clang :: CodeGen/AArch64/neon-3v.c
  Clang :: CodeGen/AArch64/neon-dot-product.c
  Clang :: CodeGen/AArch64/neon-extract.c
  Clang :: CodeGen/AArch64/neon-fma.c
  Clang :: CodeGen/AArch64/neon-fp16fml.c
  Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon-intrinsics.c
  Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c
  Clang :: CodeGen/AArch64/neon-misc-constrained.c
  Clang :: CodeGen/AArch64/neon-misc.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c
  Clang :: CodeGen/AArch64/neon-shifts.c
  Clang :: CodeGen/AArch64/neon-tbl.c
  Clang :: CodeGen/AArch64/neon-vcmla.c
  Clang :: CodeGen/AArch64/neon-vcombine.c
  Clang :: CodeGen/AArch64/neon-vget-hilo.c
  Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c
  Clang :: CodeGen/AArch64/neon/add.c
  Clang :: CodeGen/AArch64/neon/bf16-getset.c
  Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c
  Clang :: CodeGen/AArch64/neon/f16-getset.c
  Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiply.c
  Clang :: CodeGen/AArch64/neon/getset.c
  Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon/intrinsics.c
  Clang :: CodeGen/AArch64/neon/load.c
  Clang :: CodeGen/AArch64/neon/perm.c
  Clang :: CodeGen/AArch64/neon/rounding-v8.5.c
  Clang :: CodeGen/AArch64/neon/rounding.c
  Clang :: CodeGen/AArch64/neon/store.c
  Clang :: CodeGen/AArch64/neon/subtraction.c
  Clang :: CodeGen/AArch64/neon/vpaddl.c
  Clang :: CodeGen/AArch64/neon/widen.c
  Clang :: CodeGen/AArch64/poly128.c
  Clang :: CodeGen/AArch64/poly64.c
  Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
  Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
  Clang :: CodeGen/AArch64/sve-vector-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vector-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vector-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c
  Clang :: CodeGen/AArch64/sve-vls-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vls-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vls-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c
  Clang :: CodeGen/AArch64/sve/addv.c
  Clang :: CodeGen/AArch64/sve/andv.c
  Clang :: CodeGen/AArch64/sve/dup.c
  Clang :: CodeGen/AArch64/sve/eorv.c
  Clang :: CodeGen/AArch64/sve/len.c
  Clang :: CodeGen/AArch64/sve/maxnmv.c
  Clang :: CodeGen/AArch64/sve/maxv.c
  Clang :: CodeGen/AArch64/sve/minnmv.c
  Clang :: CodeGen/AArch64/sve/minv.c
  Clang :: CodeGen/AArch64/sve/nand.c
  Clang :: CodeGen/AArch64/sve/nor.c
  Clang :: CodeGen/AArch64/sve/orn.c
  Clang :: CodeGen/AArch64/sve/orv.c
  Clang :: CodeGen/AArch64/sve/pfalse.c
  Clang :: CodeGen/AArch64/sve/recpe.c
  Clang :: CodeGen/AArch64/sve/recps.c
  Clang :: CodeGen/AArch64/sve/rsqrte.c
  Clang :: CodeGen/AArch64/sve/rsqrts.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
  Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
  Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
  Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/builtin-cpu-is.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c
  Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c
  Clang :: CodeGen/RISCV/riscv-xcvalu.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c
  Clang :: CodeGen/RISCV/rvp-intrinsics.c
  Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/SystemZ/zvector.c
  Clang :: CodeGen/WebAssembly/builtins-table-externref.c
  Clang :: CodeGen/WebAssembly/builtins-table-funcref.c
  Clang :: CodeGen/X86/avx-cmp-builtins.c
  Clang :: CodeGen/X86/avx-shuffle-builtins.c
  Clang :: CodeGen/X86/bfloat16-convert-half.c
  Clang :: CodeGen/X86/sse.c
  Clang :: CodeGen/aapcs-bitfield.c
  Clang :: CodeGen/arm-bf16-convert-intrinsics.c
  Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c
  Clang :: CodeGen/arm-bf16-params-returns.c
  Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/arm-cde-gpr.c
  Clang :: CodeGen/arm-cde-reinterpret.c
  Clang :: CodeGen/arm-cde-vec.c
  Clang :: CodeGen/arm-cde-vfp.c
  Clang :: CodeGen/arm-crc32.c
  Clang :: CodeGen/arm-mfp8.c
  Clang :: CodeGen/arm-mve-intrinsics/absneg.c
  Clang :: CodeGen/arm-mve-intrinsics/admin.c
  Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/compare.c
  Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp
  Clang :: CodeGen/arm-mve-intrinsics/dup.c
  Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c
  Clang :: CodeGen/arm-mve-intrinsics/idup.c
  Clang :: CodeGen/arm-mve-intrinsics/load-store.c
  Clang :: CodeGen/arm-mve-intrinsics/predicates.c
  Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c
  Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c
  Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c
  Clang :: CodeGen/arm-mve-intrinsics/ternary.c
  Clang :: CodeGen/arm-mve-intrinsics/vabavq.c
  Clang :: CodeGen/arm-mve-intrinsics/vabdq.c
  Clang :: CodeGen/arm-mve-intrinsics/vadc.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddv.c
  Clang :: CodeGen/arm-mve-intrinsics/vandq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbicq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vclz.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c
  Clang :: CodeGen/arm-mve-intrinsics/veorq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vld24.c
  Clang :: CodeGen/arm-mve-intrinsics/vldr.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminvq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovl.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vornq.c
  Clang :: CodeGen/arm-mve-intrinsics/vorrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrev.c
  Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrnd.c
  Clang :: CodeGen/arm-mve-intrinsics/vshlc.c
  Clang :: CodeGen/arm-mve-intrinsics/vsubq.c
  Clang :: CodeGen/arm-neon-directed-rounding-constrained.c
  Clang :: CodeGen/arm-neon-directed-rounding.c
  Clang :: CodeGen/arm-neon-dot-product.c
  Clang :: CodeGen/arm-neon-endianness.c
  Clang :: CodeGen/arm-neon-fma.c
  Clang :: CodeGen/arm-neon-numeric-maxmin.c
  Clang :: CodeGen/arm-neon-shifts.c
  Clang :: CodeGen/arm-neon-vcadd.c
  Clang :: CodeGen/arm-neon-vcvtX.c
  Clang :: CodeGen/arm-neon-vget.c
  Clang :: CodeGen/arm-neon-vld.c
  Clang :: CodeGen/arm-neon-vst.c
  Clang :: CodeGen/arm-poly-add.c
  Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c
  Clang :: CodeGen/arm-vector_type-params-returns.c
  Clang :: CodeGen/arm64-crc32.c
  Clang :: CodeGen/arm64-lanes.c
  Clang :: CodeGen/arm64_vcopy.c
  Clang :: CodeGen/arm64_vcreate.c
  Clang :: CodeGen/arm64_vdupq_n_f64.c
  Clang :: CodeGen/arm_acle.c
  Clang :: CodeGen/arm_acle_swp.c
  Clang :: CodeGen/arm_neon_intrinsics.c
  Clang :: CodeGen/attr-counted-by-issue200014.c
  Clang :: CodeGen/builtin-align.c
  Clang :: CodeGen/builtins-arm-exclusive.c
  Clang :: CodeGen/builtins-arm.c
  Clang :: CodeGen/builtins-arm64.c
  Clang :: CodeGen/builtins-loongarch.c
  Clang :: CodeGen/builtins-riscv.c
  Clang :: CodeGen/cx-complex-range-real.c
  Clang :: CodeGen/cx-complex-range.c
  Clang :: CodeGen/distributed-thin-lto/backend-skip.ll
  Clang :: CodeGen/distributed-thin-lto/basic.ll
  Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll
  Clang :: CodeGen/distributed-thin-lto/cfi.ll
  Clang :: CodeGen/distributed-thin-lto/newpm.ll
  Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll
  Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
  Clang :: CodeGen/linker-diagnostic.ll
  Clang :: CodeGen/memcmp-inline-builtin-to-asm.c
  Clang :: CodeGen/mozilla-ms-inline-asm.c
  Clang :: CodeGen/packed-structure.c
  Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
  Clang :: CodeGen/thinlto-funcattr-prop.ll
  Clang :: CodeGen/thinlto-multi-module.ll
  Clang :: CodeGen/thinlto-opaque-typed-mix.ll
  Clang :: CodeGen/thinlto_backend.ll
  Clang :: CodeGen/thinlto_backend_local_name_conflict.ll
  Clang :: CodeGen/thinlto_embed_bitcode.ll
  Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
  Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
  Clang :: CodeGenCXX/attr-musttail.cpp
  Clang :: CodeGenCXX/ctor-globalopt.cpp
  Clang :: CodeGenCXX/inline-then-fold-variadics.cpp
  Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll
  Clang :: CodeGenCXX/virtual-base-ctor.cpp
  Clang :: CodeGenCoroutines/coro-gro4.cpp
  Clang :: CodeGenCoroutines/pr65054.cpp
  Clang :: CodeGenHIP/offload-pgo-sections.hip
  Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
  Clang :: Modules/pr93497.cppm


Testing Time: 159.68s

Total Discovered Tests: 55927
  Skipped          :    37 (0.07%)
  Unsupported      :  1675 (2.99%)
  Passed           : 50889 (90.99%)
  Expectedly Failed:    29 (0.05%)
  Failed           :  3297 (5.90%)
FAILED: gen/clang/test/run-lit 
python3 bin/llvm-lit -sv ../../clang/test
ninja: build stopped: subcommand failed.
Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.